JP3850259B2 - Semiconductor chip - Google Patents

Description

【０１０５】
（７）めっきレジスト５４を５％ＮａＯＨで剥離除去した後、そのめっきレジスト下の金属層５２を硝酸および硫酸と過酸化水素の混合液を用いるエッチングにて溶解除去し、金属層５２と電解めっき膜５６からなる厚さ１６μｍの導体回路５８及びバイアホール６０を形成し、第二銅錯体と有機酸とを含有するエッチング液によって、粗化面５８α、６０αを形成する（図１１（Ｄ）参照）。
【０１０６】
（８）次に、バイアホール６０が設けられた層間樹脂絶縁層５０上に、厚さ３５μｍのエポキシ樹脂フィルム（線熱膨張係数４０ｐｐｍ／℃）を貼り付けることにより、接着層８０を形成させる（図１２（Ａ）参照）。本実施例の接着層８０は、線熱膨張係数がＩＣチップ２０および後述する樹脂絶縁層２５０と比較して大きい。しかし、その厚さはＩＣチップ２０および樹脂絶縁層２５０と比較して非常に薄く、また、ＩＣチップ２０と樹脂絶縁層２５０とに挟まれた構造となっている。このため、接着層８０の硬化時、および実装後に熱サイクルを繰り返し受けた場合においても、接着層８０の伸縮の影響を最小限に抑えることができる。
【０１０７】
（９）接着層８０の上に、板状に形成された厚さ５５μｍの後述する絶縁性基板を載置する。続いて、温度５０〜１５０℃まで昇温しながら圧力５ｋｇ／ｃｍ²で真空圧着ラミネートし、樹脂絶縁層２５０を形成する（図１２（Ｂ）参照）。真空圧着時の真空度は、１０ｍｍＨｇである。
【０１０８】
また、線熱膨張係数がＩＣチップ２０（３ｐｐｍ／℃）と外部基板２１０（１５ｐｐｍ／℃）との間の値である樹脂絶縁層２５０（１０ｐｐｍ／℃）を層間樹脂絶縁層５０上に積層することにより、チップサイズパッケージ１０を形成した際に、ＩＣチップ２０と外部基板２１０との間に位置する構造となる。これにより、熱サイクルを繰り返し受けた場合でも、線熱膨張係数の差に起因する層間絶縁層の伸縮を抑制できるため、層間絶縁層に生じる応力を緩和できる。
【０１０９】
（１０）次いで、例えば、ＣＯ₂ガスレーザによって、パルスエネルギー２．０〜１０．０ｍＪ、パルス幅１〜１００μｓ、パルス間隔０．５ｍｓ以上、ショット数３〜５０の条件で、樹脂絶縁層２５０から導体回路５８に至る銅めっきポスト用開口１４８を形成する（図１２（Ｃ）参照）。本実施例では、レーザを用いるため、種々の材質の絶縁性基板に容易に開口を穿設できる。
【０１１０】
（１１）この後、銅めっきポスト用開口１４８内に残留する樹脂をデスミア処理により除去する。ここでは、デスミア処理により樹脂残さを除去したが、過マンガン酸などの酸化剤を用いて樹脂残さを除去することも可能である。
【０１１１】
（１２）樹脂絶縁層２５０および銅めっきポスト用開口１４８の表面に、無電解めっきにより銅めっき膜１５２を形成する（図１３（Ａ）参照）。予め樹脂絶縁層２５０および銅めっきポスト用開口１４８の表層にパラジウム触媒（アトテック製）などを付与させて、無電解めっき液に５〜６０分間浸漬させることにより、０．１〜５μｍの範囲でめっき膜である金属層１５２を設けた。その一例として、
〔無電解めっき水溶液〕
ＮｉＳＯ₄ ０．００３ ｍｏｌ／ｌ
酒石酸 ０．２００ ｍｏｌ／ｌ
硫酸銅 ０．０３０ ｍｏｌ／ｌ
ＨＣＨＯ ０．０５０ ｍｏｌ／ｌ
ＮａＯＨ ０．１００ ｍｏｌ／ｌ
α、α′−ビピルジル １００ ｍｇ／ｌ
ポリエチレングリコール（ＰＥＧ） ０．１０ ｇ／ｌ
３４℃の液温度で４０分間浸漬させた。
【０１１２】
（１３）次に、この銅めっき膜１５２上に、例えばスピンコートにより市販の感光性ドライフィルムを貼り付け、フォトマスクフィルムを載置して、１００ｍＪ／ｃｍ²で露光した後、０．８％炭酸ナトリウムで現像処理し、厚さ１５μｍのめっきレジスト１５４を設ける。次に、以下の条件で電解めっきを施して、電解銅めっき１５６を形成する（図１３（Ｂ）参照）。なお、電解めっき水溶液中の添加剤は、アトテックジャパン社製のカパラシドＨＬである。
【０１１３】

【０１１４】
（１４）めっきレジスト１５４を５％ＮａＯＨで剥離除去した後、そのめっきレジスト下の金属層１５２を硝酸および硫酸と過酸化水素の混合液を用いるエッチングにて溶解除去し、金属層１５２と電解銅めっき１５６からなる銅めっきポスト１６０を形成し、第二銅錯体と有機酸とを含有するエッチング液によって、粗化面１６０αを形成する（図１３（Ｃ）参照）。ここで、形成される銅めっきポスト１６０の線熱膨張係数は３〜４０ｐｐｍ／℃が望ましい。
【０１１５】
（１５）次に、ジエチレングリコールジメチルエーテル（ＤＭＤＧ）に６０重量％の濃度になるように溶解させた、クレゾールノボラック型エポキシ樹脂（日本化薬社製）のエポキシ基５０％をアクリル化した感光性付与のオリゴマー（分子量４０００）４６．６７重量部、メチルエチルケトンに溶解させた８０重量％のビスフェノールＡ型エポキシ樹脂（油化シェル社製、商品名：エピコート１００１）１５重量部、イミダゾール硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）１．６重量部、感光性モノマーである多官能アクリルモノマー（共栄化学社製、商品名：Ｒ６０４）３重量部、同じく多価アクリルモノマー（共栄化学社製、商品名：ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ社製、商品名：Ｓ−６５）０．７１重量部を容器にとり、攪拌、混合して混合組成物を調整し、この混合組成物に対して光重量開始剤としてベンゾフェノン（関東化学社製）２．０重量部、光増感剤としてのミヒラーケトン（関東化学社製）０．２重量部を加えて、粘度を２５℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物（有機樹脂絶縁材料）を得る。
なお、粘度測定は、Ｂ型粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｒｐｍの場合はローターNo.４、６ｒｐｍの場合はローターNo.３によった。
【０１１６】
（１６）次に、樹脂絶縁層２５０上に、上記ソルダーレジスト組成物を２０μｍの厚さで塗布し、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、ソルダーレジストレジスト開口部のパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト層７０に密着させて１０００ｍＪ／ｃｍ²の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、２００μｍの直径の開口７１を形成する（図１４（Ａ）参照）。また、市販のソルダーレジストを用いてもよい。
【０１１７】
（１７）次に、ソルダーレジスト層（有機樹脂絶縁層）７０を形成したＩＣチップ２０を、塩化ニッケル（２．３×１０^-1ｍｏｌ／ｌ）、次亞リン酸ナトリウム（２．８×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．６×１０^-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無電解ニッケルめっき液に２０分間浸漬して、開口部７１に厚さ５μｍのニッケルめっき層７２を形成する。さらに、その基板を、シアン化金カリウム（７．６×１０^-3ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．２×１０^-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（１．７×１０^-1ｍｏｌ／ｌ）を含む無電解めっき液に８０℃の条件で７．５分間浸漬して、ニッケルめっき層７２上に厚さ０．０３μｍの金めっき層７４を形成することで、銅めっきポスト１６０に半田パッド７５を形成する（図１４（Ｂ）参照）。
【０１１８】
（１８）この後、ソルダーレジスト層７０の開口部７１に、半田ペーストを印刷して、２００℃でリフローすることにより、半田バンプ７６を形成する。これにより、半田バンプ７６を有するチップサイズパッケージ１０を得ることができる（図１５参照）。
【０１１９】
半田ペーストには、Ｓｎ／Ｐｂ、Ｓｎ／Ｓｂ、Ｓｎ／Ａｇ、Ｓｎ／Ａｇ／Ｃｕなどを用いることができる。もちろん、放射線の低α線タイプの半田ペーストを用いてもよい。
【０１２０】
本実施例では、ダイシングなどによって個片に分割された半導体素子２０（図３（Ｂ）参照）を出発材料とした。ここで、個片に分割されていない半導体素子２０（図３（Ａ）参照）を出発材料とし、チップサイズパッケージ形成後、このチップサイズパッケージをダイシングなどによって個片に分割してもよい。
【０１２１】
また、線熱膨張係数がＩＣチップ２０と外部基板２１０との間の値である樹脂絶縁層２５０をＩＣチップ２０と外部基板２１０との間に設けることによって、熱サイクルを繰り返し受けた場合でも、線熱膨張係数の差に起因する層間絶縁層の伸縮を抑制できるため、層間絶縁層に生じる応力を緩和できる。
【０１２２】
[第２実施例]
本発明の第２実施例の改変例に係るチップサイズパッケージについて、図２０を参照して説明する。
図１５を参照して上述した第１実施例に係るチップサイズパッケージでは、樹脂絶縁層２５０に予め硬化させた絶縁基板を用いた。これに対して、第２実施例では、樹脂絶縁層１５０に、後述する熱硬化性樹脂フィルムを用いている。このため、接着層を介在させることなく層間樹脂絶縁層５０の上に樹脂絶縁層１５０を形成している。
【０１２３】
この第２実施例においても、熱硬化性樹脂フィルムとして、硬化した際に、線熱膨張係数が１０〜７０ｐｐｍ／℃となるものを用いることができる。
【０１２４】
なお、樹脂絶縁層１５０は、線熱膨張係数が１０〜７０ｐｐｍ／℃である材質を用いられる。線熱膨張係数が小さいため、熱サイクルを繰り返し受けた際にも、外部基板２１０との熱膨張率差による大きな応力が発生しない。また、樹脂絶縁層１５０の線熱膨張係数を、外部基板未満とすることで、樹脂絶縁層１５０の線熱膨張係数を、外部基板２１０とＩＣチップ２０との中間にすることができ、外部基板２１０とＩＣチップ２０との間の線熱膨張差によって発生する応力を緩和することができる。これにより、樹脂絶縁層１５０のクラックを防止でき、接続信頼性を確保することができる。
【０１２５】
また、第２実施例の半導体チップでは、樹脂絶縁層１５０は、硬化させた絶縁性基板である。つまり、強度の高い絶縁性基板から成る樹脂絶縁層１５０を配設するため、ＩＣチップ２０と外部基板２１０との線熱膨張率差により、銅めっきポスト１６０に高さ方向の力が加わり、銅めっきポスト１５０の側壁からの応力が水平方向に働いても、樹脂絶縁層１５０にクラックを生じることがなく、また、内部で断線が生じることがない。
【０１２６】
この第２実施例のチップサイズパッケージの製造工程について、図１７〜図２０を参照して説明する。ここで、樹脂絶縁層１５０を形成する以前の工程は、図１１及び図１２を参照して上述した第１実施例と同様であるため、図示及び説明を省略する。
【０１２７】
（８）バイアホール６０が設けられた層間樹脂絶縁層５０上に、厚さ７０μｍの板状に形成された後述する熱硬化性樹脂フィルムを積層する。この後、温度５０〜１５０℃まで昇温しながら圧力５ｋｇ／ｃｍ²で真空圧着ラミネートし、硬化させることによって層間樹脂絶縁層１５０を形成する（図１７（Ａ）参照）。真空圧着時の真空度は、１０ｍｍＨｇである。
【０１２８】
また、硬化後の線熱膨張係数がＩＣチップ２０（３ｐｐｍ／℃）と外部基板２１０（１５ｐｐｍ／℃）との間の値である熱硬化性樹脂フィルム（１０ｐｐｍ／℃）を層間樹脂絶縁層５０上に積層することにより、チップサイズパッケージ１０を形成した際に、ＩＣチップ２０と外部基板２１０との間に位置する構造になる。これにより、熱サイクルを繰り返し受けた場合でも、線熱膨張係数の差に起因する層間絶縁層の伸縮を抑制できるため、層間絶縁層に生じる応力を緩和できる。
【０１２９】
第２実施例では、熱硬化性樹脂フィルムは、接着層を介することなく、直接に層間樹脂絶縁層５０上に積層できる。これにより、接着層を形成する必要がないため、接着層とＩＣチップ２０、層間樹脂絶縁層１５０との線熱膨張係数の差に起因する応力が発生しない。これにより、接続信頼性を確保することができる。また、接着層を形成させる必要がないため、製造工程を簡略化できる。
【０１３０】
（９）次いで、例えば、ＣＯ₂ガスレーザによって、パルスエネルギー２．０〜１０．０ｍＪ、パルス幅１〜１００μｓ、パルス間隔０．５ｍｓ以上、ショット数３〜５０の条件で、層間樹脂絶縁層１５０から導体回路５８に至る銅めっきポスト用開口１４８を形成する（図１７（Ｂ）参照）。この後、銅めっきポスト用開口１４８内に残留する樹脂をデスミア処理により除去する。ここでは、デスミア処理により樹脂残さを除去したが、過マンガン酸などの酸化剤を用いて樹脂残さを除去することも可能である。
【０１３１】
（１０）層間樹脂絶縁層１５０および銅めっきポスト用開口１４８の表面に、無電解めっきにより銅めっき膜１５２を形成する（図１７（Ｃ）参照）。予め層間樹脂絶縁層１５０および銅めっきポスト用開口１４８の表層にパラジウム触媒（アトテック製）などを付与させて、無電解めっき液に５〜６０分間浸漬させることにより、０．１〜５μｍの範囲でめっき膜である金属層１５２を設けた。
【０１３２】
（１１）次に、この銅めっき膜１５２上に、例えばスピンコートにより市販の感光性ドライフィルムを貼り付け、フォトマスクフィルムを載置して、１００ｍＪ／ｃｍ²で露光した後、０．８％炭酸ナトリウムで現像処理し、厚さ１５μｍのめっきレジスト１５４を設ける。次に、第１実施例と同様の条件で電解めっきを施して、電解銅めっき１５６を形成する（図１７（Ｄ）参照）。
【０１３３】
（１２）めっきレジスト１５４を５％ＮａＯＨで剥離除去した後、そのめっきレジスト下の金属層１５２を硝酸および硫酸と過酸化水素の混合液を用いるエッチングにて溶解除去し、金属層１５２と電解銅めっき１５６からなる銅めっきポスト１６０を形成し、第二銅錯体と有機酸とを含有するエッチング液によって、粗化面１６０αを形成する（図１８（Ａ）参照）。
【０１３４】
（１４）次に、層間樹脂絶縁層１５０上に、第１実施例と同様のソルダーレジスト組成物を２０μｍの厚さで塗布し、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、ソルダーレジストレジスト開口部のパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト層７０に密着させて１０００ｍＪ／ｃｍ²の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、２００μｍの直径の開口７１を形成する（図１８（Ｂ）参照）。なお、市販のソルダーレジストを用いてもよい。
【０１３５】
（１５）次に、ソルダーレジスト層（有機樹脂絶縁層）７０を形成したＩＣチップ２０を、無電解ニッケルめっき液に２０分間浸漬して、開口部７１に厚さ５μｍのニッケルめっき層７２を形成する。さらに、その基板を、無電解めっき液に浸漬して、ニッケルめっき層７２上に厚さ０．０３μｍの金めっき層７４を形成することで、銅めっきポスト１６０に半田パッド７５を形成する（図１８（Ｃ）参照）。
【０１３６】
（１６）この後、ソルダーレジスト層７０の開口部７１に、半田ペーストを印刷して、２００℃でリフローすることにより、半田バンプ７６を形成する。これにより、半田バンプ７６を有するチップサイズパッケージ１０を得ることができる（図１９参照）。
【０１３７】
第２実施例では、熱硬化性樹脂フィルムを層間樹脂絶縁層５０上に積層して、硬化させることにより層間樹脂絶縁層１５０を形成するため、接着層を介することなく、直接に半導体素子２０上に積層できる。これにより、接着層を形成させる必要がないため、接着層と半導体素子２０、層間樹脂絶縁層１５０との線熱膨張係数の差に起因する応力が発生しない。これにより、接続信頼性を確保することができる。更に、接着層を形成させる必要がないため、製造工程を簡略化できる。
【０１３８】
上述した実施例では、樹脂絶縁層２５０に絶縁性基板を、樹脂絶縁層１５０に硬化性樹脂フィルムを用いた。この絶縁性基板及び硬化性樹脂フィルムには、難溶性樹脂（例えば、無機フィラー）、可溶性粒子（例えば、エラストマー）、硬化剤、その他の成分が含有されている。それぞれについて以下に説明する。
【０１３９】
本発明の製造方法において使用する樹脂は、酸または酸化剤に可溶性の粒子（以下、可溶性粒子という）が酸または酸化剤に難溶性の樹脂（以下、難溶性樹脂という）中に分散したものである。
なお、本発明で使用する「難溶性」「可溶性」という語は、同一の酸または酸化剤からなる溶液に同一時間浸漬した場合に、相対的に溶解速度の早いものを便宜上「可溶性」と呼び、相対的に溶解速度の遅いものを便宜上「難溶性」と呼ぶ。
【０１４０】
上記可溶性粒子としては、例えば、酸または酸化剤に可溶性の樹脂粒子（以下、可溶性樹脂粒子）、酸または酸化剤に可溶性の無機粒子（以下、可溶性無機粒子）、酸または酸化剤に可溶性の金属粒子（以下、可溶性金属粒子）等が挙げられる。これらの可溶性粒子は、単独で用いても良いし、２種以上併用してもよい。
ここで、無機フィラーを配合することで、樹脂絶縁層の線膨張係数を小さくすることができる。
【０１４１】
上記可溶性粒子の形状は特に限定されず、球状、破砕状等が挙げられる。また、上記可溶性粒子の形状は、一様な形状であることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができるからである。
【０１４２】
上記可溶性粒子の平均粒径としては、０．１〜１０μｍが望ましい。この粒径の範囲であれば、２種類以上の異なる粒径のものを含有してもよい。すなわち、平均粒径が０．１〜０．５μｍの可溶性粒子と平均粒径が１〜３μｍの可溶性粒子とを含有する等である。これにより、より複雑な粗化面を形成することができ、導体回路との密着性にも優れる。なお、本発明において、可溶性粒子の粒径とは、可溶性粒子の一番長い部分の長さである。
【０１４３】
上記可溶性樹脂粒子としては、熱硬化性樹脂、熱可塑性樹脂等からなるものが挙げられ、酸あるいは酸化剤からなる溶液に浸漬した場合に、上記難溶性樹脂よりも溶解速度が速いものであれば特に限定されない。
上記可溶性樹脂粒子の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等からなるものが挙げられ、これらの樹脂の一種からなるものであってもよいし、２種以上の樹脂の混合物からなるものであってもよい。
【０１４４】
また、上記可溶性樹脂粒子としては、ゴムからなる樹脂粒子を用いることもできる。上記ゴムとしては、例えば、ポリブタジエンゴム、エポキシ変性、ウレタン変性、（メタ）アクリロニトリル変性等の各種変性ポリブタジエンゴム、カルボキシル基を含有した（メタ）アクリロニトリル・ブタジエンゴム等が挙げられる。これらのゴムを使用することにより、可溶性樹脂粒子が酸あるいは酸化剤に溶解しやすくなる。つまり、酸を用いて可溶性樹脂粒子を溶解する際には、強酸以外の酸でも溶解することができ、酸化剤を用いて可溶性樹脂粒子を溶解する際には、比較的酸化力の弱い過マンガン酸塩でも溶解することができる。また、クロム酸を用いた場合でも、低濃度で溶解することができる。そのため、酸や酸化剤が樹脂表面に残留することがなく、後述するように、粗化面形成後、塩化パラジウム等の触媒を付与する際に、触媒が付与されなたかったり、触媒が酸化されたりすることがない。さらに、ゴム等のエラストマーを配合することで、樹脂絶縁層が応力を吸収することができる。
【０１４５】
上記可溶性無機粒子としては、例えば、アルミニウム化合物、カルシウム化合物、カリウム化合物、マグネシウム化合物およびケイ素化合物からなる群より選択される少なくとも一種からなる粒子等が挙げられる。
【０１４６】
上記アルミニウム化合物としては、例えば、アルミナ、水酸化アルミニウム等が挙げられ、上記カルシウム化合物としては、例えば、炭酸カルシウム、水酸化カルシウム等が挙げられ、上記カリウム化合物としては、炭酸カリウム等が挙げられ、上記マグネシウム化合物としては、マグネシア、ドロマイト、塩基性炭酸マグネシウム等が挙げられ、上記ケイ素化合物としては、シリカ、ゼオライト等が挙げられる。これらは単独で用いても良いし、２種以上併用してもよい。
【０１４７】
上記可溶性金属粒子としては、例えば、銅、ニッケル、鉄、亜鉛、鉛、金、銀、アルミニウム、マグネシウム、カルシウムおよびケイ素からなる群より選択される少なくとも一種からなる粒子等が挙げられる。また、これらの可溶性金属粒子は、絶縁性を確保するために、表層が樹脂等により被覆されていてもよい。
【０１４８】
上記可溶性粒子を、２種以上混合して用いる場合、混合する２種の可溶性粒子の組み合わせとしては、樹脂粒子と無機粒子との組み合わせが望ましい。両者とも導電性が低くいため樹脂フィルムの絶縁性を確保することができるとともに、難溶性樹脂との間で熱膨張の調整が図りやすく、樹脂フィルムからなる樹脂絶縁層にクラックが発生せず、樹脂絶縁層と導体回路との間で剥離が発生しないからである。
【０１４９】
上記難溶性樹脂としては、樹脂絶縁層に酸または酸化剤を用いて粗化面を形成する際に、粗化面の形状を保持できるものであれば特に限定されず、例えば、熱硬化性樹脂、熱可塑性樹脂、これらの複合体等が挙げられる。また、これらの樹脂に感光性を付与した感光性樹脂であってもよい。感光性樹脂を用いることにより、樹脂絶縁層に露光、現像処理を用いてバイアホール用開口を形成することできる。
これらのなかでは、熱硬化性樹脂を含有しているものが望ましい。それにより、めっき液あるいは種々の加熱処理によっても粗化面の形状を保持することができるからである。
【０１５０】
上記難溶性樹脂の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、フェノキシ樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、ポリエーテルスルホン、フッ素樹脂等が挙げられる。これらの樹脂は単独で用いてもよいし、２種以上を併用してもよい。
さらには、１分子中に、２個以上のエポキシ基を有するエポキシ樹脂がより望ましい。前述の粗化面を形成することができるばかりでなく、耐熱性等にも優れてるため、ヒートサイクル条件下においても、金属層に応力の集中が発生せず、金属層の剥離などが起きにくいからである。
【０１５１】
上記エポキシ樹脂としては、例えば、クレゾールノボラック型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、アルキルフェノールノボラック型エポキシ樹脂、ビフェノールＦ型エポキシ樹脂、ナフタレン型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、フェノール類とフェノール性水酸基を有する芳香族アルデヒドとの縮合物のエポキシ化物、トリグリシジルイソシアヌレート、脂環式エポキシ樹脂等が挙げられる。これらは、単独で用いてもよく、２種以上を併用してもよい。それにより、耐熱性等に優れるものとなる。
【０１５２】
本発明で用いる樹脂フィルムにおいて、上記可溶性粒子は、上記難溶性樹脂中にほぼ均一に分散されていることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができ、樹脂フィルムにバイアホールやスルーホールを形成しても、その上に形成する導体回路の金属層の密着性を確保することができるからである。また、粗化面を形成する表層部だけに可溶性粒子を含有する樹脂フィルムを用いてもよい。それによって、樹脂フィルムの表層部以外は酸または酸化剤にさらされることがないため、樹脂絶縁層を介した導体回路間の絶縁性が確実に保たれる。
【０１５３】
上記樹脂フィルムにおいて、難溶性樹脂中に分散している可溶性粒子の配合量は、樹脂フィルムに対して、３〜４０重量％が望ましい。可溶性粒子の配合量が３重量％未満では、所望の凹凸を有する粗化面を形成することができない場合があり、４０重量％を超えると、酸または酸化剤を用いて可溶性粒子を溶解した際に、樹脂フィルムの深部まで溶解してしまい、樹脂フィルムからなる樹脂絶縁層を介した導体回路間の絶縁性を維持できず、短絡の原因となる場合がある。
【０１５４】
上記樹脂フィルムは、上記可溶性粒子、上記難溶性樹脂以外に、硬化剤、その他の成分等を含有していることが望ましい。
上記硬化剤としては、例えば、イミダゾール系硬化剤、アミン系硬化剤、グアニジン系硬化剤、これらの硬化剤のエポキシアダクトやこれらの硬化剤をマイクロカプセル化したもの、トリフェニルホスフィン、テトラフェニルホスフォニウム・テトラフェニルボレート等の有機ホスフィン系化合物等が挙げられる。
【０１５５】
上記硬化剤の含有量は、樹脂フィルムに対して０．０５〜１０重量％であることが望ましい。０．０５重量％未満では、樹脂フィルムの硬化が不十分であるため、酸や酸化剤が樹脂フィルムに侵入する度合いが大きくなり、樹脂フィルムの絶縁性が損なわれることがある。一方、１０重量％を超えると、過剰な硬化剤成分が樹脂の組成を変性させることがあり、信頼性の低下を招いたりしてしまうことがある。
【０１５６】
上記その他の成分としては、例えば、粗化面の形成に影響しない無機化合物あるいは樹脂等のフィラーが挙げられる。上記無機化合物としては、例えば、シリカ、アルミナ、ドロマイト等が挙げられ、上記樹脂としては、例えば、ポリイミド樹脂、ポリアクリル樹脂、ポリアミドイミド樹脂、ポリフェニレン樹脂、メラニン樹脂、オレフィン系樹脂等が挙げられる。これらのフィラーを含有させることによって、熱膨脹係数の整合や耐熱性、耐薬品性の向上などを図りチップサイズパッケージの性能を向上させることができる。
【０１５７】
また、上記樹脂フィルムは、溶剤を含有していてもよい。上記溶剤としては、例えば、アセトン、メチルエチルケトン、シクロヘキサノン等のケトン類、酢酸エチル、酢酸ブチル、セロソルブアセテートやトルエン、キシレン等の芳香族炭化水素等が挙げられる。これらは単独で用いてもよいし、２種類以上併用してもよい。ただし、これらの樹脂絶縁層は、３５０℃以上の温度を加えると溶解、炭化をしてしまう。
【０１５８】
[本実施例による試験例]
試験サンプルとしては、上記のようにして線熱膨張係数の１０〜７０ｐｐｍ／℃の絶縁性基板を用いて製造した９．７ｍｍ角の第１実施例に係るチップサイズパッケージ１０を５０ｍｍ角、厚さ８００μｍのプリント基板に実装したものを使用した。この試験サンプルについて、−５５℃と１２５℃の各温度に制御した恒温槽に３分／３分の保持を１サイクルとして５００サイクル繰り返した。
一方、比較例１として、線熱膨張係数の１０ｐｐｍ／℃未満の絶縁性基板を用いたものと、比較例２として、線熱膨張係数７０ｐｐｍ／℃超の絶縁性基板を用いたものとを作成した。
また、それぞれの試験サンプルについて、クラックの発生を目視により観察した結果を図２２中に示す。
【０１５９】
第１実施例のものでは、クラックの発生が見られず、クラックの発生が抑止されていることが分かった。一方、比較例１，比較例２では、クラックが発生した。これは、比較例１では、線熱膨張係数を小さくするために、無機フィラーの配合料が多くなり、靱性が低くなった結果、クラックが発生しているたのと考えられる。一方、比較例２では、線熱膨張係数が大きいため、樹脂絶縁層２５０自体の熱収縮によってクラックが発生していると考えられる。
【図面の簡単な説明】
【図１】（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１実施例に係る半導体素子の製造工程図である。
【図２】（Ａ）、（Ｂ）、（Ｃ）は、本発明の第１実施例に係る半導体素子の製造工程図である。
【図３】（Ａ）、（Ｂ）は、本発明の第１実施例に係る半導体素子の製造工程図である。
【図４】（Ａ）は、本発明の第１実施例に係るシリコンウエハー２０Ａの平面図であり、（Ｂ）は、個片化された半導体素子の平面図である。
【図５】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第２の製造方法に係る半導体素子の製造工程図である。
【図６】（Ａ）、（Ｂ）、（Ｃ）は、第２の製造方法に係る半導体素子の製造工程図である。
【図７】（Ａ）、（Ｂ）は、第２の製造方法に係る半導体素子の製造工程図である。
【図８】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第３の製造方法に係る半導体素子の製造工程図である。
【図９】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第４の製造方法に係る半導体素子の製造工程図である。
【図１０】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施例に係るチップサイズパッケージの製造工程図である。
【図１１】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第１実施例に係るチップサイズパッケージの製造工程図である。
【図１２】（Ａ）、（Ｂ）、（Ｃ）は、第１実施例に係るチップサイズパッケージの製造工程図である。
【図１３】（Ａ）、（Ｂ）、（Ｃ）は、第１実施例に係るチップサイズパッケージの製造工程図である。
【図１４】（Ａ）、（Ｂ）は、第１実施例に係るチップサイズパッケージの製造工程図である。
【図１５】第１実施例に係るチップサイズパッケージの断面図である。
【図１６】第１実施例に係るチップサイズパッケージの断面図である。
【図１７】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施例に係るチップサイズパッケージの製造工程図である。
【図１８】（Ａ）、（Ｂ）、（Ｃ）は、第２実施例に係るチップサイズパッケージの製造工程図である。
【図１９】第２実施例に係るチップサイズパッケージの断面図である。
【図２０】第２実施例に係るチップサイズパッケージの断面図である。
【図２１】従来のチップサイズパッケージの断面図である。
【図２２】第１実施例の半導体チップと比較例の半導体チップとを試験した結果を示す図表である。
【符号の説明】
２０ ＩＣチップ（半導体素子）
２０Ａ ウエハ
２２ ダイパッド
２４ 保護膜
３３ 薄膜層
３６ 薄膜層
３７ 厚付け層
３８ トランジション層
５０ 層間樹脂絶縁層
５８ 導体回路
６０ バイアホール
７０ ソルダーレジスト層
７６ 半田バンプ
８０ 接着層
１５０ 樹脂絶縁層
１６０ 銅めっきポスト
２５０ 樹脂絶縁層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor chip. In It is related.
[0002]
[Prior art]
In the technical field of semiconductor chips, development of miniaturized chips is underway in order to further increase the density. One such technique is chip size package (CSP). In this CSP, a structure in which a semiconductor chip and a printed board are connected via a solder ball formed on one surface side of the semiconductor chip is employed.
[0003]
By the way, the linear thermal expansion coefficient of a silicon wafer used for a semiconductor chip is about 3 ppm / ° C., whereas the linear thermal expansion coefficient of a glass epoxy substrate usually used for a printed circuit board is about 15 ppm / ° C. Bigger than the chip. For this reason, when the semiconductor chip is actuated and repeatedly subjected to a thermal cycle after mounting, a stress caused by a difference in linear thermal expansion coefficient between the semiconductor chip and the printed circuit board is generated. Due to this thermal stress, peeling may occur between the connection pads of the semiconductor chip and the printed circuit board and the solder balls.
[0004]
In order to relieve the stress applied to the joint portion between the semiconductor chip and the printed board described above, a structure having a flexible resin insulating layer on the wafer has been proposed. In the semiconductor chip having this structure, as shown in FIG. 21, an insulating layer 350 is formed on the electrode pad 122 of the wafer 120A, and a via hole 260 and a conductor circuit 258 are formed in the insulating layer 350. Further, a resin insulating layer 450 made of, for example, an epoxy resin is formed on the insulating layer 350, and a copper plating post 360 connected to the conductor circuit 258 is formed on the resin insulating layer 450, and the copper plating post 360 is formed. A solder ball 176 is formed thereon. Then, it is connected to the pad 312 of the printed wiring board 310 via the solder ball 176. In such a structure, an attempt is made to relieve stress caused by a difference in linear thermal expansion coefficient between the IC chip 120 made of silicon and the printed circuit board 310 made of resin by the insulating layer 450 and the copper plating post 360. .
[0005]
[Problems to be solved by the invention]
The linear thermal expansion coefficient of the epoxy resin used as the interlayer insulating layer 450 is much larger than the linear thermal expansion coefficients of the wafer 120A and the printed circuit board 310. For this reason, when the IC chip 120 operates and repeatedly receives a thermal cycle, a large stress is generated due to the difference in coefficient of linear thermal expansion between the resin insulating layer 450, the wafer 120A, and the printed circuit board 310, and the resin insulating layer 450 In some cases, cracks occurred.
[0006]
Furthermore, since the copper plating post 360 is formed by plating and filling copper, which is a metal, it does not absorb stress applied from the outside. Therefore, when a vertical force in FIG. 21 is applied to the copper plating post 360 due to the difference in linear thermal expansion coefficient between the wafer 120A and the printed circuit board 310, the stress from the side wall of the copper plating post 360 is horizontal. In some cases, the resin insulating layer 450 is cracked, and the copper plating post 360 and the conductor circuit 258 may be separated.
[0007]
The present invention has been made in view of the above-described circumstances, and a purpose thereof is a semiconductor chip capable of preventing cracks and ensuring connection reliability. The It is to provide.
[0008]
[Means for Solving the Problem and Actions and Effects of the Invention]
In order to solve the above problems, a semiconductor chip according to the invention of claim 1 is formed on a semiconductor element. Pa The (22) Semiconductor chip having (20) Because
An insulating substrate having a linear thermal expansion coefficient of 10 to 70 ppm / ° C. obtained by curing a resin containing an inorganic filler having a particle size in the range of 0.1 to 5.0 μm, located on the semiconductor element. (250) When,
Said insulating substrate (250) Column-shaped conductive post formed in (160) When,
Conductive post (160) Formed on the insulating substrate (250) External board located on (210) Solder bump connected to (76) When,
Conductive post (160) And said Pa The (22) Placed between Formed on the interlayer insulating layer (50) , Conductor layer connecting the two (60, 58) When,
Said insulating substrate (250) In Said Interlayer insulation layer (50) Adhesive layer connecting the semiconductor element via (150) When,
It is a technical feature to have.
[0009]
According to the invention of claim 1, the insulating layer provided on the semiconductor element is an insulating substrate obtained by curing a resin-impregnated base material. In other words, in order to dispose the conductive post on the insulating layer formed of a strong insulating substrate, when a force in the height direction is applied to the conductive post due to the difference in linear thermal expansion coefficient between the semiconductor element and the external substrate, Even if the stress from the side wall of the conductive post acts in the horizontal direction, the insulating layer is not cracked and no disconnection occurs inside.
Furthermore, since the insulating layer has a small coefficient of linear thermal expansion of 10 to 70 ppm / ° C., large stress due to a difference in thermal expansion coefficient with the external substrate does not occur even when the thermal cycle is repeatedly received. Moreover, by making the linear thermal expansion coefficient of the insulating layer less than that of the external substrate, the linear thermal expansion coefficient of the insulating layer can be intermediate between the external substrate and the semiconductor element, and between the external substrate and the semiconductor element. The stress generated by the difference in linear thermal expansion can be relaxed. Thereby, the crack of an insulating layer can be prevented and connection reliability can be ensured.
[0010]
Claim 1 Then, since the insulating substrate contains an inorganic filler, the linear thermal expansion coefficient can be adjusted to 10 to 70 ppm / ° C.
Although it does not specifically limit as said inorganic filler, For example, an aluminum compound, a calcium compound, a potassium compound, a magnesium compound, a silicon compound etc. are mentioned. These compounds may be used alone or in combination of two or more.
[0011]
Examples of the aluminum compound include alumina and aluminum hydroxide, and examples of the calcium compound include calcium carbonate and calcium hydroxide.
[0012]
Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite and basic magnesium carbonate. Examples of the silicon compound include silica and zeolite. It is done.
[0013]
The shape of the inorganic filler is not particularly limited, and examples thereof include a spherical shape, an elliptical spherical shape, and a polyhedral shape. Of these, spherical and elliptical spheres are desirable because cracks are likely to occur when the tip is sharp.
[0014]
The inorganic filler preferably has a length (or diameter) of 0.1 to 5.0 μm in the longest part. If it is less than 0.1 μm, it is difficult to relieve internal stress generated when the resin insulating layer is thermally expanded, and the coefficient of thermal expansion cannot be adjusted, and if it exceeds 5.0 μm, the resin insulating layer itself becomes hard and brittle. Moreover, when performing photocuring and thermosetting, an inorganic filler inhibits reaction between resin, As a result, it will become easy to generate | occur | produce a crack. From such points, the inorganic filler is more preferably transparent.
[0015]
As the inorganic filler, SiO ₂ Is preferably in the range of 3 to 50% by weight. If it is less than 3% by weight, the thermal expansion coefficient of the resin insulating layer does not decrease, whereas if it exceeds 50% by weight, the resolution is lowered and the opening is abnormal. More preferably, it is 5 to 40% by weight.
The content of the inorganic filler in the resin insulating layer is preferably 5 to 40% by weight. By using the inorganic filler in the above content ratio, the linear expansion coefficient of the resin insulating layer can be effectively reduced, and the stress generated by thermal expansion can be effectively relieved.
[0016]
It is desirable to blend a resin made of an elastomer into the resin insulating layer. Since the elastomer itself is rich in flexibility and impact resilience, even if the resin insulating layer receives stress, the stress is absorbed or the stress is relieved, so that cracks can be prevented. The elastomer component is preferably microphase-separated so as to have a sea-island structure after the resin insulating layer is cured. By adopting the sea-island structure, cracks and peeling due to the stress can be prevented.
[0017]
Examples of the elastomer used in the present invention include natural rubber, synthetic rubber, thermoplastic resin, thermosetting resin, and the like. In particular, an elastomer made of a thermosetting resin can sufficiently relieve stress.
Examples of the elastomer made of the thermosetting resin include polyester elastomers, styrene elastomers, vinyl chloride elastomers, fluorine elastomers, amide elastomers, and olefin elastomers.
[0018]
The shape of the elastomer component is not particularly limited, but a spherical shape, an elliptical spherical shape, and the like are desirable because of excellent effects of absorbing and relaxing stress.
Although the magnitude | size of the said elastomer component is not specifically limited, The length (or diameter) of the longest part has a desirable range of 0.5-1.5 micrometers. This is because if the size of the elastomer component is less than 0.5 μm, it is difficult to relax or absorb stress and cracks are likely to occur, and if it exceeds 1.5 μm, the resolution decreases.
[0019]
In the printed wiring board of the present invention, it is desirable that the elastomer component is microphase-separated so as to have a sea-island structure after the resin insulating layer is cured. This is because it is most suitable to disperse the elastomer component in this manner in order to obtain an effect of absorbing or relaxing stress by the elastomer component. The sea-island structure refers to a state where the elastomer component is dispersed in the form of “islands” in the “sea” made of an interlayer insulating resin composition other than the elastomer component.
[0020]
The content of the elastomer component in the resin insulation layer is preferably 1 to 20% by weight. This is because if the content is less than 1% by weight, it is difficult to relieve or absorb stress and cracks are likely to occur, and if it exceeds 20% by weight, the resolution decreases.
[0021]
The resin insulating layer constituting the printed wiring board of the present invention contains, in addition to the inorganic filler and elastomer, for example, a thermosetting resin, a thermoplastic resin, a composite of a thermosetting resin and a thermoplastic resin, and the like. May be. Examples of such a resin layer include (meth) acrylates of novolak type epoxy resins, bifunctional (meth) acrylic acid ester monomers, polymers of (meth) acrylic acid esters having a molecular weight of about 500 to 5000, and bisphenol type epoxy. Examples include those obtained by polymerizing and curing a composition made of a thermosetting resin made of a resin or the like, or a photosensitive monomer such as a polyvalent acrylic monomer.
[0022]
The bifunctional (meth) acrylic acid ester monomer is not particularly limited, and examples thereof include acrylic acid or methacrylic acid esters of various diols, and commercially available products include R-604 manufactured by Nippon Kayaku Co., Ltd. , PM2, PM21 and the like.
[0023]
Examples of the (meth) acrylate of the novolak type epoxy resin include an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid or methacrylic acid.
[0024]
The interlayer insulating resin composition of the present invention is preferably formed by blending an inorganic filler and an elastomer in a paste containing a resin for a resin insulating layer. By blending the inorganic filler, the reduced toughness is increased by blending the elastomer, and cracks are not generated in the resin insulating layer even when stress is applied.
[0025]
As the inorganic filler, those described above can be used. The blending amount is preferably such that the content ratio in the formed resin insulation layer is 5 to 20% by weight.
[0026]
As the elastomer component, those described above can be used. Moreover, the compounding quantity has the preferable content rate in an interlayer insulation resin composition that it will become 5 to 10 weight%.
[0027]
In addition to the inorganic filler and elastomer, the interlayer insulating resin composition of the present invention is a (meth) acrylate, imidazole curing agent, bifunctional (meth) acrylic acid ester monomer having a molecular weight of 500 to 5000, as described above. A paste-like fluid containing a polymer of (meth) acrylic acid ester, a thermosetting resin composed of a bisphenol type epoxy resin, a photosensitive monomer such as a polyvalent acrylic monomer, a glycol ether solvent, etc. The viscosity is desirably adjusted to 1 to 10 Pa · s at 25 ° C.
[0028]
Although it does not specifically limit as said imidazole hardening | curing agent, It is desirable to use the imidazole hardening | curing agent which is liquid at 25 degreeC. This is because uniform kneading is difficult with powder, and liquid can be uniformly kneaded.
Examples of such a liquid imidazole curing agent include 1-benzyl-2-methylimidazole (manufactured by Shikoku Kasei Co., Ltd., 1B2MZ), 1-cyanoethyl-2-ethyl-4-methylimidazole (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN). ), 4-methyl-2-ethylimidazole (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ) and the like.
[0029]
The glycol ether solvent preferably has, for example, a chemical structure represented by the following general formula (1), and specifically, at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG). It is more desirable to use seeds. This is because these solvents can completely dissolve benzophenone, Michler's ketone, and ethylaminobenzophenone, which are polymerization initiators, by heating at about 30 to 50 ° C.
CH _Three O- (CH ₂ CH ₂ O) n-CH _Three (1)
(In the above formula, n is an integer of 1 to 5.)
[0030]
The linear expansion coefficient of the resin or resin composite constituting this resin insulation layer is 60 × 10 ^-6 ~ 80 × 10 ^-6 K ^-1 However, by including the inorganic filler in this layer, the linear expansion coefficient is 40 to 50 × 10 ^-6 K ^-1 Can be reduced to a degree.
[0031]
The invention of claim 5 is technically characterized in that a transition layer for connection to a via hole of an interlayer insulating layer is formed on a die pad of a semiconductor element, and the transition layer is at least two layers.
[0032]
The transition layer defined in the present invention will be described.
The transition layer means an intermediate intermediary layer provided to directly connect the IC chip as a semiconductor element and the conductor layer. A feature is that it is formed of two or more metal layers and is larger than a die pad of an IC chip which is a semiconductor element. Thereby, the electrical connection and alignment are improved. Further, it is possible to directly form a metal which is a conductor layer on the transition layer.
[0033]
The reason for providing the transition layer on the die pad of the IC chip is as follows. The die pad of the IC chip is made with a diameter of about 20 to 60 μm, and since the via hole is larger than that, unconnection is likely to occur at the time of displacement. For this reason, via holes can be reliably connected by interposing a transition layer having a diameter larger than 20 μm on the die pad of the IC chip. Desirably, the transition layer should be equal to or larger than the via hole diameter.
[0034]
In order to function as a package substrate as a semiconductor device, a BGA, a solder bump, or a PGA (conductive connection pin) may be provided for connection to a mother board or daughter board as an external board. In addition, with this configuration, the wiring length can be shortened and the loop inductance can be reduced as compared with the case of connection by the conventional mounting method.
[0035]
Vapor deposition, sputtering, electroless plating, and the like are performed on the entire surface of the core substrate in which the IC chip is incorporated, and a conductive metal film (first thin film layer) is formed on the entire surface. As the metal, tin, chromium, titanium, nickel, zinc, cobalt, gold, copper and the like are preferable. As thickness, it is good to form between 0.001-2.0 micrometers. If it is less than 0.001 μm, it cannot be uniformly laminated on the entire surface. It was difficult to form a film having a thickness exceeding 2.0 μm, and the effect was not enhanced. In the case of chromium, a thickness of 0.1 μm is desirable.
[0036]
The first thin film layer can cover the die pad, and can improve the adhesion of the interface between the transition layer and the IC chip with the die pad. Further, by covering the die pad with these metals, moisture can be prevented from entering the interface, the die pad can be prevented from being dissolved and corroded, and reliability can be improved. Further, the first thin film layer can be connected to the IC chip by a mounting method without a lead. Here, it is desirable to use copper, chromium, nickel, or titanium in order to provide good adhesion to the metal and to prevent moisture from entering the interface. When the die pad is made of copper, copper is optimal for the first thin film layer.
[0037]
A second thin film layer can also be provided on the first thin film layer. Examples of the metal include nickel, copper, gold, and silver. In particular, when the die pad is made of copper, the second thin film layer is formed on the first thin film layer by sputtering, vapor deposition, or electroless plating. Since the die pad is made of copper and the thick layer formed later is mainly copper, it is preferable to use copper for the second thin film layer.
[0038]
The reason for providing the second thin film layer is that the first thin film layer is difficult to obtain a lead for electrolytic plating for forming a thickening layer to be described later. The second thin film layer 36 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5.0 μm. If the thickness is less than 0.01 μm, it cannot serve as a lead. If the thickness exceeds 5.0 μm, the first thin film layer as a lower layer is scraped off more during etching, and moisture easily enters. This is because the reliability is lowered. Since the thickening layer to be formed later is mainly copper, it is preferable to use copper. In particular, when the die pad is made of copper, copper is optimal.
[0039]
The second thin film layer is thickened by electroless or electrolytic plating. Examples of the metal to be formed include nickel, copper, gold, silver, zinc, and iron. Electrical characteristics, economy, strength as a transition layer, structural resistance, and the build-up conductor layer, which will be formed later, is mainly copper, so it is desirable to use copper for electrolytic plating . The thickness is preferably in the range of 1 to 20 μm. If it is thinner than 1 μm, the connection reliability with the upper via hole is lowered, and if it is thicker than 20 μm, an undercut occurs during etching, and a gap is generated at the interface between the formed transition layer and via hole. Because. In some cases, the first thin film layer may be directly thick-plated or further laminated in multiple layers.
[0040]
Thereafter, an etching resist is formed, and exposure and development are performed to expose portions of the metal other than the transition layer, and etching is performed to form a transition layer on the die pad of the IC chip.
[0041]
In addition to the above method of manufacturing the transition layer, a dry film resist is formed on the metal film formed on the IC chip and the core substrate, and the portion corresponding to the transition layer is removed and thickened by electrolytic plating. Thereafter, the resist is peeled off, and a transition layer can be similarly formed on the die pad of the IC chip with an etching solution.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor chip (chip size package) according to the present invention will be described below with reference to the drawings.
[First embodiment]
A. Chip size package (CSP) structure
A configuration of a chip size package formed by laminating a conductor circuit and an interlayer resin insulating layer on a semiconductor element (IC chip) will be described with reference to FIGS.
[0047]
As shown in FIG. 15, the chip size package 10 includes an IC chip 20, which will be described later with reference to FIG. 3B, an interlayer resin insulation layer 50, an adhesive layer 80, and a resin insulation layer 250. A via hole 60 and a conductor circuit 58 are formed in the interlayer resin insulation layer 50, and a copper plating post 160 is formed in the resin insulation layer 250.
[0048]
A solder resist layer 70 is disposed on the resin insulating layer 250. As shown in FIG. 16, solder bumps 76 for connecting to the external substrate 210 are provided on the copper plating posts 160 below the openings 71 of the solder resist layer 70.
[0049]
In the chip size package 10 of the present embodiment, an interlayer resin insulation layer 50 is provided on the IC chip 20, and a resin insulation layer 250 is provided on the interlayer resin insulation layer 50 via an adhesive layer 80. The resin insulating layer 250 is made of a 55 μm thick insulating substrate formed in a plate shape, and its linear thermal expansion coefficient is 10 ppm / ° C. As shown in FIG. 16, the insulating layer 350 of the external substrate 210 connected to the chip size package 10 is made of a glass cloth base epoxy resin (FR-4) having a thickness of 800 μm and formed in a plate shape. The thermal expansion coefficient is 15 ppm / ° C. Further, the linear thermal expansion coefficient of the IC chip 20 is 3 ppm / ° C.
[0050]
An insulating substrate having a linear thermal expansion coefficient of 10 ppm / ° C. is used for the resin insulating layer 250 of the chip size package 10. By making the linear thermal expansion coefficient of the resin insulating layer substantially the same as that of the external substrate, even when the thermal cycle is repeatedly received, stress due to the difference in thermal expansion coefficient with the external substrate 210 does not occur, and the resin insulating layer 250 Expansion and contraction is suppressed, and the generated stress is small. Thereby, the crack of the resin insulating layer 250 can be prevented, peeling does not occur between the copper plating post 160 and the conductor circuit 58, and connection reliability can be ensured.
[0051]
The resin insulating layer 250 may be an insulating substrate having a linear thermal expansion coefficient of 10 to 70 ppm / ° C. Since the linear thermal expansion coefficient is small, large stress due to the difference in thermal expansion coefficient with the external substrate 210 does not occur even when the thermal cycle is repeatedly received. Further, by setting the linear thermal expansion coefficient of the resin insulating layer 250 to be less than that of the external substrate, the linear thermal expansion coefficient of the resin insulating layer 250 can be made intermediate between the external substrate 210 and the IC chip 20, and the external substrate The stress generated by the difference in linear thermal expansion between 210 and the IC chip 20 can be relaxed. Thereby, the crack of the resin insulation layer 250 can be prevented and connection reliability can be ensured.
[0052]
In the semiconductor chip of the first embodiment, the resin insulating layer 250 is an insulating substrate obtained by curing a resin. That is, since the resin insulating layer 250 made of an insulating substrate having high strength is disposed, a force in the height direction is applied to the copper plating post 160 due to a difference in linear thermal expansion coefficient between the IC chip 20 and the external substrate 210, and the copper Even if the stress from the side wall of the plating post 250 acts in the horizontal direction, the resin insulating layer 250 is not cracked, and no disconnection occurs inside.
[0053]
Further, in the chip size package 10 of the present embodiment, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so the upper interlayer insulating layer 50 is also flattened, The film thickness is also uniform. In addition, the transition layer 38 can maintain the shape stability when the upper via hole 60 is formed.
[0054]
Furthermore, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22 from being immersed in an acid, an oxidant, or an etching solution in various subsequent processes, and various annealing. Even after the process, discoloration and dissolution of the pad 22 do not occur. This improves the connectivity and reliability between the IC chip pads and via holes. Furthermore, a via hole having a diameter of 60 μm can be reliably connected by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm.
[0055]
Next, regarding the configuration of the semiconductor element (IC chip) used in the above-described chip size package, further reference is made to FIG. 3A showing a cross section of the semiconductor element 20 and FIG. 4B showing a plan view. This will be described in detail. The wafer 20A used for the semiconductor element 20 is made of a silicon single crystal, and has a diameter of 4 inches and a thickness of about 300 μm, for example. On the wafer 20A, for example, square semiconductor elements 20 having a side of about 10 mm are manufactured in a state where they are aligned vertically and horizontally.
[0056]
As shown in FIG. 3B, a die pad 22 and wiring (not shown) are disposed on the upper surface of the semiconductor element 20, and a protective film 24 is coated on the die pad 22 and wiring. The die pad 22 has an opening for the protective film 24. On the die pad 22, a transition layer 38 mainly made of copper is formed. The transition layer 38 includes a thin film layer 33 and a thickening layer 37. In other words, it is formed of two or more metal layers.
[0057]
B. Manufacturing method of chip size package (CSP)
Next, a manufacturing method of the chip size package described above will be described with reference to FIGS.
The chip size package is formed by first manufacturing a semiconductor element used for the chip size package, and then laminating an interlayer insulating layer and a conductor circuit on the semiconductor element.
[0058]
First, a method for manufacturing a semiconductor element used for the chip size package described above with reference to FIG. 3B will be described with reference to FIGS.
[0059]
(1) First, the wiring 21 and the die pad 22 are formed by the usual method on the silicon wafer 20A shown in FIG. 1A (see FIG. 4A showing the plan views of FIG. 1B and FIG. 1B). Note that FIG. 1B shows a BB cross section of FIG.
(2) Next, a protective film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (see FIG. 1C).
[0060]
(3) Physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (see FIG. 2A). The thickness is preferably formed in the range of 0.001 to 2.0 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the first embodiment, the thin film layer 33 is made of chromium by sputtering. Chromium has good adhesion to metal and can suppress moisture intrusion. Moreover, you may sputter | spatter copper on a chromium layer. Two layers of chromium and copper may be continuously formed in a vacuum chamber. At this time, the thickness is about 0.05 to 0.1 μm of chromium and about 0.5 μm of copper.
[0061]
(4) Thereafter, a resist layer of any one of a liquid resist, a photosensitive resist, and a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposure and development are performed to form a non-formed portion 35a in the resist 35. Electrolytic plating is performed to provide a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (see FIG. 2B). The types of plating formed include nickel, copper, gold, silver, zinc, and iron. Electrical characteristics, economic efficiency, and the conductor layer, which is a build-up formed later, is mainly copper, so copper is preferably used. In the first embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm.
[0062]
(5) After removing the plating resist 35 with an alkaline solution or the like, the metal film 33 under the plating resist 35 is subjected to sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, etc. Then, the transition layer 38 is formed on the pad 22 of the IC chip (see FIG. 2C).
[0063]
(6) Next, an etching solution is sprayed onto the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (see FIG. 3A). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
[0064]
(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into pieces by dicing or the like to form the semiconductor element 20 (FIGS. 3B and 3B are plan views). (See FIG. 4B). Thereafter, if necessary, operation check and electrical inspection of the divided semiconductor element 20 may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pin can be easily applied, and the inspection accuracy is high.
[0065]
The thin film layer 33 can also be formed of titanium. Titanium is applied by vapor deposition or sputtering. Titanium has good adhesion to metal and can suppress the intrusion of moisture. Further, the thin film layer can be formed of tin, zinc, or cobalt. Further, the thin film layer can be formed of nickel. Nickel is formed by sputtering. Nickel has good adhesion to metal and can suppress the intrusion of moisture. Copper may be further laminated on the thin film layer.
[0066]
[Second manufacturing method]
Next, a semiconductor device according to the second manufacturing method will be described with reference to FIGS.
The semiconductor element 20 according to the second manufacturing method will be described with reference to FIG. In the semiconductor device according to the first embodiment described above with reference to FIG. 3B, the transition layer 38 has a two-layer structure including the thin film layer 33 and the thickening layer 37. On the other hand, in the second manufacturing method, as shown in FIG. 7B, the transition layer 38 includes three layers including a first thin film layer 33, a second thin film layer 36, and a thickening layer 37. It is structured as a structure.
[0067]
A method for manufacturing a semiconductor device according to the second manufacturing method described above with reference to FIG. 7B will be described with reference to FIGS.
[0068]
(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 5A (see FIG. 5B).
(2) Next, a protective film 24 is formed on the die pad 22 and the wiring (see FIG. 5C).
[0069]
(3) Physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film (first thin film layer) 33 on the entire surface (see FIG. 5D). The thickness is preferably in the range of 0.001 to 2 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the second manufacturing method, the first thin film layer 33 is formed of chromium. Chromium, nickel, and titanium have good adhesion to metal and can suppress moisture intrusion.
[0070]
(4) The second thin film layer 36 is laminated on the first thin film layer 33 by any one of sputtering, vapor deposition, and electroless plating (see FIG. 6A). In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it may be formed of either copper or nickel. This is because copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and hardly causes peeling or cracking. In the second manufacturing method, the second thin film layer 36 is formed by electroless copper plating. A desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel, or the like. It is superior to other combinations in terms of metal bondability and electrical conductivity.
[0071]
(5) Thereafter, a resist layer is formed on the second thin film layer 36. A mask (not shown) is placed on the resist layer, and after exposure and development, a non-formed portion 35a is formed in the resist 35. Electrolytic plating is performed to provide a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (see FIG. 6B). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical characteristics, economic efficiency, and the conductor layer, which is a build-up formed later, is mainly copper. Therefore, copper is preferably used. In the second manufacturing method, copper is used. The thickness is preferably in the range of 1 to 20 μm.
[0072]
(6) After removing the plating resist 35 with an alkaline solution or the like, the second thin film layer 36 and the first thin film layer 33 under the plating resist 35 are mixed with sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, second The transition layer 38 is formed on the pad 22 of the IC chip by removing with an etching solution such as a dicopper complex-organic acid salt (see FIG. 6C).
[0073]
(7) Next, an etching solution is sprayed on the substrate to etch the surface of the transition layer 38, thereby forming a roughened surface 38α (see FIG. 7A). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
[0074]
(8) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor element 20 (see FIG. 7B).
[0075]
In the second manufacturing method described above, the first thin film layer 33 is formed of chromium, the second thin film layer 36 is formed of electroless plated copper, and the thickening layer 37 is formed of electrolytic copper plating. On the other hand, the first thin film layer 33 can be formed of chromium, the second thin film layer 36 can be formed of sputtered copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper.
[0076]
Further, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of electroless copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.0 μm plated copper, and 17 μm electrolytic copper.
[0077]
Furthermore, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of sputtered copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.06 μm titanium, 0.5 μm copper, and 15 μm electrolytic copper.
[0078]
Alternatively, the first thin film layer 33 may be formed of chromium, the second thin film layer 36 may be formed of electroless plating nickel, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 1.0 μm plated copper, and 15 μm electrolytic copper.
[0079]
Alternatively, the first thin film layer 33 may be formed of titanium, the second thin film layer 36 may be formed of electroless plating nickel, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.05 μm titanium, 1.2 μm plated nickel, and 15 μm electrolytic copper.
[0080]
[Third production method]
The semiconductor element 20 according to the third manufacturing method will be described. The configuration of the semiconductor device of the third manufacturing method is substantially the same as that of the first embodiment described above with reference to FIG. However, in the first embodiment, the transition layer 38 is formed by forming the thickening layer 37 in the resist non-forming portion using a semi-additive process. On the other hand, in the third manufacturing method, after the thick layer 37 is uniformly formed using an additive process, a resist is provided, and the non-resist formation portion is removed by etching to form the transition layer 38.
[0081]
A semiconductor device manufacturing method according to the third manufacturing method will be described with reference to FIG.
(1) As described above with reference to FIG. 2A in the first embodiment, physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive thin film layer 33 on the entire surface ( (See FIG. 8A). The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is preferably 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals provide die pad protection and do not degrade electrical properties. In the third manufacturing method, the thin film layer 33 is formed by sputtering chromium. The thickness of chromium is 0.05 μm.
[0082]
(2) A thickening layer (electrolytic plating film) 37 is uniformly provided on the thin film layer 33 by electrolytic plating (see FIG. 8B). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the conductor layer, which is a build-up formed later, is mainly copper, it is preferable to use copper. In the third manufacturing method, copper is used. The thickness is preferably in the range of 1 to 20 μm. If it is thicker than that, undercut occurs during the etching described later, and a gap may be generated at the interface between the formed transition layer and via hole.
[0083]
(3) Thereafter, a resist layer 35 is formed on the thickening layer 37 (see FIG. 8C).
[0084]
(4) The thin film layer 33 and the thickening layer 37 in the non-formation part of the resist 35 are removed with an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt. After that, the resist 35 is removed to form a transition layer 38 on the pad 22 of the IC chip (see FIG. 8D). Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted. Note that the thin film layer 33 can also be formed of titanium.
[0085]
[Fourth manufacturing method]
The semiconductor element 20 according to the fourth manufacturing method will be described. In the semiconductor device according to the third manufacturing method described above with reference to FIG. 8, the transition layer 38 has a two-layer structure including the thin film layer 33 and the thickening layer 37. On the other hand, in the fourth manufacturing method, as shown in FIG. 9D, the transition layer 38 includes three layers including a first thin film layer 33, a second thin film layer 36, and a thickening layer 37. It is structured as a structure.
[0086]
A semiconductor device manufacturing method according to the fourth manufacturing method will be described with reference to FIG.
(1) Similar to the second manufacturing method described above with reference to FIG. 6A, the second thin film layer 36 is laminated on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating (FIG. 9 (A)). In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it may be formed of either copper or nickel. This is because copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and hardly causes peeling or cracking. In the fourth manufacturing method, the second thin film layer 36 is formed by electroless copper plating.
Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of metal bondability and electrical conductivity.
[0087]
(2) Electroplating is performed to uniformly provide a thick film 37 on the second thin film layer 36 (see FIG. 9B).
[0088]
(3) Thereafter, a resist layer 35 is formed on the thickening layer 37 (see FIG. 9C).
[0089]
(4) The first thin film layer 33, the second thin film layer 36, and the thickening layer 37 in the portion where the resist 35 is not formed are made of sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic. After removal with an etching solution such as an acid salt, the resist 35 is peeled off to form a transition layer 38 on the pad 22 of the IC chip (see FIG. 9D). Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.
[0090]
The first thin film layer 33 may be formed of chromium, the second thin film layer 36 may be formed of sputtered copper, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper. Alternatively, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of electroless copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.0 μm copper, and 15 μm electrolytic copper.
[0091]
Further, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of sputtered copper, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is titanium 0.07 μm, copper 0.5 μm, and electrolytic copper 18 μm.
[0092]
Alternatively, the first thin film layer 33 may be formed of chromium, the second thin film layer 36 may be formed of electroless plating nickel, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.06 μm chromium, 1.2 μm nickel, and 16 μm electrolytic copper.
[0093]
Furthermore, the first thin film layer 33 can be formed of titanium, the second thin film layer 36 can be formed of electroless plating nickel, and the thickening layer 37 can be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.1 μm nickel, and 15 μm electrolytic copper.
[0094]
[Fifth Manufacturing Method]
In the fifth manufacturing method, a zincate process is performed on the surface of the die pad 22. The IC chip 20 is immersed in a nickel non-electric plating bath or a plating bath to deposit a nickel plating film on the die pad 22. Subsequently, the IC chip 20 is immersed in a nickel-copper composite plating solution to form a nickel-copper composite plating layer having a thickness of 0.01 to 5 μm on the nickel plating layer.
[0095]
Next, a manufacturing method of a chip size package formed by laminating a conductor circuit and an interlayer resin insulating layer on a semiconductor element (IC chip) formed by the manufacturing method described above will be described with reference to FIGS. explain.
[0096]
(1) First, the IC chip 20 provided with the transition layer 38 is used as a starting material by the manufacturing steps of the first embodiment and the third manufacturing method described above (see FIG. 10A). Next, an interlayer resin insulating layer 50 is provided on the IC chip 20 by applying a photosensitive curable resin (see FIG. 10B). As the curable resin, for example, a photosensitive polyimide resin can be used.
[0097]
(2) Next, the photomask film 49 on which the black circle 49a corresponding to the via hole forming position is drawn is placed on the interlayer resin insulating layer 50 and exposed (see FIG. 10C).
[0098]
(3) A via hole opening 48 having a diameter of 85 μm is provided in the interlayer resin insulating layer 50 by spray development with DMTG solution and heat treatment (see FIG. 10D). The resin residue in the opening 48 is removed using permanganic acid having a liquid temperature of 60 ° C.
[0099]
By providing the copper transition layer 38 on the die pad 22, it is possible to prevent resin residue on the pad 22, thereby improving the connectivity and reliability between the pad 22 and a via hole 60 described later. Further, by providing the transition layer 38 having a diameter of 60 μm or more on the 40 μm diameter pad 22, the via hole opening 48 having a diameter of 60 μm can be reliably connected. Here, the resin residue is removed using an oxidizing agent such as permanganic acid, but it is also possible to perform desmear treatment using oxygen plasma or the like or corona treatment.
[0100]
(4) Next, the surface of the interlayer resin insulating layer 50 is roughened with permanganic acid or chromic acid to form a roughened surface 50α (see FIG. 11A). The roughened surface is desirably between 0.05 and 5 μm.
[0101]
(5) A metal layer 52 is provided on the interlayer resin insulation layer 50 on which the roughened surface 50α is formed. The metal layer 52 was formed by electroless plating. A metal layer 52 as a plating film was provided in the range of 0.1 to 5 μm by previously applying a catalyst such as palladium on the surface layer of the interlayer resin insulation layer 50 and immersing it in an electroless plating solution for 5 to 60 minutes. (See FIG. 11B). As an example,
[Electroless plating aqueous solution]
NiSO _Four 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
It was immersed for 40 minutes at a liquid temperature of 34 ° C.
[0102]
Instead of plating, using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd., sputtering using Ni—Cu alloy as a target was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes. The Cu alloy 52 can also be formed on the surface of the interlayer resin insulation layer 50. At this time, the formed Ni—Cu alloy layer 52 has a thickness of 0.2 μm.
[0103]
(6) A commercially available photosensitive dry film is pasted on the IC chip 20 that has been subjected to the above treatment, and a photomask film is placed on the IC chip 20 to obtain 100 mJ / cm. ² After the exposure, the development process is performed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 11C). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0104]

[0105]
(7) After stripping and removing the plating resist 54 with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating are removed. A conductor circuit 58 and a via hole 60 having a thickness of 16 μm formed of the film 56 are formed, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (see FIG. 11D). ).
[0106]
(8) Next, an adhesive resin 80 is formed by attaching an epoxy resin film (linear thermal expansion coefficient 40 ppm / ° C.) having a thickness of 35 μm on the interlayer resin insulation layer 50 provided with the via hole 60 ( (See FIG. 12A). The adhesive layer 80 of this embodiment has a larger linear thermal expansion coefficient than the IC chip 20 and a resin insulating layer 250 described later. However, the thickness is much smaller than that of the IC chip 20 and the resin insulating layer 250, and the IC chip 20 and the resin insulating layer 250 are sandwiched. For this reason, even when the adhesive layer 80 is cured and when it is repeatedly subjected to thermal cycles after mounting, the influence of expansion and contraction of the adhesive layer 80 can be minimized.
[0107]
(9) On the adhesive layer 80, a later-described insulating substrate having a thickness of 55 μm is placed. Subsequently, while raising the temperature to 50 to 150 ° C., the pressure is 5 kg / cm. ² Then, the resin insulating layer 250 is formed by vacuum compression lamination (see FIG. 12B). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0108]
Further, a resin insulation layer 250 (10 ppm / ° C.) having a linear thermal expansion coefficient between the IC chip 20 (3 ppm / ° C.) and the external substrate 210 (15 ppm / ° C.) is laminated on the interlayer resin insulation layer 50. Thus, when the chip size package 10 is formed, the structure is located between the IC chip 20 and the external substrate 210. Thereby, even when the thermal cycle is repeatedly received, since the expansion and contraction of the interlayer insulating layer due to the difference in the linear thermal expansion coefficient can be suppressed, the stress generated in the interlayer insulating layer can be relieved.
[0109]
(10) Then, for example, CO ₂ Copper plating post opening from resin insulation layer 250 to conductor circuit 58 under conditions of pulse energy of 2.0 to 10.0 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot number of 3 to 50 by gas laser 148 is formed (see FIG. 12C). In this embodiment, since a laser is used, an opening can be easily formed in an insulating substrate made of various materials.
[0110]
(11) Thereafter, the resin remaining in the copper plating post opening 148 is removed by a desmear process. Here, the resin residue is removed by desmear treatment, but it is also possible to remove the resin residue using an oxidizing agent such as permanganic acid.
[0111]
(12) A copper plating film 152 is formed on the surface of the resin insulating layer 250 and the opening 148 for the copper plating post by electroless plating (see FIG. 13A). Plating in the range of 0.1 to 5 μm by preliminarily applying a palladium catalyst (manufactured by Atotech) on the surface layer of the resin insulation layer 250 and the opening 148 for the copper plating post and immersing it in the electroless plating solution for 5 to 60 minutes A metal layer 152 as a film was provided. As an example,
[Electroless plating aqueous solution]
NiSO _Four 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
It was immersed for 40 minutes at a liquid temperature of 34 ° C.
[0112]
(13) Next, a commercially available photosensitive dry film is attached onto the copper plating film 152 by, for example, spin coating, and a photomask film is placed thereon to obtain 100 mJ / cm. ² After the exposure, a development process is performed with 0.8% sodium carbonate to provide a plating resist 154 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form electrolytic copper plating 156 (see FIG. 13B). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0113]

[0114]
(14) After removing the plating resist 154 with 5% NaOH, the metal layer 152 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 152 and electrolytic copper are removed. A copper plating post 160 made of plating 156 is formed, and a roughened surface 160α is formed by an etching solution containing a cupric complex and an organic acid (see FIG. 13C). Here, the linear thermal expansion coefficient of the formed copper plating post 160 is desirably 3 to 40 ppm / ° C.
[0115]
(15) Next, a photosensitizing agent obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd.) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured with a B type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0116]
(16) Next, the solder resist composition is applied on the resin insulating layer 250 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist is applied. A photomask having a thickness of 5 mm on which a pattern of the resist opening is drawn is brought into close contact with the solder resist layer 70 to 1000 mJ / cm. ² Then, an opening 71 having a diameter of 200 μm is formed (see FIG. 14A). A commercially available solder resist may also be used.
[0117]
(17) Next, the IC chip 20 on which the solder resist layer (organic resin insulating layer) 70 is formed is made of nickel chloride (2.3 × 10 6). ^-1 mol / l), sodium hypophosphate (2.8 × 10 6) ^-1 mol / l), sodium citrate (1.6 × 10 ^-1 The nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6 ^-3 mol / l), ammonium chloride (1.9 × 10 ^-1 mol / l), sodium citrate (1.2 × 10 ^-1 mol / l), sodium hypophosphite (1.7 × 10 ^-1 The copper plating post 160 is formed by immersing in an electroless plating solution containing (mol / l) for 7.5 minutes at 80 ° C. to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72. A solder pad 75 is formed on the substrate (see FIG. 14B).
[0118]
(18) Thereafter, a solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps 76. Thereby, the chip size package 10 having the solder bumps 76 can be obtained (see FIG. 15).
[0119]
For the solder paste, Sn / Pb, Sn / Sb, Sn / Ag, Sn / Ag / Cu, or the like can be used. Of course, a radiation low α-ray type solder paste may be used.
[0120]
In this example, the semiconductor element 20 (see FIG. 3B) divided into individual pieces by dicing or the like was used as a starting material. Here, the semiconductor element 20 (see FIG. 3A) that is not divided into individual pieces may be used as a starting material, and after the chip size package is formed, the chip size package may be divided into individual pieces by dicing or the like.
[0121]
Further, by providing a resin insulating layer 250 having a linear thermal expansion coefficient between the IC chip 20 and the external substrate 210 between the IC chip 20 and the external substrate 210, even when the thermal cycle is repeatedly received, Since the expansion and contraction of the interlayer insulating layer due to the difference in linear thermal expansion coefficient can be suppressed, the stress generated in the interlayer insulating layer can be relaxed.
[0122]
[Second Embodiment]
A chip size package according to a modification of the second embodiment of the present invention will be described with reference to FIG.
In the chip size package according to the first embodiment described above with reference to FIG. 15, an insulating substrate cured in advance on the resin insulating layer 250 was used. On the other hand, in the second embodiment, a thermosetting resin film described later is used for the resin insulating layer 150. For this reason, the resin insulating layer 150 is formed on the interlayer resin insulating layer 50 without interposing an adhesive layer.
[0123]
Also in the second embodiment, a thermosetting resin film having a linear thermal expansion coefficient of 10 to 70 ppm / ° C. when cured can be used.
[0124]
The resin insulating layer 150 is made of a material having a linear thermal expansion coefficient of 10 to 70 ppm / ° C. Since the linear thermal expansion coefficient is small, large stress due to the difference in thermal expansion coefficient with the external substrate 210 does not occur even when the thermal cycle is repeatedly received. Further, by setting the linear thermal expansion coefficient of the resin insulating layer 150 to be less than that of the external substrate, the linear thermal expansion coefficient of the resin insulating layer 150 can be made intermediate between the external substrate 210 and the IC chip 20, and the external substrate The stress generated by the difference in linear thermal expansion between 210 and the IC chip 20 can be relaxed. Thereby, the crack of the resin insulating layer 150 can be prevented, and connection reliability can be ensured.
[0125]
In the semiconductor chip of the second embodiment, the resin insulating layer 150 is a cured insulating substrate. That is, in order to dispose the resin insulating layer 150 made of an insulating substrate having high strength, a force in the height direction is applied to the copper plating post 160 due to a difference in linear thermal expansion coefficient between the IC chip 20 and the external substrate 210, and the copper Even if the stress from the side wall of the plating post 150 acts in the horizontal direction, the resin insulating layer 150 does not crack and does not break internally.
[0126]
The manufacturing process of the chip size package of the second embodiment will be described with reference to FIGS. Here, since the process before forming the resin insulating layer 150 is the same as that of the first embodiment described above with reference to FIGS. 11 and 12, illustration and description thereof are omitted.
[0127]
(8) On the interlayer resin insulation layer 50 provided with the via holes 60, a thermosetting resin film described later formed in a plate shape with a thickness of 70 μm is laminated. Thereafter, the pressure is increased to 50 to 150 ° C. and the pressure is 5 kg / cm. ² Then, the interlayer resin insulation layer 150 is formed by vacuum compression lamination and curing (see FIG. 17A). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0128]
Further, a thermosetting resin film (10 ppm / ° C.) whose linear thermal expansion coefficient after curing is a value between the IC chip 20 (3 ppm / ° C.) and the external substrate 210 (15 ppm / ° C.) is used as the interlayer resin insulation layer 50. By stacking on top of each other, the structure is located between the IC chip 20 and the external substrate 210 when the chip size package 10 is formed. Thereby, even when the thermal cycle is repeatedly received, since the expansion and contraction of the interlayer insulating layer due to the difference in the linear thermal expansion coefficient can be suppressed, the stress generated in the interlayer insulating layer can be relieved.
[0129]
In the second embodiment, the thermosetting resin film can be directly laminated on the interlayer resin insulating layer 50 without using an adhesive layer. Thereby, since it is not necessary to form an adhesive layer, stress due to the difference in linear thermal expansion coefficient between the adhesive layer, the IC chip 20 and the interlayer resin insulating layer 150 does not occur. Thereby, connection reliability can be ensured. Moreover, since it is not necessary to form an adhesive layer, the manufacturing process can be simplified.
[0130]
(9) Next, for example, CO ₂ For copper plating posts from the interlayer resin insulation layer 150 to the conductor circuit 58 under the conditions of pulse energy of 2.0 to 10.0 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot number of 3 to 50 by gas laser An opening 148 is formed (see FIG. 17B). Thereafter, the resin remaining in the copper plating post opening 148 is removed by a desmear process. Here, the resin residue is removed by desmear treatment, but it is also possible to remove the resin residue using an oxidizing agent such as permanganic acid.
[0131]
(10) A copper plating film 152 is formed on the surface of the interlayer resin insulation layer 150 and the copper plating post opening 148 by electroless plating (see FIG. 17C). In the range of 0.1 to 5 μm, a palladium catalyst (manufactured by Atotech) is applied to the surface layer of the interlayer resin insulation layer 150 and the opening 148 for the copper plating post in advance and immersed in the electroless plating solution for 5 to 60 minutes. A metal layer 152 which is a plating film was provided.
[0132]
(11) Next, a commercially available photosensitive dry film is attached onto the copper plating film 152 by, for example, spin coating, and a photomask film is placed thereon to obtain 100 mJ / cm. ² After the exposure, a development process is performed with 0.8% sodium carbonate to provide a plating resist 154 having a thickness of 15 μm. Next, electrolytic plating is performed under the same conditions as in the first embodiment to form electrolytic copper plating 156 (see FIG. 17D).
[0133]
(12) After removing the plating resist 154 with 5% NaOH, the metal layer 152 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 152 and the electrolytic copper are removed. A copper plating post 160 made of plating 156 is formed, and a roughened surface 160α is formed by an etching solution containing a cupric complex and an organic acid (see FIG. 18A).
[0134]
(14) Next, a solder resist composition similar to that of the first embodiment is applied to the interlayer resin insulation layer 150 in a thickness of 20 μm, and dried under conditions of 70 ° C. for 20 minutes and 70 ° C. for 30 minutes. After that, a photomask having a thickness of 5 mm on which the pattern of the opening portion of the solder resist resist was drawn was brought into close contact with the solder resist layer 70 and 1000 mJ / cm. ² Then, an opening 71 having a diameter of 200 μm is formed (see FIG. 18B). A commercially available solder resist may be used.
[0135]
(15) Next, the IC chip 20 on which the solder resist layer (organic resin insulating layer) 70 is formed is immersed in an electroless nickel plating solution for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. To do. Further, the substrate is immersed in an electroless plating solution to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72, thereby forming solder pads 75 on the copper plating posts 160 (FIG. 18 (C)).
[0136]
(16) After that, solder bumps 76 are formed by printing solder paste in the openings 71 of the solder resist layer 70 and reflowing at 200 ° C. Thereby, the chip size package 10 having the solder bumps 76 can be obtained (see FIG. 19).
[0137]
In the second embodiment, a thermosetting resin film is laminated on the interlayer resin insulation layer 50 and cured to form the interlayer resin insulation layer 150, so that it is directly on the semiconductor element 20 without an adhesive layer. Can be laminated. Thereby, since it is not necessary to form an adhesive layer, no stress is generated due to a difference in linear thermal expansion coefficient between the adhesive layer, the semiconductor element 20 and the interlayer resin insulating layer 150. Thereby, connection reliability can be ensured. Furthermore, since it is not necessary to form an adhesive layer, the manufacturing process can be simplified.
[0138]
In the embodiment described above, an insulating substrate is used for the resin insulating layer 250 and a curable resin film is used for the resin insulating layer 150. The insulating substrate and the curable resin film contain a hardly soluble resin (for example, an inorganic filler), soluble particles (for example, an elastomer), a curing agent, and other components. Each will be described below.
[0139]
The resin used in the production method of the present invention is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a hardly soluble resin). is there.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively high dissolution rate as “soluble” for convenience when immersed in a solution comprising the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0140]
Examples of the soluble particles include resin particles soluble in acid or oxidizing agent (hereinafter referred to as soluble resin particles), inorganic particles soluble in acid or oxidizing agent (hereinafter referred to as soluble inorganic particles), and metals soluble in acid or oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
Here, the linear expansion coefficient of a resin insulating layer can be made small by mix | blending an inorganic filler.
[0141]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0142]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0143]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0144]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified and other modified polybutadiene rubbers, carboxyl group-containing (meth) acrylonitrile / butadiene rubbers, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do. Furthermore, a resin insulation layer can absorb stress by mix | blending elastomers, such as rubber | gum.
[0145]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0146]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0147]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0148]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted with the hardly soluble resin, and the resin insulation layer made of the resin film does not crack, and the resin This is because no peeling occurs between the insulating layer and the conductor circuit.
[0149]
The hardly soluble resin is not particularly limited as long as the roughened surface can be maintained when the roughened surface is formed using an acid or an oxidizing agent in the resin insulating layer. For example, the thermosetting resin , Thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the resin insulating layer using exposure and development processes.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0150]
Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin, polyimide resin, polyphenylene resin, polyolefin resin, polyethersulfone, and fluorine resin. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0151]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0152]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. Thereby, since the portions other than the surface layer portion of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the resin insulating layer is reliably maintained.
[0153]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. Moreover, it melt | dissolves to the deep part of a resin film, cannot maintain the insulation between the conductor circuits through the resin insulating layer which consists of a resin film, and may cause a short circuit.
[0154]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0155]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0156]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, dolomite, and the like. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By including these fillers, it is possible to improve the performance of the chip size package by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0157]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more. However, these resin insulating layers are dissolved and carbonized when a temperature of 350 ° C. or higher is applied.
[0158]
[Test example according to this example]
As a test sample, the chip size package 10 according to the first example of 9.7 mm square manufactured using the insulating substrate having a linear thermal expansion coefficient of 10 to 70 ppm / ° C. as described above is 50 mm square and thickness. What was mounted on the printed circuit board of 800 micrometers was used. About this test sample, holding | maintenance for 3 minutes / 3 minutes was made into 1 cycle in the thermostat controlled to each temperature of -55 degreeC and 125 degreeC, and 500 cycles were repeated.
On the other hand, a comparative example 1 was prepared using an insulating substrate having a linear thermal expansion coefficient of less than 10 ppm / ° C, and a comparative example 2 was prepared using an insulating substrate having a linear thermal expansion coefficient exceeding 70 ppm / ° C. did.
Moreover, the result of having observed the generation | occurrence | production of a crack visually about each test sample is shown in FIG.
[0159]
In the first example, it was found that the occurrence of cracks was not observed and the occurrence of cracks was suppressed. On the other hand, in Comparative Examples 1 and 2, cracks occurred. This is probably because, in Comparative Example 1, cracks were generated as a result of an increase in the amount of inorganic filler compounding material and a decrease in toughness in order to reduce the linear thermal expansion coefficient. On the other hand, in Comparative Example 2, since the linear thermal expansion coefficient is large, it is considered that cracks are generated due to thermal contraction of the resin insulating layer 250 itself.
[Brief description of the drawings]
FIGS. 1A, 1B, and 1C are manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention. FIGS.
FIGS. 2A, 2B, and 2C are manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention. FIGS.
FIGS. 3A and 3B are manufacturing process diagrams of a semiconductor device according to the first embodiment of the present invention. FIGS.
FIG. 4A is a plan view of a silicon wafer 20A according to the first embodiment of the present invention, and FIG. 4B is a plan view of a separated semiconductor element.
5A, 5B, 5C, and 5D are manufacturing process diagrams of a semiconductor device according to a second manufacturing method.
6A, 6B, and 6C are manufacturing process diagrams of a semiconductor device according to a second manufacturing method.
7A and 7B are manufacturing process diagrams of a semiconductor device according to a second manufacturing method.
8A, 8B, 8C, and 8D are manufacturing process diagrams of a semiconductor device according to a third manufacturing method.
9A, 9B, 9C, and 9D are manufacturing process diagrams of a semiconductor device according to a fourth manufacturing method.
10A, 10B, 10C, and 10D are manufacturing process diagrams of a chip size package according to the first embodiment of the present invention.
FIGS. 11A, 11B, 11C, and 11D are manufacturing process diagrams of a chip size package according to the first embodiment. FIGS.
FIGS. 12A, 12B, and 12C are manufacturing process diagrams of a chip size package according to the first embodiment; FIGS.
13A, 13B, and 13C are manufacturing process diagrams of a chip size package according to the first embodiment.
14A and 14B are manufacturing process diagrams of a chip size package according to the first embodiment.
FIG. 15 is a cross-sectional view of the chip size package according to the first embodiment.
FIG. 16 is a cross-sectional view of the chip size package according to the first embodiment.
17A, 17B, 17C, and 17D are manufacturing process diagrams of a chip size package according to a second embodiment of the present invention.
18A, 18B, and 18C are manufacturing process diagrams of a chip size package according to a second embodiment.
FIG. 19 is a cross-sectional view of a chip size package according to a second embodiment.
FIG. 20 is a cross-sectional view of a chip size package according to a second embodiment.
FIG. 21 is a cross-sectional view of a conventional chip size package.
FIG. 22 is a chart showing the results of testing the semiconductor chip of the first example and the semiconductor chip of the comparative example.
[Explanation of symbols]
20 IC chip (semiconductor element)
20A wafer
22 die pad
24 Protective film
33 Thin film layer
36 Thin film layer
37 Thickening layer
38 Transition layer
50 Interlayer resin insulation layer
58 Conductor circuit
60 Bahia Hall
70 Solder resist layer
76 Solder bump
80 Adhesive layer
150 Resin insulation layer
160 Copper plating post
250 Resin insulation layer

Claims (4)

A semiconductor chip having a path head on a semiconductor element,
An insulating substrate having a linear thermal expansion coefficient of 10 to 70 ppm / ° C. obtained by curing a resin containing an inorganic filler having a particle size in the range of 0.1 to 5.0 μm, located on the semiconductor element;
A columnar conductive post formed on the insulating substrate;
Solder bumps formed on the conductive posts and connected to an external substrate located on the insulating substrate;
The conductive posts and the Pas Tsu formed in the interlayer insulating layer that will be positioned between the de, and the conductor layer connecting the two,
An adhesive layer for connecting the semiconductor element via the interlayer insulating layer on the insulating substrate,
A semiconductor chip comprising:   2. The semiconductor chip according to claim 1, wherein the inorganic filler is at least one selected from the group consisting of an aluminum compound, a calcium compound, a potassium compound, a magnesium compound, and a silicon compound.   The elastomer containing at least 1 sort (s) selected from the group which consists of a natural rubber, a synthetic rubber, a thermoplastic resin, and a thermosetting resin is further mix | blended with the resin insulating layer containing the said inorganic filler. The semiconductor chip described in 1. On Pas head of the semiconductor device, it is formed transition layer for connecting to a via hole of the interlayer insulating layer, the transition layer, according to claim 1, characterized in that at least two layers semiconductor Chip.

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