JP3853395B2 - Method for manufacturing thin film transistor - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a method for obtaining a semiconductor having excellent electrical characteristics. Furthermore, the present invention relates to a method for manufacturing a semiconductor device having excellent characteristics. Furthermore, the present invention relates to a method for obtaining a thin film transistor (hereinafter referred to as TFT) having excellent characteristics.
[0002]
[Prior art]
A thin film transistor (generally called TFT) is known as a thin film semiconductor element. This thin film transistor forms a semiconductor device by forming a thin film semiconductor (generally a silicon semiconductor) of several hundreds to several thousands on a substrate having an insulating surface (for example, a glass substrate) and using the thin film semiconductor as an active layer.
[0003]
As an application field of TFT, for example, there are electro-optical devices such as liquid crystal display devices and image sensors. This constitutes a pixel drive and a peripheral driver circuit using TFTs formed directly on a glass substrate.
[0004]
In the case where a glass substrate is used as the substrate, the thin film silicon semiconductor formed on the surface thereof is in an amorphous or crystalline state. The state having crystallinity refers to a polycrystalline state, a microcrystalline state, and a state where amorphous and crystalline structures are mixed.
[0005]
An amorphous TFT is unsatisfactory in operating speed and electrical characteristics, and its application range is limited. On the other hand, when a crystalline silicon film (hereinafter referred to as a crystalline silicon film) is used, high speed operation and high electrical characteristics can be obtained.
[0006]
However, when a TFT is manufactured using a crystalline silicon film, the presence of the OFF current becomes a problem. For example, in a N-channel TFT, when a negative voltage is applied to the gate electrode, in principle, no current flows between the source and drain. This is because when a negative voltage is applied to the gate electrode, the channel portion becomes P-type and a PN junction is formed between the source and drain. However, in practice, there are crystal grain boundaries, defects, and unpaired bonds in the crystalline silicon film, and there are a number of levels resulting from them, and the reverse direction of the PN junction. , Charge transfer through these levels occurs. Therefore, when the electric field concentrates on the PN junction portion, current leaks in the reverse direction between the source and drain via the defect or trap. As a result, when a negative voltage is applied to the gate electrode, a current (OFF current) flows between the source and the drain.
[0007]
In order to solve this problem, there is a method of forming an electric field relaxation region between the channel and the drain so that the electric field does not concentrate between the channel and the drain. This is a technique called LDD (lightly doped drain). This is to form a lightly doped region (weak N type) between the channel (I type) and the drain (N type) so that electric field concentration does not occur at the junction between the channel and the drain. is there.
[0008]
As a method for obtaining the same effect as LDD, a method of providing an offset gate is also known. This is to avoid electric field concentration between the channel and the drain by providing a region that does not function as the drain region between the region functioning as the channel and the drain region.
[0009]
As described above, there is a problem that the off-current of the TFT increases due to defects and traps in the film. Furthermore, defects and traps in the film hinder the movement of carriers in the film and hinder the operation of the TFT.
[0010]
On the other hand, in the TFT, the interface characteristics between the channel and the gate insulating film are extremely important. If the interface characteristics are poor, the TFT characteristics are greatly impaired. This interface characteristic is evaluated by an index called an interface state. This interface state is caused by defects or dangling bonds. In order to obtain a TFT having high characteristics, it is important to reduce the interface state at the interface between the channel and the gate insulating film.
[0011]
[Problems to be solved by the invention]
In order to solve the problem of TFT OFF current and the problem of the interface state at the interface between the channel and the gate insulating film, the present invention provides a level in a thin film silicon semiconductor (these are related to unpaired bonds). It is an object to provide a technique for reducing the risk.
[0012]
Another object of the present invention is to obtain a TFT having excellent characteristics. Another object of the present invention is to obtain a silicon semiconductor film with few levels.
[0013]
[Means for Solving the Problems]
The main configuration of the present invention is as follows.
A method of manufacturing a thin film transistor,
Forming an active layer;
Forming a gate insulating film on the active layer;
Forming a gate electrode on the gate insulating film;
Forming a silicon nitride film covering the gate insulating film and the gate electrode;
Implanting one or more kinds of ions selected from hydrogen, fluorine, and chlorine into the active layer through the gate insulating film and the silicon nitride film;
A step of heat-treating the whole,
It is characterized by having.
[0014]
In the above structure, the substrate having an insulating surface is composed of, for example, a glass substrate, a glass substrate on which an insulating film is formed, a semiconductor substrate on which an insulating film is formed, a metal substrate on which an insulating film is formed, and other insulators. Refers to the substrate.
[0015]
Examples of the silicon semiconductor film include an amorphous silicon semiconductor and a crystalline silicon semiconductor. These silicon semiconductor films are formed by a plasma CVD method or a low pressure thermal CVD method. As the crystalline silicon film, an amorphous silicon film formed by a plasma CVD method or a low pressure thermal CVD method, which is crystallized by heating or irradiation with laser light or strong light equivalent thereto, can be used.
[0016]
As a method for implanting ions, a known ion implantation apparatus or plasma doping apparatus may be used. As a method for producing ions, a method of generating plasma by high-frequency discharge to generate ions, or a method of generating ions by mass separation can be used. The ion implantation apparatus required in the present invention has a configuration in which an ion can be implanted into a substrate by applying an acceleration voltage to at least one kind of ions selected from hydrogen, fluorine, and chlorine. In the present specification, ionized materials are collectively referred to as ions. For example, in the case of hydrogen ions, H⁺Ion, H₂ ⁺Ion, H_Three ⁺Ions and the like will be included.
[0017]
Forming a silicon nitride film and then implanting at least one ion selected from hydrogen, fluorine and chlorine through the silicon nitride film confines the implanted ions in the active layer and maintains the effect This is to make it happen. Hydrogen, fluorine, and chlorine ions have strong bonding strength with silicon and can neutralize dangling bonds of silicon. The silicon nitride film is for maintaining the neutralizing effect. By forming the silicon nitride film, separation of the element can be prevented and the effect can be enhanced. And the stability as a device can be improved.
[0018]
The silicon nitride film functions as a barrier layer against implanted ions. That is, it functions as a barrier layer in which an element selected from hydrogen, fluorine, and chlorine is not degassed. As this barrier layer, an aluminum nitride film, an aluminum oxide film, an aluminum oxynitride film, and a silicon oxynitride film can be used in addition to the silicon nitride film. Aluminum oxynitride is AlO_xN_yIndicated by The silicon oxynitride film is made of SiO_xN_ySince the stress relaxation function is higher than that of the silicon nitride film, it effectively functions as a film covering the device.
[0019]
The whole is heat-treated in order to confine the ions implanted in the previous step in the silicon semiconductor and further promote neutralization of dangling bonds by the implanted elements. The atmosphere for this heat treatment is H₂ , N₂ , Ar, He, O₂ Is possible. It is also effective to make this atmosphere mainly composed of fluorine or chlorine. In particular, when this annealing is performed in an atmosphere containing hydrogen, fluorine, or chlorine as a main component, an effect of neutralizing dangling bonds in the silicon semiconductor or at the interface of the silicon semiconductor can be obtained. In this step, the dangling bonds in the silicon film are neutralized by the implanted ions, and levels (traps) and defects due to the dangling bonds can be reduced.
[0020]
Other main components of the present invention are:
A method of manufacturing a thin film transistor,
Forming an active layer;
Forming a gate insulating film on the active layer;
Implanting one or more kinds of ions selected from hydrogen, fluorine, and chlorine into the active layer through the gate insulating film;
Forming a gate electrode on the gate insulating film;
Forming a silicon nitride film covering the gate insulating film and the gate electrode;
Implanting hydrogen ions into the active layer through the gate insulating film and the silicon nitride film;
A step of heat-treating the whole,
It is characterized by having.
[0021]
In general, when a TFT is formed using a silicon semiconductor film, an insulating gate type field effect transistor is employed. A silicon oxide film or a silicon nitride film is employed as the gate insulating film. In this case, the interface characteristics between the silicon semiconductor film and the gate insulating film are extremely important.
[0022]
Therefore, in the above invention, in the state in which the insulating film is formed on the silicon semiconductor film, ions selected from hydrogen, fluorine, and chlorine are implanted to neutralize the dangling bonds of silicon in the silicon semiconductor. At the same time, the interface state at the interface between the silicon semiconductor and the insulating film is reduced. Since the interface state is caused by the dangling bond, the dangling bond can be neutralized by implantation of ions selected from hydrogen, fluorine, and chlorine. And the interface state can be reduced.
[0023]
In the above structure, the effect can be further increased by setting the projected range of ions selected from hydrogen, fluorine, and chlorine in the vicinity of the interface between the silicon semiconductor film and the insulating film. The projection range is an index that gives the most established depth for the rest position of ions implanted in a solid. Therefore, setting the projected range of the ions in the vicinity of the interface between the silicon semiconductor film and the insulating film means that the most ions are implanted in the vicinity of the interface between the silicon semiconductor film and the insulating film. To do. As a result, neutralization of dangling bonds of silicon is performed mainly in the vicinity of the interface between the silicon semiconductor film and the insulating film, and the interface state at the interface between the silicon semiconductor film and the insulating film can be greatly reduced. it can.
[0024]
In the above configuration, it is more effective to set the projected range of ions selected from hydrogen, fluorine, and chlorine to the silicon semiconductor side at the interface between the silicon semiconductor film and the insulating film. This is because there are more silicon dangling bonds that cause interface states on the silicon semiconductor side.
[0025]
In addition, the whole is confined in a hydrogen atmosphere, an atmosphere containing hydrogen as a main component, or an atmosphere containing fluorine or chlorine as a main component, thereby confining the elements neutralizing dangling bonds and stabilizing the state. Can be obtained.
[0026]
Another main configuration of the present invention is to implant ions of an element selected from ionized hydrogen, fluorine, and chlorine through a layer functioning as a barrier layer, and thereafter The heat treatment is performed.
[0027]
Furthermore, another main configuration of the present invention is characterized in that ions of an element selected from ionized hydrogen, fluorine, and chlorine are implanted into an active layer formed of a silicon semiconductor film using a gate electrode as a mask. . When hydrogen is selected as the element to be implanted and plasma doping is used, H⁺Ion, H₂ ⁺Ion, H_Three ⁺Ions will be implanted, but H₂ ⁺Ion and H_Three ⁺Since ions have a large ion radius, they are prevented by gate electrodes. That is, the gate electrode serves as a mask. Therefore, H₂ ⁺Ion and H_Three ⁺Considering ions, ion implantation is performed using the gate electrode as a mask.
[0028]
[Action]
By implanting ionized hydrogen into the silicon film, the dangling bonds in the silicon film can be neutralized, and the electrical characteristics can be improved.
[0029]
In particular, after forming a silicon nitride film, ions of hydrogen, fluorine or chlorine are implanted, and then heat treatment is performed in a hydrogen atmosphere, so that the implanted atoms are confined in the silicon film by the action of the silicon nitride film. The effect of neutralizing trap levels and defects by the atoms can be increased.
[0030]
In addition, after ion implantation of impurities into the silicon film and laser light irradiation, hydrogen, fluorine, or chlorine ions are implanted into the silicon film through the silicon nitride film, and then desorbed by ion implantation or laser light irradiation. Hydrogen, fluorine or chlorine can be supplemented.
[0031]
In addition to the above implantation of hydrogen, fluorine, or chlorine ions, heat treatment is further performed in the atmosphere containing the implanted atoms or the atmosphere of the element, thereby confining the implanted ions in the silicon film. And the effect can be further increased.
[0032]
【Example】
A manufacturing process of a TFT using the present invention will be described below. In each example shown below, an example in which the present invention is implemented in each manufacturing process of a TFT is shown, but it is also possible to combine a plurality of examples. For example, hydrogen, fluorine, or chlorine ions can be implanted in a plurality of necessary steps.
[0033]
[Example 1]
In this embodiment, hydrogen ions are implanted into a crystalline thin silicon semiconductor film (referred to as a crystalline silicon film) formed on a substrate having an insulating surface, and exists in the crystalline silicon film. It eliminates dangling bonds and defects and reduces traps in the film. This is an example of manufacturing a TFT using this crystalline silicon film.
[0034]
FIG. 1 shows a manufacturing process of this embodiment. In this embodiment, an example in which a glass substrate is used as a substrate having an insulating surface and a TFT is formed on the surface is shown. First, Corning 7059 glass is prepared as the glass substrate 11. A silicon oxide film (not shown) serving as a base film is formed on the surface to a thickness of 2000 mm by sputtering. Next, an amorphous silicon film is formed to a thickness of 1000 mm by plasma CVD or low pressure thermal CVD. Then, the amorphous silicon film is crystallized by heating, irradiation with laser light or strong light, or a combination of them. A crystalline silicon film is thus obtained.
[0035]
Next, the crystalline silicon film is patterned into a shape required as an active layer of the TFT to obtain an active layer indicated by 12 in FIG.
[0036]
Next, a silicon oxide film 13 to be a gate insulating film is formed to a thickness of 1000 mm by sputtering. And the film | membrane which has aluminum as a main component is formed by the vapor deposition method in the thickness of 5000 mm. The gate electrode 14 is formed by patterning this aluminum-based film. Further, an oxide layer 15 is formed around the gate electrode 14 made of a material mainly composed of aluminum by using an anodic oxidation method. The oxide layer 15 is formed to a thickness of 2000 mm, for example. The presence of the oxide layer 15 makes it possible to form an offset gate region by forming a mask on the side surface of the gate electrode 14 in an ion implantation step of an impurity imparting one conductivity type later. (Fig. 1 (B))
[0037]
Note that the gate electrode may be composed of another metal material, a semiconductor material, or a laminate or a mixture thereof.
[0038]
Then, P (phosphorus) ions are implanted, and P ions are implanted into the regions 16 and 18. At this time, the oxide layer 15 serves as a mask, and a portion indicated by 10 can be provided as an offset gate region.
[0039]
In this embodiment, since P ions are implanted in this step, the completed TFT is an N-channel type. If B ions are implanted here, a P-channel TFT can be obtained.
[0040]
Next, the activation of the P ions implanted in the step (B) and annealing by laser light irradiation are performed to recover the damage received during the ion implantation. Here, using a KrF excimer laser, 100 to 300 mJ / cm² One to several shots are irradiated at a power density of 1 to 10. In this step, it is effective to use heating at about 300 ° C. simultaneously with laser light irradiation. Thus, source / drain regions 16/18 can be formed. At the same time, a channel formation region 17 is formed in a self-aligning manner.
[0041]
Further, instead of laser light irradiation, annealing may be performed by irradiating the same intense light, for example, infrared light. Infrared light is hardly absorbed by the glass substrate and easily absorbed by silicon, so that only silicon can be selectively heated. Such heating using infrared light is called RTA (rapid thermal annealing). Further, annealing may be performed using a heating means such as a heater.
[0042]
Next, a silicon nitride film 23 is formed to a thickness of 1000 mm by a plasma CVD method using silane and ammonia as source gases. This silicon nitride film is made of Si_Three N_4-x(−0.3 ≦ x ≦ 1).
[0043]
Then, hydrogen ions are implanted through the silicon nitride film 23 under the following conditions by ion doping. (Figure 1 (C))
Acceleration voltage: 40 KeV
Dose amount: 1 × 10¹⁶cm^-2
[0044]
The hydrogen ions implanted in the hydrogen ion implantation step are confined in the active layer because the silicon nitride film 23 exists. In other words, the implanted ions can be prevented from being released to the outside later. Further, by implanting hydrogen ions as described above, the concentration of the hydrogen element in the active layer becomes about 0.001 atomic% to 5 atomic%. Of course, this numerical value can be controlled by the above doping conditions.
[0045]
FIG. 9 shows a concentration distribution of hydrogen element after hydrogen ions are implanted under the above-described conditions of FIG. FIG. 8 shows the concentration distribution of the hydrogen element in the state shown in FIG. 1C using the SIMS (secondary ion analysis method) for the source / drain regions. As can be seen from FIG. 8, the concentration of hydrogen element is maximum at a depth of about 2100 mm. Since the silicon oxide film 13 having a thickness of 1000 mm and the silicon nitride film 23 having a thickness of 1000 mm are provided on the active layer, the depth of about 2100 mm from the surface shown in FIG. This is a place about 100 mm deep from the surface of the active layer.
[0046]
In the active layer, the dangling bonds in the vicinity of the interface between the active layer and the silicon oxide film 13 which is the gate insulating film cause the presence of interface states. Existence of sigma has a great effect on reducing the interface state.
[0047]
Here, the plasma doping method is used because of its high productivity. As a method for implanting hydrogen ions, there is an ion doping method, but this involves a problem that mass separation is required and productivity for a large area is low.
[0048]
When hydrogen ions are implanted using the plasma doping method as in this embodiment, H⁺Ion, H₂ ⁺Ion, H_Three ⁺Ions are implanted. H⁺The ions pass through the gate electrode and enter the channel formation region 17, but H₂ ⁺Ion, H_Three ⁺Since ions have a large ion radius, they are prevented by the gate electrode and implanted into the source / drain regions 16 and 18. That is, the source / drain region has H⁺Ion and H₂ ⁺Ion and H_Three ⁺Ions are implanted. The effect of injecting hydrogen ions into the source / drain region through the silicon nitride film as the barrier layer is extremely great, and a considerable effect can be obtained without injecting hydrogen ions into the channel formation region. Can do. Therefore, a considerable effect can be obtained even by using a plasma doping method in which hydrogen ions are mainly implanted into the source / drain regions. In addition, when the plasma doping method is used, ion implantation can be performed on a large area, so that another effect of excellent productivity can be obtained.
[0049]
Next, a silicon oxide film is formed as an interlayer insulating film 19 to a thickness of about 8000 mm by a plasma CVD method using TEOS as a raw material. In the formation of the silicon oxide film by this plasma CVD method, it is necessary to set the heating temperature to 350 ° C. or less. This is to prevent the detachment of the hydrogen ions implanted in the step (C). Further, since the silicon nitride film 23 is present, it is possible to prevent hydrogen from being detached in this step.
[0050]
Next, hole patterning for wiring is performed, and electrodes 20 and 21 are formed using a multilayer film of aluminum or aluminum and another metal. Further, a silicon nitride film 22 is formed as a final coat film to a thickness of 1000 to 5000 mm, for example, 3000 mm. The silicon nitride film 22 may be formed by a plasma CVD method using silane and ammonia as source gases. (Figure 1 (D))
[0051]
Finally, hydrogen annealing is performed for 1 hour at a temperature of 200 to 450 degrees in a normal-pressure hydrogen atmosphere to complete the TFT. By this hydrogenation annealing, the hydrogen ion-implanted in the step (A) can be confined in the active layer, and the dangling bonds and defects in the active layer can be reduced more thoroughly. Note that hydrogen annealing can be performed before the formation of the silicon nitride film that is the final coat film, and then the final coat film can be formed to prevent hydrogen desorption. In this step, hydrogen enters the active layer through the contact hole between the electrodes 20 and 21, and the active layer is hydrogenated.
[0052]
FIG. 7 shows characteristics (A) of a TFT manufactured by the process shown in this embodiment and characteristics (B) of a TFT manufactured without hydrogen ion implantation in the structure shown in this embodiment. . As apparent from FIG. 7, the OFF current can be reduced by performing the hydrogen ion implantation shown in this embodiment. This is because the dangling bonds of silicon in the active layer can be neutralized by the action of hydrogen ions, thereby causing defects and levels that cause leakage current (OFF current). It is understood that this could be reduced.
[0053]
[Example 2]
In this embodiment, a silicon nitride film is formed after forming a gate electrode, and then impurity ions are implanted for forming source / drain regions, and hydrogen ions are implanted.
[0054]
FIG. 2 illustrates a manufacturing process of this embodiment. The reference numerals shown in FIG. 2 indicate the same parts as those shown in FIG. 1 unless otherwise specified. In this embodiment, a Corning 7059 glass substrate is used as the substrate having an insulating surface. First, a silicon oxide film is formed on the glass substrate 11 as a base film (not shown) to a thickness of 2000 mm by sputtering.
[0055]
Next, an amorphous silicon film is formed to a thickness of 1000 mm by plasma CVD or low pressure thermal CVD. Then, the amorphous silicon film is crystallized by heating, irradiation with laser light or strong light, or a combination of them. A crystalline silicon film is thus obtained.
[0056]
Next, the crystalline silicon film is patterned into a shape required as an active layer of the TFT. Further, a silicon oxide film 13 serving as a gate insulating film is formed to a thickness of 1000 mm by sputtering. (Fig. 2 (A))
[0057]
Next, a film containing aluminum as a main component is formed to a thickness of 5000 mm by vapor deposition. The gate electrode 14 is formed by patterning this aluminum-based film. Further, an oxide layer 15 is formed around the gate electrode 14 made of a material mainly composed of aluminum by using an anodic oxidation method. The oxide layer 15 is formed to a thickness of 2000 mm, for example.
[0058]
Note that the gate electrode may be composed of another metal material, a semiconductor material, or a laminate or a mixture thereof.
[0059]
Next, a silicon nitride film 23 is formed to a thickness of 1000 mm by plasma CVD using silane and ammonia as raw materials. (Fig. 2 (B))
[0060]
Then, P (phosphorus) ions are implanted, and P ions are implanted into the regions 16 and 18. At this time, the oxide layer 15 and the silicon nitride film 23 serve as a mask, and a portion indicated by 10 can be provided as an offset gate region. (Fig. 2 (C))
[0061]
In this embodiment, since P ions are implanted in this step, the completed TFT is an N-channel type. If B ions are implanted here, a P-channel TFT can be obtained.
[0062]
Next, in order to activate the P ions implanted in the step (C) and recover the damage received at the time of ion implantation, a process is performed by laser light irradiation. Here, using a KrF excimer laser, 100 to 300 mJ / cm² One to several shots are irradiated at a power density of 1 to 10. In this step, it is effective to use heating at about 300 ° C. simultaneously with laser light irradiation. In this way, source / drain regions 16/18 can be obtained. Further, the channel formation region 17 is formed in a self-aligning manner.
[0063]
The annealing process may be performed by RTA or heating by the infrared light irradiation described above.
[0064]
Next, hydrogen ions are implanted to reduce traps and defects present in the active layer. The hydrogen ion implantation conditions are as follows. (Fig. 2 (D))
Acceleration voltage: 40 KeV
Dose amount: 1 × 10¹⁶cm^-2
[0065]
Next, a silicon oxide film is formed as an interlayer insulating film 19 to a thickness of about 8000 mm by a plasma CVD method using TEOS as a raw material. In the formation of the silicon oxide film by this plasma CVD method, it is necessary to set the heating temperature to 350 ° C. or less. This is to prevent the separation of hydrogen ions implanted in the step (B).
[0066]
Next, hole patterning for wiring is performed, and electrodes 20 and 21 are formed using a multilayer film of aluminum or aluminum and another metal. Further, a silicon nitride film 22 is formed as a final coat film. (Figure 2 (E))
[0067]
Finally, hydrogen annealing is performed for 1 hour at a temperature of 200 to 450 degrees in a normal-pressure nitrogen atmosphere to complete the TFT. This hydrogenation annealing is for confining the hydrogen ion-implanted in the step (B) in the active layer and further thoroughly reducing dangling bonds and defects in the active layer.
[0068]
Example 3
In this embodiment, traps and defects are reduced at the interface between the active layer and the gate insulating film and in the vicinity thereof. FIG. 3 shows a manufacturing process of this example. First, a glass substrate on which a silicon oxide film as a base film is formed to a thickness of 2000 mm is prepared. Here, a Corning 7059 glass substrate is used.
[0069]
An amorphous silicon film is formed on the glass substrate 11 on which the base film is formed to a thickness of 1000 mm by plasma CVD or low pressure thermal CVD. Then, the amorphous silicon film is crystallized by heating, irradiation with laser light or strong light, or a combination of them. A crystalline silicon film is thus obtained.
[0070]
Next, an active layer 12 is obtained by patterning the crystalline silicon film into a shape required as an active layer of the TFT. Then, a silicon oxide film 13 is formed as a gate insulating film by sputtering. Then, hydrogen ions are implanted under the following conditions. (Fig. 3 (A))
Acceleration voltage: 40 KeV
Dose amount: 1 × 10¹⁶cm^-2
[0071]
By performing the ion implantation, traps and defects at the active layer 12, particularly at the interface between the channel formation region and the gate insulating film and in the vicinity thereof can be reduced. In order to further enhance the ion implantation effect, it is effective to set the projected range in the hydrogen ion implantation in the vicinity of the interface between the active layer 12 and the silicon oxide film 13 which is a gate insulating film. In this way, the effect of implanting hydrogen ions can be obtained at the interface between the active layer 12 and the gate insulating film and in the vicinity thereof.
[0072]
Next, a film containing aluminum as a main component is formed to a thickness of 5000 mm by vapor deposition. The gate electrode 14 is formed by patterning this aluminum-based film. Further, an oxide layer 15 is formed around the gate electrode 14 made of a material mainly composed of aluminum by using an anodic oxidation method. The oxide layer 15 is formed to a thickness of 2000 mm, for example.
[0073]
Then, P (phosphorus) ions are implanted, and P ions are implanted into the regions 16 and 18. At this time, the oxide layer 15 and the silicon nitride film 23 serve as a mask, and a portion indicated by 10 can be provided as an offset gate region. (Figure 3 (C))
[0074]
Here, hydrogen ions are implanted. The ion implantation conditions are as follows. (Fig. 3 (D))
Acceleration voltage: 40 KeV
Dose amount: 2 × 10¹⁶cm^-2
[0075]
Next, activation of the P ions and hydrogen ions implanted in the steps (C) and (D) and laser irradiation to recover the damage received during the P ion implantation in the step (C) are performed. Do the work. Here, using a KrF excimer laser, 100 to 300 mJ / cm² One to several shots are irradiated at a power density of 1 to 10. In this step, it is effective to use heating at about 300 ° C. simultaneously with laser light irradiation. (Not shown)
[0076]
The annealing step may be performed by RTA or heating as in the above-described infrared light irradiation.
[0077]
Next, in the same manner as in the other examples, the formation of an interlayer insulating film, the patterning of holes for wiring, the formation of an electrode using aluminum or a multilayer film of aluminum and another metal, the hydrogen atmosphere at normal pressure A TFT is completed by performing heat treatment in the inside.
[0078]
Example 4
This embodiment is mainly characterized in that, in the TFT manufacturing process, hydrogen ion field implantation is performed after the gate electrode is formed, and a barrier layer made of a silicon nitride film is formed.
[0079]
FIG. 4 shows a manufacturing process of this example. In this embodiment, an example in which a glass substrate is used as a substrate having an insulating surface and a TFT is formed on the surface is shown. First, Corning 7059 glass is prepared as the glass substrate 11. A silicon oxide film (not shown) serving as a base film is formed on the surface to a thickness of 2000 mm by sputtering. Next, an amorphous silicon film is formed to a thickness of 1000 mm by plasma CVD or low pressure thermal CVD. Then, the amorphous silicon film is crystallized by heating, irradiation with laser light or strong light, or a combination of them. A crystalline silicon film is thus obtained.
[0080]
Next, the crystalline silicon film is patterned into a shape required as an active layer of the TFT to obtain an active layer indicated by 12 in FIG.
[0081]
Next, a silicon oxide film 13 to be a gate insulating film is formed to a thickness of 1000 mm by sputtering. And the film | membrane which has aluminum as a main component is formed by the vapor deposition method in the thickness of 5000 mm. The gate electrode 14 is formed by patterning this aluminum-based film. Further, an oxide layer 15 is formed around the gate electrode 14 made of a material mainly composed of aluminum by using an anodic oxidation method. The oxide layer 15 is formed to a thickness of 2000 mm, for example. The presence of the oxide layer 15 makes it possible to form an offset gate region by forming a mask on the side surface of the gate electrode 14 in an ion implantation step of an impurity imparting one conductivity type later. (Fig. 4 (B))
[0082]
Note that the gate electrode may be composed of another metal material, a semiconductor material, or a laminate or a mixture thereof.
[0083]
Then, P (phosphorus) ions are implanted, and P ions are implanted into the regions 16 and 18. At this time, the oxide layer 15 serves as a mask, and a portion indicated by 10 can be provided as an offset gate region.
[0084]
In this embodiment, since P ions are implanted in this step, the completed TFT is an N-channel type. If B ions are implanted here, a P-channel TFT can be obtained.
[0085]
Next, hydrogen ions are implanted through the silicon nitride film under the following conditions by ion doping. (Fig. 4 (B))
Acceleration voltage: 35 KeV
Dose amount: 1 × 10¹⁶cm^-2
[0086]
Here, the plasma doping method is used because of its high productivity. As a method for implanting hydrogen ions, there is an ion doping method, but this involves a problem that mass separation is required and productivity for a large area is low.
[0087]
Next, activation of P ions implanted in the step (B), recovery of damage received during the ion implantation, and annealing by irradiation with laser light are performed to activate hydrogen ions. Here, using a KrF excimer laser, 100 to 300 mJ / cm² One to several shots are irradiated at a power density of 1 to 10. In this step, it is effective to use heating at about 300 ° C. simultaneously with laser light irradiation. Thus, source / drain regions 16/18 can be formed. At the same time, a channel formation region 17 is formed in a self-aligning manner. Furthermore, the implanted hydrogen ions can be activated.
[0088]
Further, instead of laser light irradiation, annealing may be performed by irradiating the same intense light, for example, infrared light. Infrared light is hardly absorbed by the glass substrate and easily absorbed by silicon, so that only silicon can be selectively heated. Such heating using infrared light is called RTA (rapid thermal annealing). Further, annealing may be performed using a heating means such as a heater.
[0089]
Next, a silicon nitride film 23 functioning as a barrier layer for preventing the implanted hydrogen ions from being degassed is formed to a thickness of 1000 mm by plasma CVD using silane and ammonia as source gases. This silicon nitride film is made of Si_Three N_4-x(−0.3 ≦ x ≦ 1). (Fig. 4 (C))
[0090]
By forming the silicon nitride film 23 as a barrier layer, the implanted hydrogen ions can be confined in the active layer, and the implanted hydrogen ions are not released to the outside later. Can do.
[0091]
Next, a silicon oxide film is formed as an interlayer insulating film 19 to a thickness of about 8000 mm by a plasma CVD method using TEOS as a raw material. In the formation of the silicon oxide film by this plasma CVD method, it is necessary that the heating temperature be 350 ° C. or less, preferably 300 ° C. to 350 ° C. This is to prevent separation of hydrogen ions implanted in the step (B). Further, since the silicon nitride film 23 is present, it is possible to prevent hydrogen from being detached in this step.
[0092]
Next, hole patterning for wiring is performed, and electrodes 20 and 21 are formed using a multilayer film of aluminum or aluminum and another metal. Further, a silicon nitride film 22 is formed as a final coat film to a thickness of 1000 to 5000 mm, for example, 3000 mm. The silicon nitride film 22 may be formed by a plasma CVD method using silane and ammonia as source gases.
[0093]
Finally, heat treatment at 350 ° C. is performed in an oxygen, nitrogen, argon or helium atmosphere. By this heat treatment, the implanted hydrogen ions are finally activated, and defects and dangling bonds are neutralized. Thus, the TFT is completed. (Fig. 4 (D))
[0094]
Example 5
This embodiment shows an example of a TFT (referred to as C / TFT) in which a P-channel TFT and an N-channel TFT are configured in a complementary manner. FIG. 5 shows an example of a TFT configured as a complementary type of this embodiment. In this embodiment, a glass substrate 501 is used. First, a silicon oxide film 502 is formed as a base film on a glass substrate 501 to a thickness of 2000 mm by sputtering. Next, a semiconductor layer constituting the active layer is formed. Here, an amorphous silicon film is formed to a thickness of 1000 mm by plasma CVD or LPCVD. Then, crystallization by heating or crystallization by intense light or laser light irradiation is performed to form a silicon film having crystallinity. This silicon film is panned, and an N-channel TFT and a P-channel active layer 503 are formed later.
[0095]
Next, a gate insulating film 504 is formed to a thickness of 1000 mm by sputtering or plasma CVD. Further, a gate electrode 506 and 507 are formed by forming a film mainly composed of aluminum to a thickness of 5000 mm and performing patterning. A gate electrode indicated by 506 is a gate electrode of an N-channel TFT, and a gate electrode indicated by 507 is a gate electrode of a P-channel TFT.
[0096]
Here, in the ethylene glycol solution containing 1 to 5% of tartaric acid, the gate electrodes 506 and 507 are used as anodes to perform anodic oxidation to form oxide layers 508 and 509. The thickness of this oxide layer is about 2000 mm. The thickness of the oxide layer can be used as a mask in the subsequent impurity ion implantation step to form an offset gate region.
[0097]
Next, a silicon nitride film 510 functioning as a barrier layer against hydrogen ions is formed to a thickness of 2000 mm. Then, a region where one TFT is formed is masked with a resist 511, and phosphorus (P) ions are implanted. Thus, impurity regions 512 and 516 are formed. The impurity regions 512 and 516 serve as source / drain regions. At the same time, offset regions 513 and 515 are formed. At the same time, a channel formation region 514 is formed.
[0098]
Next, the resist 511 is removed, and the TFT region where the phosphorus (P) ions have been previously implanted is masked with a resist (not shown), and boron (B) ions are implanted. Thus, source / drain regions 517 and 521, offset gate regions 518 and 520, and a channel formation region 519 are formed.
[0099]
Next, the resist is removed, and hydrogen ions are implanted into the whole as shown in FIG. At this time, hydrogen ions are implanted into the active layer region through the silicon nitride film 510 serving as a barrier layer.
[0100]
Next, activation is performed by irradiation with laser light or strong light. Each source / drain region is completed.
[0101]
Next, an interlayer insulating film 522 is formed by a plasma CVD method. Then, contact holes are formed. A source or drain electrode 523 of NTFT which is one TFT (TFT on the left side of the drawing), a drain or source electrode 525 of PTFT which is the other TFT (TFT on the right side of the drawing), and a common electrode of one output of the two TFTs 524.
[0102]
Finally, heat treatment is performed at 350 ° C. in a nitrogen atmosphere to activate the implanted hydrogen ions (in this step, dangling bonds are neutralized with silicon), and complementary TFTs (C / C TFT) is completed.
[0103]
Example 6
FIG. 6 shows a block diagram of an electro-optical system using an integrated circuit in which a display, a CPU, and a memory are mounted on a single glass substrate. Here, the input port reads an externally input signal and converts it into an image signal, and the correction memory is a memory specific to the panel for correcting the input signal etc. in accordance with the characteristics of the active matrix panel. is there. In particular, this correction memory has information specific to each pixel as a non-volatile memory, and is used for individual correction. That is, if a pixel of the electro-optical device has a point defect, a signal corrected accordingly is sent to the pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when the pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so that the brightness is the same as that of the surrounding pixels.
[0104]
The CPU and the memory are the same as those of an ordinary computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. Moreover, the backlight which irradiates a board | substrate from a back surface can also be changed according to image information.
[0105]
As the TFT used in this embodiment, the TFT described in this specification can be used as appropriate.
[0106]
Example 7
This embodiment is an example in which fluorine ions are implanted instead of hydrogen ions in the hydrogen ion implantation step shown in the first embodiment. In this embodiment, fluorine ions are implanted using a plasma doping method. Here, fluorine gas or silicon tetrafluoride (SiF) is used as a doping gas._Four ) Is used. The projection range is set near the interface between the active layer and the gate insulating film. Specific conditions are shown below. Acceleration voltage: 60 KeV
Dose amount: 1 × 10¹⁶cm^-2
[0107]
Example 8
The present embodiment is an example in which chlorine ions are implanted instead of hydrogen ions in the hydrogen ion implantation step shown in the first embodiment. In this embodiment, chlorine ions are implanted using a plasma doping method. Here, chlorine gas is used as the doping gas. The projection range is set near the interface between the active layer and the gate insulating film. Specific conditions are shown below.
Acceleration voltage: 60 KeV
Dose amount: 1 × 10¹⁶cm^-2
【The invention's effect】
By implanting hydrogen ions into the silicon semiconductor film through the silicon nitride film, dangling bonds in the silicon semiconductor film can be neutralized, and the level inside the silicon semiconductor film can be reduced. it can. A TFT having high characteristics can be obtained by manufacturing a TFT using a semiconductor film into which hydrogen ions are implanted.
[Brief description of the drawings]
FIG. 1 shows a manufacturing process of an example.
FIG. 2 shows a manufacturing process of the example.
FIG. 3 shows a manufacturing process of the example.
FIG. 4 shows a manufacturing process of the example.
FIG. 5 shows a manufacturing process of the example.
FIG. 6 shows a manufacturing process of the example.
FIG. 7 shows characteristics of a TFT manufactured in an example.
FIG. 8 shows the concentration distribution of implanted hydrogen ions.
[Explanation of symbols]
11 .... Glass substrate
12 ... Active layer
13... Silicon oxide film
14 ... Gate electrode
15 .... Oxide layer
16... Source / drain region
18... Drain / source region
17... Channel formation region
19. Interlayer insulating film
20... Electrode
21... Electrode
22... Silicon nitride film
23... Silicon nitride film
501 ... Glass substrate
502... Base film (silicon oxide film)
503 ... Active layer
504... Gate insulating film (silicon oxide film)
506 ... Gate electrode
507 ... Gate electrode
508 ... Oxide layer
509 ... Oxide layer
510... Silicon nitride film (barrier layer)
511 ... resist
512... Source / drain region
513: Offset gate area
514 ... Channel formation region
515: Offset gate area
516... Drain / source region
517... Drain / source region
518 ... Offset gate area
519 ... Channel formation region
520: Offset gate area
521... Source / drain region
522 ... Interlayer insulating film
523 ... Electrode
524 ... Electrode
525 ... Electrode

Claims (14)

Forming a silicon semiconductor film over a substrate having an insulating surface;
Forming a gate insulating film on the silicon semiconductor film;
Ionizing and injecting a hydrogen element or a compound comprising the hydrogen element into the silicon semiconductor film through the gate insulating film,
Forming a gate electrode on the gate insulating film;
Forming a silicon nitride film covering the gate insulating film and the gate electrode;
A source region and a drain region are formed by implanting an impurity imparting one conductivity type using the gate electrode as a mask,
From the silicon nitride film, ionizing and implanting a hydrogen element or a compound comprising the hydrogen element using the gate electrode as a mask,
A method for manufacturing a thin film transistor, wherein the silicon semiconductor film is heated. In claim 1,
A method for manufacturing a thin film transistor, characterized by ionizing the hydrogen element or a compound including the hydrogen element and implanting any one of H ⁺ ions , H ₂ ⁺ ions, and H ₃ ⁺ ions into the silicon semiconductor film. Forming a silicon semiconductor film over a substrate having an insulating surface;
Forming a gate insulating film on the silicon semiconductor film;
Fluorine element or a compound composed of the fluorine element is ionized and injected into the silicon semiconductor film through the gate insulating film,
Forming a gate electrode on the gate insulating film;
Forming a silicon nitride film covering the gate insulating film and the gate electrode;
A source region and a drain region are formed by implanting an impurity imparting one conductivity type using the gate electrode as a mask,
Fluorine element or a compound comprising the fluorine element is ionized and implanted from above the silicon nitride film using the gate electrode as a mask,
A method for manufacturing a thin film transistor, wherein the silicon semiconductor film is heated. Forming a silicon semiconductor film over a substrate having an insulating surface;
Forming a gate insulating film on the silicon semiconductor film;
It said gate insulating film through a consisting of chlorine element or the chlorine element in the silicon semiconductor film compound was injected ionized,
Forming a gate electrode on the gate insulating film;
Forming a silicon nitride film covering the gate insulating film and the gate electrode;
A source region and a drain region are formed by implanting an impurity imparting one conductivity type using the gate electrode as a mask,
From the silicon nitride film, the gate electrode is used as a mask to ionize and inject chlorine element or a compound composed of the chlorine element,
A method for manufacturing a thin film transistor, wherein the silicon semiconductor film is heated. In any one of Claims 1 thru | or 4 ,
The silicon nitride is _Si 3 _{N (4-x)} a method for manufacturing a thin film transistor which is characterized by being represented by (-0.3 ≦ x ≦ 1). In any one of Claims 1 thru | or 5 ,
The method for manufacturing a thin film transistor, which comprises heating a pre-Symbol silicon semiconductor film at normal pressure atmosphere. In any one of Claims 1 thru | or 5 ,
Hydrogen, nitrogen, argon, helium, oxygen, a method for manufacturing a thin film transistor, which comprises heating a pre-Symbol silicon semiconductor film in an atmosphere that fluorine and mainly composed of one of chlorine. In any one of Claims 1 thru | or 7 ,
A method for manufacturing a thin film transistor , wherein the ion implantation method is a plasma doping method. In any one of Claims 1 thru | or 8 ,
And characterized in that before after forming a source region and a drain region by implanting an impurity imparting one conductivity type Kige sites electrode as a mask, activated by irradiating laser to the source region and the drain region A method for manufacturing a thin film transistor. In any one of Claims 1 thru | or 8 ,
After forming the source and drain regions by implanting impurity imparting before one conductivity type a Kige sites electrode as a mask, to activate by irradiating infrared light on the source region and the drain region A method for manufacturing a thin film transistor. In any one of Claims 1 thru | or 10 ,
A method for manufacturing a thin film transistor , comprising forming an interlayer insulating film at a heating temperature of 350 ° C. or lower after ions are implanted into the source region and the drain region. In any one of Claims 1 thru | or 11 ,
A method for manufacturing a thin film transistor, wherein the silicon semiconductor film is a crystalline silicon film crystallized by laser irradiation. In any one of Claims 1 thru | or 12 ,
A method of manufacturing a thin film transistor , wherein the gate insulating film is made of a silicon oxide film or a silicon nitride film. In any one of Claims 1 thru | or 13 ,
The gate electrode is a method for manufacturing a thin film transistor which is characterized by comprising a multilayer film of a material that material and aluminum main component, or a semiconductor material and the aluminum main component.

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