JP3854021B2 - Computer chipset for computer motherboard referring to various clock rates - Google Patents

Description

[0001]
Background of the Invention
1. TECHNICAL FIELD OF THE INVENTION
[0002]
The present invention relates to a chip set used on a computer motherboard, and more particularly to a computer chip set designed for computer motherboards having various clock rates. The computer motherboard allows various clock speeds to be used to run various data processing devices such as high performance CPUs and storage devices.
2. Explanation of related technology
[0003]
A central processing unit (hereinafter referred to as “CPU”) is the heart of a personal computer. In general, CPU performance depends mainly on the speed of the clock signal used to run the CPU. Conventionally, the clock rate of a CPU has been several megahertz. However, due to the development of semiconductor technology, it is now progressing to several hundred megahertz. An old CPU with a low clock rate on a computer motherboard can be upgraded to a new one with a higher clock rate by simply replacing the old CPU with a new one. However, concerns arise that related devices operating in conjunction with a CPU, such as a DRAM (dynamic random memory), cannot keep up with the faster speed provided by the new CPU. Therefore, a chip set for a computer motherboard needs to be able to provide various clock rates that can be selected by the CPU. For example, in a high-end computer motherboard, 100 MHz, 83 MHz, or 66 MHz may be selected as the CPU clock rate. As the DRAM clock rate, 100 MHz, 83 MHz, 66 MHz, or 50 MHz can be selected. 66 MHz or 33 MHz can be selected as a clock rate for PCI (Peripheral Component Interconnect) control. Finally, 133 MHz or 66 MHz can be selected as a clock rate for AGP (Accelerated Graphics Port) control.
[0004]
If these devices are set to different clock rates, the transmission of data and signals between these devices can even cause the computer system to stop. Therefore, in order to handle different clock rates, a suitable interface method needs to be provided between these devices.
[0005]
The conventional solution to the above problem is to run the CPU and DRAM once for each individual pulse until the current pulse finishes, regardless of their clock rate ratio. It is a method of letting. This causes a significant decrease in performance because a wait state is caused during data processing.
[0006]
Another conventional solution is to run the CPU and DRAM at the same clock rate. However, a DRAM that can operate at a high clock rate equivalent to a high-end CPU is usually too expensive. Since modern CPUs are generally provided with a cache memory, the use of a slow DRAM does not significantly affect the overall system performance. However, if a low-speed DRAM is used directly with a high-speed CPU, the actual operation of the computer system becomes extremely unstable. As a result, the system can be destroyed or stopped.
[0007]
In addition, personal computers must pass an EMI (Electromagnetic Interference) test before entering the market because electromagnetic radiation from electrical appliances can adversely affect health. Electromagnetic radiation from a fast CPU has a high frequency and can cause a higher level of interference. In order to reduce the EMI effect, several solutions have been proposed, such as lowering the CPU clock rate or shortening the signal transmission path between the CPU and DRAM. In a high-speed CPU, it is easy to shorten the signal transmission path in order to reduce the EMI effect. However, in a DRAM, the signal transmission path can hardly be shortened. This is because DRAM is generally provided in units mounted in slots on a motherboard. Therefore, if the DRAM shares the same high clock rate as the CPU, the EMI problem is very important.
[0008]
In summary, conventional computer motherboards with various clock rates have the following disadvantages.
(1) The conventional method of causing the CPU and DRAM to execute one process at the appearance of each pulse until the current pulse process is completed requires a waiting state and wastes time. Cause low.
(2) Since all sequence control needs to be considered in the design, its wide boundary conditions make the circuit structure very complicated, difficult to debug, increase the mounting area, and reduce the manufacturing cost. Make the effect worse.
(3) If the DRAM shares the same high clock rate of the CPU, the signal transmission path for the DRAM cannot be shortened, so the EMI effect becomes very serious.
Summary of the Invention
[0009]
An object of the present invention is to provide a computer chip set for a computer motherboard having a minimum of two clock rates in order to convert one signal referring to the first clock rate into another signal referring to the second clock rate. It is to provide.
[0010]
It is another object of the present invention to provide a computer chip set for a computer motherboard that is very efficient in processing data and signals referring to various clock rates and has no waiting state.
[0011]
Yet another object of the present invention is to use a storage device at a high clock rate used by the CPU and another low clock rate to reduce the cost of the storage device and also reduce the EMI effects from the storage device. It is to provide a computer chip set for a computer motherboard that can be used.
[0012]
In accordance with the foregoing and other objects of the present invention, a computer chipset for a computer motherboard that references various clock rates is provided. In particular, the computer chip set of the present invention includes a first clock rate for converting an input signal referring to one of the first and second clock rates into an output signal referring to the other clock rate. Invented for use on a computer motherboard having at least two clock rates including a second clock rate. The ratio between the first clock rate and the second clock rate is m: n. m and n are relatively prime and m> n. The first and second clock rates are substantially synchronized. That is, the difference between the start time of the i-th cycle of the first clock rate and the start time of the j-th cycle of the second clock rate is smaller than the predetermined time. Here, i and j are positive integers.
[0013]
The computer chip set of the present invention includes a phase signal generator that can generate m phase signals that can be sequentially switched and are enabled for a period equal to one period of the first clock rate.
[0014]
The computer motherboard further includes a first subsystem that references the first clock rate, a second subsystem that references the second clock rate, and a third subsystem that references the third clock rate. The third clock rate is either the first clock rate or the second clock rate.
[0015]
In addition, the computer chipset of the present invention includes a logic circuit that references a first clock rate, a second clock rate, m phase signals, and either the first or second clock rate. It is coupled to accept an input signal and generates an output signal that references the other clock rate.
[0016]
The multiplexer means used in the computer chipset of the present invention has an output that is selectively multiplexed between the first clock rate and the second clock rate so that it can be used as the third clock signal.
[0017]
The computer motherboard further includes a first subsystem that references the first clock rate, a second subsystem that references the second clock rate, and a third subsystem that references the third clock rate. The third clock rate is either the first clock rate or the second clock rate.
Details of preferred embodiments
[0018]
FIG. 1 is a circuit block diagram showing an internal structure of a computer chip set according to the present invention (a circuit in a broken line indicated by reference numeral 100). The present invention is particularly used on computer motherboards with various clock rates, such as CLK-A 'and CLK-B'. As shown, the computer chip set 100 includes a first multiplexer 110, a second multiplexer 120, a third multiplexer 130, a phase signal generator 140, a first buffer 111, a second buffer 121, a third buffer 131, a main The system interface 112, the first signal conversion circuit 113, the second signal conversion circuit 114, the memory interface 122, the third signal conversion circuit 123, and the AGP / PCI interface 132 are configured. The computer chip set 100 is externally provided with a clock generator 150 capable of generating two clock signals CLK-A ′ and CLK-B ′ having different clock rates but a constant ratio for the computer chip set 100. Yes. For example, if CLK-A ′: CLK-B ′ is 3: 2 and CLK-A ′ is set to 100 MHz, CLK-B ′ is 66 KHz and CLK-A ′: CLK-B ′ is 4: 3 and CLK-A 'is set to 83 MHz, CLK-B' is 66 KHz. In the following embodiment of the present invention, it is assumed that CLK-A ′: CLK-B ′ is 3: 2. This means that three consecutive clock pulses in CLK-A ′ are equal to the length of time of two consecutive clock pulses in CLK-B ′.
[0019]
The computer chipset 100 includes three subsystems, a main system interface 112, a memory interface 122, and an AGP / PCI interface 132. The clock generator 150 sends CLK-A ′ to the main system interface 112 via the first multiplexer 110 and the first buffer 111 (output of the first buffer 111 indicated by the delay signal CLK-A of CLK-A ′). hand over. Further, the clock generator 150 passes CLK-A ′ and CLK-B ′ to the second multiplexer 120. The second multiplexer 120 selects and outputs one of these two inputs under the control of the SEL selection signal. The second multiplexer 120 passes the output to the memory interface 122 via the second buffer 121 (as the output of the second buffer 121 indicated by CLK-C). Further, the clock generator 150 passes CLK-B ′ to the AGP / PCI interface 132 via the third multiplexer 130 and the third buffer 131 (as the output of the third buffer 131 indicated by CLK-B). The buffers 111, 121, 131 can provide a larger current to each interface 112, 122, 132. The SEL selection signal is determined by the user. For example, it is determined by the jumper line means provided on the motherboard, or in the case of an IBM compatible machine, the software setting in the BIOS (Basic Input Output System). The first multiplexer 110 and the third multiplexer 130 are connected to CLK-A ′ and CLK-B ′ so that the output clock signals CLK-A and CLK-B are substantially synchronized with the output clock signal CLK-C from the second multiplexer 120. It functions as a delay means for giving a propagation delay to the clock signal.
[0020]
The first signal conversion circuit 113 is between the main system interface 112 and the memory interface 122, the second signal conversion circuit 114 is between the main system interface 112 and the AGP / PCI interface 132, and the third signal conversion circuit. Is provided between the memory interface 122 and the AGP / PCI interface 132. Further, the phase signal generation circuit 140 receives CLK-A ′ and CLK-B ′ as input signals from the clock generator 150 and generates several types of phase signals to be passed to all of the signal conversion circuits 113, 114, and 123. .
[0021]
The number of phase signals is determined to be equal to the larger value when the ratio of CLK-A ′ and CLK-B ′ is expressed by a relatively prime integer. For example, if CLK-A ′: CLK-B ′ = 3: 2, the number of phase signals is three represented by PH1, PH2, and PH3. Further, each phase signal is clocked according to the higher clock rate of CLK-A ′ and CLK-B ′. An example of waveforms and phase signal timings for CLK-A ′ and CLK-B ′ is shown in FIG.
[0022]
FIG. 2 shows the timing relationship between the two clock rates CLK-A ′ and CLK-B ′ and the phase signals PH1, PH2, and PH3 when CLK-A ′: CLK-B ′ = 3: 2. In FIG. 2, it is assumed that CLK-A ′ and CLK-B ′ are virtually synchronized, as the first pulses of CLK-A ′ and CLK-B ′ appear almost simultaneously. Under this assumption, the (3N + 1) th pulse of CLK-A ′ and the (2N + 1) th pulse of CLK-B ′ also appear almost simultaneously. Here, N is an integer of 1 or more. However, there may actually be a small deviation between CLK-A ′ and CLK-B ′. This deviation can be set within an allowable range by design. As shown in FIG. 2, the first phase signal PH1 is switched to the high voltage logic state during the first period of CLK-A ′ and the subsequent (3N + 1) period, and the others are the low voltage logic state. It remains. The second phase signal PH2 is switched to the high voltage logic state between the second period of CLK-A ′ and the subsequent (3N + 2) period, and the others remain at the low voltage logic state. The third phase signal PH3 is switched to the high voltage logic state between the third period of CLK-A ′ and the subsequent (3N + 3) period, and the others remain at the low voltage logic state.
[0023]
FIG. 3 is a circuit diagram showing input / output signals of the signal conversion circuits 113, 114, 123 used in the chip set of FIG. In FIG. 3, symbol SG-I represents an input signal referred to by either CLK-A or CLK-B. Symbol SG-O indicates an output signal from the signal conversion circuit referred to by either CLK-A or CLK-B. However, it is assumed that the input signal SG-I and the output signal SG-O refer to different clock signals. For example, if the input signal SG-I refers to CLK-A, the output signal SG-O must refer to CLK-B. Conversely, if the output signal SG-O refers to CLK-A, the input signal SG-I must refer to CLK-B. The waveform and timing of the output signal SG-O depend on the input signal SG-I, the clock signals CLK-A, CLK-B, and the phase signals PH1, PH2, PH3. This will be described in detail below.
[0024]
FIG. 4 is an internal circuit diagram of the embodiment of the signal conversion circuit of FIG. As shown in the figure, the signal conversion circuit includes a first AND gate 41, a first transparent latch 42, a second AND gate 43, a second transparent latch 44, and an OR gate 45. This signal conversion circuit uses only the clock signal CLK-A and the two phase signals PH1 and PH3, and CLK-B and PH2 are not used. Further, here, symbol A indicates an input signal referring to CLK-B, and symbol B indicates an output signal referring to CLK-A. First AND gate 41 has a first input connected to receive input A and a second input connected to receive PH3. The first transparent latch 42 has a D input coupled to the output of the first AND gate 41, a G input coupled to receive CLK-A, and a Q output coupled to the input of the OR gate 45. . Second AND gate 43 has a first input coupled to receive input A and a second input coupled to receive PH1. The second transparent latch 44 has a D input coupled to the output of the second AND gate 43, a G input coupled to receive CLK-A, and a Q output coupled to the other input of the OR gate 45. With an edge. The output of the first AND gate 41 enters the first transparent latch 42 when CLK-A is in the high voltage logic state. On the other hand, the output of the second AND gate 43 enters the second transparent latch 44. The OR gate 45 performs an OR logic operation on the output of the first transparent latch 42 and the output of the second transparent latch 44 to obtain an output B.
[0025]
5A and 5B are two examples of waveform diagrams of the input / output signals CLK-A, CLK-B, PH1, PH2, PH3, A, and B in the signal conversion circuit of FIG. In the examples of FIGS. 5A and 5B, it is assumed that CLK-A ′: CLK-B ′ = 3: 2. The signal conversion circuit of FIG. 4 has two cases to be discussed, as shown in FIGS. 5 (a) and 5 (b), respectively. Assume that CLK-A and CLK-B are virtually synchronized.
[0026]
In the case of FIG. 5A, if the input signal A is in a high voltage logic state during the first period of CLK-A, the output signal B is in a high voltage logic state according to the input signal A. As shown in FIG. 4, the input of the AND gate 43 is PH1 and A . Therefore, Input signal A is Maintained at the high voltage logic state for the first period of CLK-B. Also, the period of CLK-B is longer than the period of CLK-A . But, The output signal B is Maintained at a high voltage logic state during the first period of CLK-A; afterwards, During the second period of CLK-A, the low voltage logic state is restored.
[0027]
In the case of FIG. 5B, the input signal A is switched to the high voltage logic state during the second period of CLK-B. However, the output signal B is switched to the high voltage logic state after the third period of CLK-A appears, and is returned to the low voltage logic state immediately when the next period appears.
[0028]
The delay time that may exist between A and CLK-B and B and CLK-A in the above-described input / output signal sequence will be apparent to those skilled in the art. Although these delay times are ignored in the waveform diagram, in practice, the designer should correctly consider the delay times in the design so that the circuit does not stop due to malfunction.
[0029]
It can be seen from the waveform diagrams of FIGS. 5A and 5B that the designer is wasting clock cycles in the timing of input / output signals. In the case of FIG. 5A, since the output signal B appears all the time while the input signal A appears, the cycle is not wasted. However, in the case of FIG. 5B, the second cycle of CLK-B starts in the middle of the second cycle of CLK-A, and output B switches the high voltage logic state at the beginning of the third cycle of CLK-A. It has been. As a result, half of the period of CLK-A is wasted.
[0030]
FIG. 6 is a signal conversion circuit diagram devised to convert an input signal A referring to CLK-A to an output signal B referring to CLK-B. As shown in the figure, this signal conversion circuit includes a first AND gate 710, a second AND gate 720, a third AND gate 730, a first transparent latch 711, a first D-type flip-flop 721, a second D-type flip-flop 731, and a first OR gate. 722, a second transparent latch 723, and a second OR gate 740. In this signal conversion circuit, all inputs, that is, CLK-A, CLK-B, PH1, PH2, and PH3 are used. This signal conversion circuit is composed of three main processing sections associated with PH1, PH2 and PH3, respectively. In the portion corresponding to PH1, when CLK-A is in the high voltage logic state, the first transparent latch 711 latches the output of the first AND gate 710 as a result of the logical product of A and PH1. In the portion corresponding to PH2, the output of the second AND gate 720, which is the result of the logical product of A and PH2, is latched in the first D-type flip-flop 721 at the falling edge of CLK-A. Next, the first OR gate 722 calculates the logical sum of the output of the first D-type flip-flop 721 and the second AND gate 720. When CLK-B is switched to the high voltage logic state, the output of the first OR gate 722 is latched in the second transparent latch 723. In the portion corresponding to PH3, the third AND gate 730 output that is the logical product of A and PH3 is latched in the second D-type flip-flop 731 at the rising edge of CLK-B. Finally, the second OR gate 740 takes the logical sum of the output of the first transparent latch 711, the output of the second transparent latch 723, and the output of the second D-type flip-flop 731. The output of the second OR gate 740 is the output signal B.
[0031]
The timing of the input / output signals in FIG. 6 due to the clock rate ratio of CLK-A and CLK-B and the actual synchronism, as shown in FIGS. There is a case. In the case of FIG. 7A, the input signal A is switched to the high voltage logic state during the first period of CLK-A, and the output signal (through the first AND gate 710 and the first transparent latch 711 in FIG. 6). B is switched and remains in the high voltage logic state for the first period of CLK-B. In the case of FIG. 7B, the input signal A is switched to the high voltage logic state during the second period of CLK-A (the second AND gate 720, the first D type flip-flop 721, the first OR gate 722 in FIG. 6). And through the second transparent latch 723), the output signal B is switched and maintained at the high voltage logic state for the second period of CLK-B. In the case of FIG. 7C, the input signal A is switched to the high voltage logic state during the third period of CLK-A and is output (through the third AND gate 730 and the second D type flip-flop 731 in FIG. 6). Signal B is switched and maintained at the high voltage logic state for the third period of CLK-B.
[0032]
In FIG. 7A described above, since the output signal B is in a high voltage logic state in accordance with the input signal A, the clock cycle is not wasted. In the case of FIG. 7B, the second cycle of CLK-B starts in the middle of the second cycle of CLK-A, and the output signal B is switched at the beginning of the second cycle of CLK-B. -A cycle is wasted. In the case of FIG. 7C, since half of the second period of CLK-B has not ended at the start of the third period of CLK-A, the output signal B changes its state after the end of the second period of CLK-B. One cycle of CLK-A is wasted.
[0033]
In conclusion, in the five cases discussed in FIGS. 5 (a), 5 (b) and FIGS. 7 (a) -7 (c), the optimum condition is a case where no waiting time is required. Of these five cases, two do not include latency, the other two require half a cycle, and one requires a full cycle. To do. The present invention is clearly advantageous over the prior art that wasted at least one cycle.
[0034]
8 and 9 show another embodiment of the signal conversion circuit of the present invention. These signal conversion circuits incorporate a reset signal and associated circuitry so that all signal conversion circuits can be reset to their initial state when the computer system is activated. As shown in the figure, this signal conversion circuit includes delay means 813, 815, 823, 825, 923 and 925.
[0035]
As described above, the computer chip set of the present invention has various advantages described below over the prior art.
[0036]
First, the present invention takes advantage of apparent synchrony between various clock rates to reduce or eliminate latency in signal processing. The computer motherboard is used at various clock rates to realize efficient data processing.
[0037]
Second, the present invention provides a specific signal sequence design guideline so that a circuit can be designed more simply and with a small mounting area.
[0038]
Third, the present invention allows the DRAM and CPU on the computer motherboard to operate at two different clock rates. In addition, it allows the DRAM to run at a slower clock rate than the designer uses to run the CPU. Then, the EMI effect can be further reduced so as to satisfy the standard of the general EMI test.
[0039]
Although the present invention has been described using preferred embodiments, the scope of the present invention is not limited to the scope described in the above embodiments. Rather, it encompasses various variations and similar circuit protection. Accordingly, the claims should be construed most broadly to include all such modifications and similar circuits.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing the internal structure of a computer chipset of the present invention for a computer motherboard referring to various clock rates.
2 is a waveform diagram showing timing between various signals used in the computer chip set of FIG. 1; FIG.
3 is a circuit diagram showing input / output signals of a signal conversion circuit used in the computer chip set of FIG. 1;
4 is a circuit diagram of a preferred embodiment showing an internal structure of the signal conversion circuit of FIG. 3. FIG.
5A and 5B are waveform diagrams of various input / output signals processed by the signal conversion circuit of FIG.
FIG. 6 is a circuit diagram of a preferred embodiment of a signal conversion circuit.
7A to 7C are waveform diagrams of various input / output signals processed by the signal conversion circuit of FIG.
FIG. 8 is a circuit diagram of another preferred embodiment of a signal conversion circuit to which reset means is added.
FIG. 9 is a circuit diagram of still another preferred embodiment of a signal conversion circuit to which reset means is added.

Claims (5)

A computer chip sets for multiple computers motherboard clock signal that runs to see, including a second clock signal of the first clock signal and the second clock rate of the first clock rate,
A first interface that runs to see the first clock signal,
Wherein the first ratio of the clock rate and said second clock rate is m: n (m, n are integers, and, m> n) is, the rise of the first clock signal and the second clock signal are synchronized for each fixed period, and a second interface that runs the second clock signal to see,
A phase signal that sequentially switches to an enable state in each of the m periods of the first clock signal and generates a set of m phase signals that are maintained in the enable state for a period equal to one period of the first clock signal. A generation circuit;
The first provided between the interface and the second interface, wherein the phase signal generating circuit with m phases signals generated, the ratio between the second clock rate and said first clock rate the basis, the first signal conversion circuit signals exchanged converts the clock rate of reference between the first interface and the second interface
Computer chipset comprising. A third interface you to operate see third clock signal of the third clock rate,
And selecting one of the first clock signal and the second clock signal, according to 請 Motomeko 1 comprising the further a clock multiplexer for supplying said third interface as the third clock signal Computer chip set.   A ratio between the first clock rate and the third clock rate is set using m phase signals generated between the first interface and the third interface and generated by the phase signal generation circuit. A second signal conversion circuit for converting a clock rate referred to by a signal exchanged between the first interface and the third interface;
  Using the m phase signals generated between the second interface and the third interface and generated by the phase signal generation circuit, a ratio between the second clock rate and the third clock rate is set. And a third signal conversion circuit for converting a clock rate referred to by a signal exchanged between the second interface and the third interface,
The computer chip set according to claim 2, further comprising:   A computer chip set for a computer motherboard that operates with reference to a plurality of clock signals including a first clock signal having a first clock rate and a second clock signal having a second clock rate,
  A first interface operating with reference to the first clock signal;
  The ratio between the first clock rate and the second clock rate is m: n (m, n is an integer and m> n), and the rising edges of the first clock signal and the second clock signal are constant. A second interface that is synchronized with each other and operates with reference to the second clock signal;
  A phase signal generation circuit for generating a set of phase signals;
  Based on the ratio between the first clock rate and the second clock rate, using the phase signal generated between the first interface and the second interface and generated by the phase signal generation circuit, A first signal conversion circuit for converting a clock rate referred to by a signal exchanged between the first interface and the second interface;
  A memory interface operating with reference to a third clock signal at a third clock rate;
  The first clock signal and the second clock signal are selected and the third clock signal is selected. A clock multiplexer for supplying the memory interface as a clock signal;
A computer chipset comprising:   Based on the ratio between the first clock rate and the third clock rate, using the phase signal generated between the first interface and the memory interface and generated by the phase signal generation circuit, A second signal conversion circuit for converting a clock rate referred to by a signal exchanged between the first interface and the memory interface;
  Based on the ratio between the second clock rate and the third clock rate, using the phase signal generated between the second interface and the memory interface and generated by the phase signal generation circuit, A third signal conversion circuit for converting a clock rate referred to by a signal exchanged between the second interface and the memory interface;
The computer chip set according to claim 4, further comprising:

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