JP3854087B2 - Power supply potential detection circuit - Google Patents

Description

ここで、Ｖthp81（＜０）はＰＭＯＳ８１（ノーマリオフ型）のしきい値電圧である。
【０００５】
電源電位ＶＤＤがゼロから式（１）で示される範囲の値まで上昇すれば、ＰＭＯＳ８１のゲート・ソース間の電位差がしきい値以上になるため、ＰＭＯＳ８１はオフ状態からオン状態に変化し、ＰＭＯＳ８１のドレイン電位ＶＤ８が上昇する。これを２段のインバータ回路ＩＮＶ８１を介して出力信号ＰＷＯＮとして出力し、出力信号ＰＷＯＮを後段の回路で受けることにより電源電位ＶＤＤの上昇を検知する。
【０００６】
次に、電源電位ＶＤＤが式（２）で示される範囲の値まで下降すれば、ＰＭＯＳ８１のゲート・ソース間の電位差がしきい値以下になるため、ＰＭＯＳ８１がオン状態からオフ状態に変化し、ＰＭＯＳ８１のドレイン電位ＶＤ８が下降し、これを２段のインバータ回路ＩＮＶ８１を介して出力信号ＰＷＯＮとして出力し、出力信号ＰＷＯＮを後段の回路で受けることにより電源電位ＶＤＤの下降を検知する。
【０００７】
ここで、ＰＭＯＳ８１の電流制限抵抗Ｒ８１の抵抗をＲ、寄生容量をＣとし、電流制限抵抗Ｒ８１のＲ＊Ｃ時定数をτ_RC81とし、図９及び図１０を用いて図８に示す各電位ノードの電位波形について説明する。はじめに、図９を用いて、電源電位ＶＤＤが電流制限抵抗の時定数τ_RC81に比べて十分遅く変化する場合について説明する。
【０００８】
図９の実線ＶＤＤに示すように、電源電位ＶＤＤは、ゼロ電位から所定の電位までリニアに上昇し、一定時間所定の電位を維持した後再度ゼロ電位まで下降する台形状の時間変化を示すものとする。このとき図８の電源電位分割回路Ｒ８３、Ｒ８４の出力電位ＶＧ８は、図９の実線ＶＧ８に示すように、電源電位ＶＤＤを抵抗分割して得られる台形状の時間変化を示す。
【０００９】
当初ＶＤＤ及びＶＧ８は共にゼロ電位であり、図８のＰＭＯＳ８１はノーマリオフ型であるからＰＭＯＳ８１はオフ状態である。ＰＭＯＳ８１のドレイン電位ＶＤ８は電流制限抵抗Ｒ８１を介して接地されるので、ＰＭＯＳ８１のドレイン電位ＶＤ８もまたゼロ電位となる。
【００１０】
時刻ｔ_{1 ａ}に達すれば、ＰＭＯＳ８１のゲート・ソース間電圧ＶＤＤ−ＶＧ８がＰＭＯＳ８１のしきい値電圧の絶対値｜Ｖthp81｜以上になるため、ＰＭＯＳ８１がオン状態となり、ＰＭＯＳ８１のドレイン電位ＶＤ８はゼロ電位から高速に時刻ｔ_{1 ａ}における実線ＶＤＤの電位まで上昇する。このＶＤ８の時間変化は、図８のＩＮＶ８１を介して電源電位検知回路の出力信号ＰＷＯＮとなり、図９の破線ＰＷＯＮに示すようにＶＤ８の時間変化に沿って出力される。
【００１１】
次に、時刻ｔ_{2 ａ}になればＰＭＯＳ８１のゲート・ソース間電圧ＶＤＤ−ＶＧ８がＰＭＯＳ８１のしきい値電圧の絶対値｜Ｖthp81｜以下になるため、ＰＭＯＳ８１がオフ状態となり、ＰＭＯＳ８１のドレイン電位ＶＤ８は時刻ｔ_{2 ａ}における実線ＶＤＤの電位から電流制限抵抗Ｒ８１の時定数τ_RC81でゼロ電位まで下降する。
【００１２】
このとき、電源電位ＶＤＤの下降速度が十分に遅ければ、時定数τ_RC81は無視できるので、ＰＭＯＳ８１のドレイン電位ＶＤ８は、時刻ｔ_{2 ａ}における実線ＶＤＤの電位からゼロまでほぼ垂直に下降する。このＶＤ８の時間変化は、図８のＩＮＶ８１を介して電源電位検知回路の出力信号ＰＷＯＮとなり、図９の破線に示すようにＶＤ８の時間変化に沿って出力される。
【００１３】
このようにして、図９に示す電源電位ＶＤＤの時間変化を所定のタイミングで検知し、急峻な上昇／下降形状を備えた電源電位検出回路の出力信号ＰＷＯＮを得ることができる。ＰＷＯＮの検知時刻やパルス幅は、電源電位分割回路Ｒ８３、Ｒ８４の電位分割比及びＰＭＯＳ８１のしきい値電圧Ｖthp81の値で定められる。
【００１４】
次に、電源電位ＶＤＤの下降時間より電流制限抵抗Ｒ８１の時定数τ_RC81が長い場合に生じる問題点について説明する。電流制限抵抗Ｒ８１の時定数τ_RC81が電源電位ＶＤＤの下降時間に比べて長ければ、時刻ｔ_{2 ａ}においてＰＭＯＳ８１がオフ状態となり、ドレイン電位ＶＤ８が、電流制限抵抗Ｒ８１を介して時定数τ_RC81で接地側に放電し始める際、それより早く電源電位ＶＤＤがゼロ電位に達するので、結果的に電源電位ＶＤＤの変化に対して電位ＶＤ８の接地側への放電が追随できなくなり、時刻ｔ_{2 ａ}におけるＶＤ８の電位降下の開始時点が検知されないことになる。
【００１５】
図１０を用いて、このときの各電位ノード波形を詳細に説明する。図１０の電位波形は、高速なＶＤＤの時間変化を見易くするため図９に比べて時間軸を拡大して示している。時刻ｔ₁においてＰＭＯＳ８１がオン状態になれば、ＰＭＯＳ８１の大きなオン電流により、電流制限抵抗Ｒ８１の容量成分が高速に充電される。従って、ドレイン電位ＶＤ８が高速に上昇し、図１０の破線に示すように出力信号ＰＷＯＮは電源電位ＶＤＤの上昇を検知することができる。
【００１６】
しかし、時刻ｔ₂においてＰＭＯＳ８１がオフ状態になれば、図１０の時刻ｔ₂以降の実線ＶＤ８に示すように、ＰＭＯＳ８１のドレイン電位ＶＤ８は、時定数τ_RC81で指数関数的に減衰し、このドレイン電位ＶＤ８の緩やかな変化がインバータ列ＩＮＶ８１の初段を反転させるしきい値に達しなければ、次段のインバータから出力される出力信号ＰＷＯＮは、次段インバータの出力高レベル（通常、ＶＤＤに等しい）のままとなる。
【００１７】
従って、図１０の破線に示す出力信号ＰＷＯＮは電源電位ＶＤＤに沿って時間変化する。すなわち、出力信号ＰＷＯＮは時刻ｔ₂におけるＶＤＤの電位降下を検知することなくＶＤＤの時間変化に沿って変化することになる。
【００１８】
このように、電源電位ＶＤＤが高速に下降すれば、ＰＭＯＳ８１のゲート・ソース間の電位差がＰＭＯＳ８１のしきい値以下になりオフ状態になっても、ドレイン電位ＶＤ８は電流制限抵抗Ｒ８１の時定数τ_RC81のため下降し終わることができず、ゆるやかな下降状態が後段のＩＮＶ８１に伝達されないため、電源電位ＶＤＤの下降の検知ができなくなるという問題があった。
【００１９】
【発明が解決しようとする課題】
上記したように、従来の電源電位検知回路は高速な電源電位の上昇を検知することは可能であるが、高速な電源電位の下降を検知することができないという問題があった。
【００２０】
本発明は上記の問題点を解決すべくなされたもので、高速な電源電位の上昇と同様に、高速な電源電位の下降を検知することができる電源電位検知回路を提供することを目的とする。
【００２１】
【課題を解決するための手段】
本発明の電源電位検知回路は、高速な電源電位の下降を検知するため、遅延回路を介して第１のＰＭＯＳトランジスタのソース電極に電源電位を付与し、ゲート電極に第１の電源電位分割回路の出力を付与することにより、電源電位の下降の際に第１のＰＭＯＳトランジスタがオンするように構成し、第１のＰＭＯＳトランジスタのオン電流を用いて高速な電源電位の下降を検知する出力信号を発生させることを特徴とする。
【００２２】
一方、高速な電源電位の上昇は、第２のＰＭＯＳトランジスタのソース電極に直接電源電位を付与し、ゲート電極に第２の電源電位分割回路の出力を付与することにより、電源電位の上昇の際に第２のＰＭＯＳトランジスタがオンするようにし、第２のＰＭＯＳトランジスタの大きなオン電流を用いて高速な電源電位の上昇を検知する出力信号を発生させる。
【００２３】
このようにして検知された出力信号を、インバータ列と論理回路を用いて合成すれば、高速な電源電位の上昇と下降を共に検知する電源電位検知回路を提供することができる。
【００２４】
なお、以上の説明においてＰＭＯＳ及びＮＭＯＳは例示であり、本発明は必ずしもＭＯＳトランジスタに限定されるものではない。本発明は、一般にＭＩＳトランジスタ(Metal-Insulator-Semiconductor transistor)に対して同様に適用することができるので、特に請求項及び以下この項において、本発明の説明に例示したＰＭＯＳをＰ型ＭＩＳトランジスタ、ＮＭＯＳをＮ型ＭＩＳトランジスタと呼ぶ。
【００２５】
具体的には本発明の電源電位検知回路は、少なくとも抵抗／容量遅延回路を介して電源電位が付与されたソース電極、及び電流制御抵抗を介して接地されたドレイン電極、及び電源電位分割回路の出力電位を入力するゲート電極を備えたＰ型ＭＩＳトランジスタを有することを特徴とする。
【００２６】
また、本発明の電源電位検知回路は、第１のＰ型ＭＩＳトランジスタと、第２のＰ型ＭＩＳトランジスタと、第１のＰ型ＭＩＳトランジスタのドレイン電位が入力される第１のインバータ列と、第２のＰ型ＭＩＳトランジスタのドレイン電位が入力される第２のインバータ列と、第１及び第２のインバータ列の出力を受けて、第２のＰ型ＭＩＳトランジスタのドレイン電位がハイレベルであって、第１のＰ型ＭＩＳトランジスタのドレイン電位がロウレベルのときに、第１レベルの所定の論理信号を出力し、第２のＰ型ＭＩＳトランジスタのドレイン電位がロウレベルであって、第１のＰ型ＭＩＳトランジスタのドレイン電位がハイレベルのときに、第１レベルを反転した第２レベルの所定の論理信号を出力する論理回路とを有することを特徴とする。
【００２７】
また、本発明の電源電位検知回路は、抵抗／容量遅延回路を介して電源電位が付与されたソース電極、及び第１の電流制御抵抗を介して接地されたドレイン電極、及び第１の電源電位分割回路の出力電位を入力するゲート電極を備えた第１のＰ型ＭＩＳトランジスタと、電源電位が付与されたソース電極、及び第２の電流制御抵抗を介して接地されたドレイン電極、及び第２の電源電位分割回路の出力電位を入力するゲート電極を備えた第２のＰ型ＭＩＳトランジスタと、第１のＰ型ＭＩＳトランジスタのドレイン電位を入力する偶数段の第１のインバータ列と、第２のＰ型ＭＩＳトランジスタのドレイン電位を入力する奇数段の第２のインバータ列と、第１及び第２のインバータ列の出力を受けるＮＯＲゲートとを有することを特徴とする。
【００２８】
好ましくは、前記抵抗／容量遅延回路は、単数又は複数の抵抗と容量との組み合わせ回路を有し、前記電源電位分割回路は、複数の抵抗が直列に接続された抵抗回路、又は複数の容量が直列に接続された容量回路、又は複数の抵抗と容量との組み合わせ回路を有し、前記抵抗／容量遅延回路の時定数は、前記電源電位分割回路、及び前記電流制御抵抗よりも大であることを特徴とする。
【００２９】
また、好ましくは前記抵抗／容量遅延回路と前記Ｐ型ＭＩＳトランジスタとの間に、ダイオード、又はダイオード接続されたＭＩＳトランジスタが挿入されることを特徴とする。
【００３０】
また、好ましくは前記抵抗／容量遅延回路は、直列に接続された複数の抵抗と、前記複数の抵抗の一方の終端部と接地との間、並びに前記複数の抵抗の各接続ノードと接地との間にそれぞれ接続された容量とを具備し、複数の抵抗の一方の終端部には直接電源電位が付与され、各接続ノードにはダイオード、又はダイオード接続されたＭＩＳトランジスタを介して電源電位が付与され、かつ複数の抵抗の他方の終端部には、Ｐ型ＭＩＳトランジスタのソース電極が接続されることを特徴とする。
【００３１】
また、本発明の電源電位検知回路は、電源電位が付与されたソース電極、及び直列接続された第１、第２の抵抗を有する電流制御抵抗を介して接地されたドレイン電極、及び直列接続された第３、第４の抵抗、又は直列接続された第１、第２の容量を有する電源電位分割回路の出力電位が入力されたゲート電極を備えるＰ型ＭＩＳトランジスタと、Ｐ型ＭＩＳトランジスタのドレイン電極の電位が入力された第１のインバータと、Ｐ型ＭＩＳトランジスタのドレイン電極に直接、又は前記第１の抵抗を介して接続されたドレイン電極、及び接地されたソース電極、及び前記第１のインバータの出力電位を入力するゲート電極を備えるＮ型ＭＩＳトランジスタとを具備し、第１のインバータの出力電位が第２のインバータを介して出力されることを特徴とする。
【００３２】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。
＜第１実施形態＞
図１は、本発明の第１の実施の形態に係る電源電位検知回路の構成を示す図である。
【００３３】
図１において、ＰＭＯＳ１１のソース電極は、抵抗と容量からなる遅延回路ＲＣ１を介して電源電位ＶＤＤに接続され、ドレイン電極はＰＭＯＳ１１の電流を絞る電流制御抵抗Ｒ１１を介して接地される。また、ＰＭＯＳ１１のゲート電極には、直列に接続された抵抗Ｒ１３、Ｒ１４からなる電源電位分割回路を用いて、電源電位ＶＤＤと接地の間を抵抗分割することにより得られたゲート電位ＶＧ１が入力され、ドレイン電位ＶＤ１は２段のインバータからなるインバータ列ＩＮＶ１１を介して２入力ＮＯＲゲートＮＯＲ１の一方の入力端子に入力される。
【００３４】
また、ＰＭＯＳ１２のソース電極は直接電源電位ＶＤＤに接続され、ドレイン電極はＰＭＯＳ１２の電流を絞る電流制御抵抗Ｒ１２を介して接地される。また、ＰＭＯＳ１２のゲート電極には電源電位分割回路Ｒ１５、Ｒ１６を用いて電源電位ＶＤＤと接地の間を抵抗分割することにより得られたゲート電位ＶＧ２が入力され、ドレイン電位ＶＤ２は１段のインバータＩＮＶ１２を介して、２入力ＮＯＲゲートＮＯＲ１の他方の入力端子に入力され、ＮＯＲ１の出力端子から電源電位検知回路の出力信号ＰＷＯＮが出力される。ここで、ＰＭＯＳ１１、ＰＭＯＳ１２は、それぞれしきい値電圧Ｖthp11、Ｖthp12（いづれも負の値）のノーマリオフ型トランジスタである。
【００３５】
次に図２に示す各電位ノードの電位波形を用いて、第１の実施の形態に係る電源電位検知回路の動作について詳細に説明する。
電源電位ＶＤＤの上昇過程で、電源電位ＶＤＤと電源電位分割回路Ｒ１５、Ｒ１６から出力されるゲート電位ＶＧ２との差が、時刻ｔ₁においてＰＭＯＳ１２のしきい値電圧｜Ｖthp12｜を越えれば、当初オフ状態であったＰＭＯＳ１２がオン状態に変化し、ドレイン電位ＶＤ２が、ゼロから実線で示すようにＶＤＤの電位まで高速に上昇する。
【００３６】
ＰＭＯＳ１２のドレイン電位ＶＤ２は、インバータＩＮＶ１２及びＮＯＲゲートＮＯＲ１を介して、図２の破線で示すように電源電位検知回路の出力信号ＰＷＯＮとして出力される。ＰＭＯＳ１２がオン状態に変化した後の出力信号ＰＷＯＮの電位は、ＮＯＲ１の高レベルが電源電位ＶＤＤに等しければＶＤＤに沿って上昇する。このようにして、２入力ＮＯＲゲートＮＯＲ１の出力端子から電源電位検知回路の出力信号ＰＷＯＮの高速な立ち上がりが出力される。
【００３７】
同様に電源電位ＶＤＤの上昇過程で、当初オフ状態のＰＭＯＳ１１のゲート電極には、電源電位分割回路Ｒ１３、Ｒ１４から出力されるゲート電位ＶＧ１が印加されるが、ＰＭＯＳ１１のソース電極は、抵抗と容量からなる遅延回路ＲＣ１を介して電源電位ＶＤＤに接続されるため、ＰＭＯＳ１１のソース電位ＶＤＤ１は、電源電位ＶＤＤの上昇から遅延回路ＲＣ１の時定数τ_RC1だけ遅れて上昇し、電源電位ＶＤＤの平坦部後方（図２の時間幅ｔｗの後方）において電源電位ＶＤＤの最大値に達する（ＲＣ１の容量の充電が完了する）ようになる。
【００３８】
ここで、第１の実施の形態においては、この平坦部における電源電位ＶＤＤの最大値とＰＭＯＳ１１のゲート電位ＶＧ１との電位差が、ＰＭＯＳ１１のしきい値電圧｜Ｖthp11｜を越えないように設定される。このため、電源電位ＶＤＤが最大になる時間幅ｔｗを越えても、なおＰＭＯＳ１１のオフ状態が維持される。
【００３９】
次に電源電位が急速に下降する場合を考える。先の充電過程で遅延回路ＲＣ１の容量に蓄積された電荷が下降していくのに、ＲＣ１の抵抗が持つ時定数τ_RC1を要するので、ＰＭＯＳ１１のソース電位ＶＤＤ１は、図２に示すように電源電位ＶＤＤの直線的な下降に遅れてゆるやかに下降する。
【００４０】
従って、ＰＭＯＳ１１のソース電位ＶＤＤ１と、電源電位分割回路Ｒ１３、Ｒ１４から出力されるゲート電位ＶＧ１との電位差が、ＰＭＯＳ１１のしきい値電圧｜Ｖthp11｜を越える時点ｔ2でＰＭＯＳ１１はオン状態となり、ドレイン電位ＶＤ１が高速に上昇する。このようにして、２個のインバータ列ＩＮＶ１１を介して、２入力ＮＯＲゲートＮＯＲ１の出力端子から電源電位検知回路の出力信号ＰＷＯＮの高速な立ち下りが出力される。
【００４１】
第１の実施の形態に係る電源電位検知回路では、ＰＭＯＳ１２がオンすることにより、ドレイン電位ＶＤ２の高速な上昇を介して電源電位ＶＤＤの上昇が検知され、ＰＭＯＳ１１がオンすることによりドレイン電位ＶＤ１の高速な上昇を介して電源電位ＶＤＤの下降が検知される。
【００４２】
すなわち、ドレイン電位ＶＤ２、ＶＤ１の高速な上昇は、それぞれ奇数個のインバータ列からなるＩＮＶ１２、偶数個のインバータ列からなるＩＮＶ１１を介して、２入力のＮＯＲゲートＮＯＲ１にそれぞれ入力し、ＮＯＲ１の出力として電源電位検知回路の出力信号ＰＷＯＮの高速な立ち上がりと立ち下りが出力される。このようにして、従来困難であった電源電位ＶＤＤの下降を高速に検知することが可能になる。
【００４３】
なお、図１ではＩＮＶ１１及びＩＮＶ１２がそれぞれ１個及び２個のインバータからなる場合が示されている。また、第１の実施の形態では、電流制限抵抗Ｒ１１の抵抗値と容量成分によるＲ＊Ｃ時定数τ_RC11及び電源電位分割回路Ｒ１３、Ｒ１４のＲ＊Ｃ時定数τ_RC13及びτ_RC14は、いずれも抵抗／容量遅延回路の時定数τ_RC1に比べて小さく、電源電位検知回路の動作に大きな影響を及ぼさないものとしている。
【００４４】
また、第１の実施の形態において、電源電位分割回路は複数の抵抗（図１では２個の抵抗）を直列に接続した場合につて説明したが、電源電位分割回路は複数の容量を直列に接続しても同様に動作することができる。一般に、電源電位分割回路は複数の抵抗と容量とを結合して形成することが可能である。
【００４５】
＜第２実施形態＞
次に、図３及び図４を用いて第２の実施の形態に係る電源電位検知回路の構成と動作について説明する。図３及び図４に示す電源電位検知回路の構成は、第１の実施の形態の変形例であって、抵抗／容量遅延回路とＰＭＯＳのソース電極との間にダイオード接続されたＭＯＳトランジスタ、又はダイオードが接続される他は第１の実施の形態と同様であるため、対応する回路要素に対応する符号を付して説明を省略し相違点についてのみ説明する。
【００４６】
図３に示す電源電位検知回路は、抵抗／容量遅延回路ＲＣ３とＰＭＯＳ３１のソース電極との間に、ゲート・ドレイン電極間が互いに接続されたダイオード接続のノーマリ・オフ型ＰＭＯＳ３３が、ゲート・ドレイン共通電極をＰＭＯＳ３１の側に、ソース電極をＲＣ３の側にして挿入されることに特徴がある。このように、ダイオード接続されたＰＭＯＳ３３は、ソース電極をアノード側、ゲート・ドレイン共通電極をカソード側とするダイオード特性を示すので、ダイオード特性の順方向電流に対して電位のレベルシフト作用を有する。
【００４７】
先に述べたように、図３に示す電源電位検知回路は、ＰＭＯＳ３２がオンすることにより出力信号ＰＷＯＮが立ち上がり、ＰＭＯＳ３１がオンすることにより出力信号ＰＷＯＮが立ち下がる。従って、ダイオード接続されたＰＭＯＳ３３の電位のレベルシフト作用がＰＭＯＳ３１のソース側に加わることにより、ＰＭＯＳ３２がオンする（ＰＷＯＮが立ち上がる）ＶＤＤの電位とＰＭＯＳ３１がオンする（ＰＷＯＮが立ち下がる）ＶＤＤの電位とを第１の実施の形態と異ならせることができる。
【００４８】
このようにして、電源電位検知回路における出力信号ＰＷＯＮの形状や出力タイミング設定の自由度を高めることが可能になる。なお、第２の実施の形態において、ＰＭＯＳをダイオード接続する場合について説明したが、ＮＭＯＳのゲート・ドレイン共通電極をアノード電極としてダイオード接続し、ゲート・ドレイン共通電極をＲＣ４の側に、ＮＭＯＳのソース電極をＰＭＯＳ４１のソース側にしてＮＭＯＳを挿入することにより同様な効果を得ることができる。
【００４９】
図４に示す電源電位検知回路では、抵抗／容量遅延回路ＲＣ４とＰＭＯＳ４１のソース電極との間に、カソード電極をＰＭＯＳ４１の側に、アノード電極をＲＣ４の側にしてダイオードＤｉ４１が挿入される。ダイオード接続されたＭＯＳトランジスタの代わりにダイオード自身を用いれば、同様な効果が得られることはいうまでもない。
【００５０】
＜第３実施形態＞
次に、図５を用いて第３の実施の形態について説明する。第３の実施の形態では、第１、第２の実施の形態に係る抵抗／容量遅延回路の変形例について説明する。
【００５１】
図５（ａ）は、抵抗／容量遅延回路ＲＣ５ａを構成する抵抗と容量との各接続ノードに、それぞれダイオード接続されたＮＭＯＳを介して電源電位ＶＤＤが付与されることに特徴がある。図５（ｂ）では同様に抵抗／容量遅延回路ＲＣ５ｂを構成する抵抗と容量との各接続ノードに、それぞれダイオード接続されたＰＭＯＳを介して電源電位ＶＤＤが付与される。また、図５（ｃ）では同様に抵抗／容量遅延回路ＲＣ５ｃを構成する抵抗と容量との各接続ノードに、それぞれダイオードを介して電源電位ＶＤＤが付与される。なお、図５の回路１は、図１に示す回路から抵抗／容量遅延回路ＲＣ１を除去した回路である。
【００５２】
このようにすれば、電源電位ＶＤＤの上昇の際、ダイオード接続のＮＭＯＳ、ダイオード接続のＰＭＯＳ、又はダイオードＤｉの順方向電流により抵抗／容量遅延回路を構成する各容量が高速にＶＤＤ−Ｖth、又はＶＤＤ−Ｖbi（Ｖbiはダイオードのビルトイン・ポテンシャル）まで充電されるので、これらの各容量と抵抗との接続ノード、及び図５（ａ）、図５（ｂ）、図５（ｃ）において、回路１に含まれるＰＭＯＳ（図１のＰＭＯＳ１１）のソース電位ＶＤＤ５ａ、ＶＤＤ５ｂ、ＶＤＤ５ｃは電源電位ＶＤＤの上昇に沿って最大電位となる時間幅ｔｗ（図２参照）の領域まで上昇する。
【００５３】
ここで、ダイオード接続のＮＭＯＳ、ＰＭＯＳを用いた時の電源電位ＶＤＤからの差分Ｖth、ダイオードＤｉを用いたときの電源電位ＶＤＤからの差分Ｖbiは、図５（ａ）、図５（ｂ）、図５（ｃ）に示すように、遅延回路ＲＣ５ａ、ＲＣ５ｂ、ＲＣ５ｃの一方の終端部を直接ＶＤＤに接続することで補充され、ほぼＶＤＤの上昇に沿って最大電位に到達することが可能になる。
【００５４】
従って、先に図１、図２を用いて説明した、電源電位ＶＤＤの上昇過程における、抵抗／容量遅延回路ＲＣ１の時定数τ_RC1によるＰＭＯＳ１１のソース電位ＶＤＤ１での電位上昇の遅れが解消し、抵抗／容量遅延回路ＲＣ１の容量の充電が完了するまでの待ち時間として必要な時間幅ｔｗを、実質的にゼロにすることができる。
【００５５】
次に、電源電位ＶＤＤの下降過程では、抵抗／容量遅延回路を構成する各容量の蓄積電荷がダイオード接続のＮＭＯＳ、ＰＭＯＳ、又はダイオードＤｉを逆バイアスするので、これらの素子は電気的に抵抗／容量遅延回路から切り離され、第１の実施の形態と同様に、電源電位ＶＤＤの下降過程でＰＭＯＳ１１をオンさせることで電源電位ＶＤＤの下降を検知することができる。
【００５６】
このように第３の実施の形態によれば、第１の実施の形態に比べて電源電位ＶＤＤの高速な下降を検出するのに必要なＶＤＤの最大値を維持する時間幅ｔｗを短縮することができるので特に高速な電源電位検知回路において、出力信号ＰＷＯＮの形状や出力タイミング設定の自由度をさらに高めることが可能になる。
【００５７】
＜第４実施形態＞
次に、図６、図７を用いて、第４の実施の形態について説明する。第４の実施の形態では、電源電位ＶＤＤの上昇と下降を検知するＰＭＯＳの他に、特に電源電位ＶＤＤの高速な下降の検知能力を高めるためのＮＭＯＳからなるフィードバック回路を形成することに特徴がある。
【００５８】
図６に示す電源電位検知回路は、電源電位ＶＤＤが直接付与されるソース電極、及び直列接続された抵抗Ｒ６１、Ｒ６２からなる電流制御抵抗を介して接地されたドレイン電極、及び直列接続された抵抗Ｒ６３、Ｒ６４（又は直列接続された第１、第２の容量）からなる電源電位分割回路の出力がゲート電位ＶＧ６として入力されるゲート電極を具備するＰＭＯＳ６１を備えている。
【００５９】
ＰＭＯＳ６１のドレイン電位ＶＤ６はインバータＩＮＶ６１に入力され、インバータＩＮＶ６１の出力はゲート電位ＶＧＮ６１としてＮＭＯＳ６１のゲートに入力される。ＮＭＯＳ６１のドレインは直接ＰＭＯＳ６１のドレインに、又は抵抗Ｒ６１を介してＰＭＯＳ６１のドレインにフィードバックされる。
【００６０】
また、ＮＭＯＳ６１のソースは接地され、インバータＩＮＶ６１の出力電位は、インバータＩＮＶ６２を介して出力信号ＰＷＯＮとして出力される。ここで、ＰＭＯＳ６１のしきい値電圧をＶthp61、インバータＩＮＶ６１の回路のしきい値電圧をＶthinv61、ＮＭＯＳ６１のしきい値電圧をＶthn61とする。
【００６１】
次に、図７を用いて、第４の実施の形態に係る電源電位検知回路の動作を説明する。時刻ｔ₁において電源電位ＶＤＤが所定の値に上昇し、電源電位分圧回路Ｒ６３、Ｒ６４から出力されるＰＭＯＳ６１のゲート電位ＶＧ６との電位差がＰＭＯＳ６１のしきい値電圧｜Ｖthp61｜を越えれば、ＰＭＯＳ６１がオン状態となり、出力信号ＰＷＯＮを高レベルにすることで電源電位ＶＤＤの上昇を検知する。
【００６２】
次に、時刻ｔ₂において電源電位ＶＤＤが所定の値まで下降し、ＰＭＯＳ６１のゲート電位ＶＧ６との電位差がＰＭＯＳ６１のしきい値電圧｜Ｖthp61｜以下となれば、ＰＭＯＳ６１がオフ状態となりドレイン電位ＶＤ６が下降し始める。図７に示すように、ドレイン電位ＶＤ６がインバータＩＮＶ６１の回路のしきい値電圧Ｖthinv61より低くなれば、ＩＮＶ６１の出力電位ＶＧＮ６１が高レベルになり始める。
【００６３】
ＮＭＯＳ６１のゲートに入力されるＶＧＮ６１がＮＭＯＳ６１のしきい値電圧Ｖthn61を越えれば、ＮＭＯＳ６１がオン状態となり、Ｒ６１とＲ６２との接続点が接地されるので、ＰＭＯＳ６１のドレイン電位ＶＤ６は高速に引き下げられ、破線で示す出力信号ＰＷＯＮを低レベルにすることで、電源電位ＶＤＤの高速な下降を検知することが可能になる。
【００６４】
このようにすれば、第１乃至第３の実施の形態に係る電源電位検知回路に比べて、抵抗／容量遅延回路を必要とせず、また、その他の回路構成も簡略化されるため抵抗列の数が少なくなり、電源電位検知回路の低消費電力化とチップ面積の縮小を図ることができる。
【００６５】
なお本発明は上記の実施の形態に限定されることはない。例えば第２、第３の実施の形態を組み合わせれば、より設計の自由度が高い電源電位検知回路を構成することができる。また、第３の実施の形態において、抵抗／容量遅延回路をＲ＊Ｃラダーからなる等価回路で表示し、電源電位ＶＤＤが直接付与される終端部を除く各等価容量に、ダイオード接続したＭＯＳトランジスタやダイオードを接続するとして説明した。しかし現実の回路では、図５における回路１との接続点の電位ＶＤＤ５ａ、ＶＤＤ５ｂ、ＶＤＤ５ｃは、容量成分を含めてその値が定まるので、回路１との接続点にもダイオード接続したＭＯＳトランジスタやダイオードを接続することが望ましい。その他本発明の要旨を逸脱しない範囲で種々変形して実施することができる。
【００６６】
【発明の効果】
上述したように本発明の電源電位検知回路によれば、高速な電源電位の上昇と同様に高速な電源電位の下降を検知する電源電位検知回路を提供することが可能になる。
【図面の簡単な説明】
【図１】第１の実施の形態に係る電源電位検知回路の構成を示す図。
【図２】第１の実施の形態に係る電源電位検知回路の動作を示す電位波形図。
【図３】第２の実施の形態に係る電源電位検知回路の構成を示す図。
【図４】第２の実施の形態に係る電源電位検知回路の他の構成を示す図。
【図５】第３の実施の形態に係る抵抗／容量遅延回路の構成を示す図であって、
（ａ）は、ダイオード接続されたＮＭＯＳを用いた回路構成を示す図。
（ｂ）は、ダイオード接続されたＰＭＯＳを用いた回路構成を示す図。
（ｃ）は、ダイオードを用いた回路構成を示す図。
【図６】第４の実施の形態に係る電源電位検知回路の構成を示す図。
【図７】第４の実施の形態に係る電源電位検知回路の動作を示す電位波形図。
【図８】従来の電源電位検知回路の構成を示す図。
【図９】従来の電源電位検知回路における電源電位の低速変化での動作を示す電位波形図。
【図１０】従来の電源電位検知回路における電源電位の高速変化での動作を示す電位波形図。
【符号の説明】
１…抵抗／容量遅延回路を除く第１の実施の形態に係る回路
ＲＣ１、ＲＣ３、ＲＣ４、ＲＣ５ａ、ＲＣ５ｂ、ＲＣ５ｃ…抵抗／容量遅延回路
ＩＮＶ１１、ＩＮＶ３１、ＩＮＶ４１…偶数段インバータ
ＩＮＶ１２、ＩＮＶ３２、ＩＮＶ４２…奇数段インバータ
ＩＮＶ６１、ＩＮＶ６２…インバータ
Ｖthp11、Ｖthp12、Ｖthp61…ＰＭＯＳのしきい値電圧
Ｖthn61…ＮＭＯＳのしきい値電圧
Ｖthinv61…ＩＮＶ６１の回路しきい値電圧
ＶＤＤ…電源電位
ＰＷＯＮ…電源電位検知回路の出力信号[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a potential detection circuit, and more particularly to a power supply potential detection circuit such as SRAM, DRAM, EEPROM, and FeRAM (Ferro-electric Random Access Memory) that detects a rise / fall of a power supply potential at high speed.
[0002]
[Prior art]
In a conventional power supply potential detection circuit, a power supply potential is applied to a source electrode of a P-type MOS transistor, a drain electrode is grounded through a current control resistor, and an output potential of a power supply potential dividing circuit that resistance-divides the power supply potential is gated. Input to the electrode, when the power supply potential becomes higher than a desired value, the P-type MOS transistor is turned on to detect the rise of the power supply potential, and when the power supply potential becomes lower than the desired value, the P-type MOS transistor is turned off. Is known which detects a drop in power supply potential.
[0003]
Next, the configuration and operation of a conventional power supply potential detection circuit will be specifically described with reference to FIGS. Hereinafter, the P-type MOS transistor is abbreviated as PMOS, and the N-type MOS transistor is abbreviated as NMOS.
In FIG. 8, the source electrode of the PMOS 81 is directly connected to the power supply potential VDD, and the drain electrode is grounded via a current control resistor R81 that suppresses the current of the PMOS 81. The gate electrode of the PMOS 81 is supplied with a potential VG8 obtained by resistance division between the power supply potential VDD and the ground using a power supply potential dividing circuit composed of resistors R83 and R84 connected in series, and the drain potential VD8 has two stages. It is output as an output signal PWON of the power supply potential detection circuit via an inverter array INV81 including inverters. The output signal PWON of the power supply potential detection circuit is input to the control circuit of the semiconductor memory device. Note that VSUB81 is the substrate bias potential of the PMOS81.
[0004]
Next, the relationship between the change in the power supply potential VDD and the on / off operation of the PMOS 81 will be described in detail using equations (1) and (2).

Here, Vthp81 (<0) is the threshold voltage of the PMOS 81 (normally off type).
[0005]
If the power supply potential VDD rises from zero to a value in the range represented by equation (1), the potential difference between the gate and source of the PMOS 81 becomes equal to or greater than the threshold value, so that the PMOS 81 changes from the off state to the on state. The drain potential VD8 increases. This is output as an output signal PWON via the two-stage inverter circuit INV81, and the output signal PWON is received by a subsequent circuit to detect an increase in the power supply potential VDD.
[0006]
Next, if the power supply potential VDD falls to a value in the range represented by the expression (2), the potential difference between the gate and the source of the PMOS 81 becomes equal to or less than the threshold value, so that the PMOS 81 changes from the on state to the off state, The drain potential VD8 of the PMOS 81 decreases, and this is output as an output signal PWON via the two-stage inverter circuit INV81, and the output signal PWON is received by the subsequent circuit to detect a decrease in the power supply potential VDD.
[0007]
Here, the resistance of the current limiting resistor R81 of the PMOS 81 is R, the parasitic capacitance is C, and the R * C time constant of the current limiting resistor R81 is τ._RC819 and FIG. 10, the potential waveform of each potential node shown in FIG. 8 will be described. First, referring to FIG. 9, the power supply potential VDD is the time constant τ of the current limiting resistor._RC81A case where the change is sufficiently slow as compared with FIG.
[0008]
As shown by the solid line VDD in FIG. 9, the power supply potential VDD rises linearly from zero potential to a predetermined potential, shows a trapezoidal time change that falls to zero potential again after maintaining the predetermined potential for a certain period of time. And At this time, the output potential VG8 of the power supply potential dividing circuits R83 and R84 in FIG. 8 shows a trapezoidal time change obtained by dividing the power supply potential VDD by resistance as shown by the solid line VG8 in FIG.
[0009]
Initially, both VDD and VG8 are at zero potential, and the PMOS 81 in FIG. 8 is normally off, so the PMOS 81 is off. Since the drain potential VD8 of the PMOS 81 is grounded via the current limiting resistor R81, the drain potential VD8 of the PMOS 81 is also zero potential.
[0010]
Time t_{1 a}, The gate-source voltage VDD-VG8 of the PMOS 81 becomes equal to or greater than the absolute value | Vthp81 | t_{1 a}It rises to the potential of the solid line VDD at. This time change of VD8 becomes the output signal PWON of the power supply potential detection circuit via INV81 of FIG. 8, and is output along with the time change of VD8 as shown by the broken line PWON of FIG.
[0011]
Next, time t_{2 a}Since the gate-source voltage VDD-VG8 of the PMOS 81 becomes equal to or lower than the absolute value | Vthp81 | of the threshold voltage of the PMOS 81, the PMOS 81 is turned off and the drain potential VD8 of the PMOS 81 is_{2 a}The time constant τ of the current limiting resistor R81 from the potential of the solid line VDD in FIG._RC81Drops to zero potential.
[0012]
At this time, if the rate of decrease of the power supply potential VDD is sufficiently slow, the time constant τ_RC81Is negligible, the drain potential VD8 of the PMOS 81 is equal to the time t_{2 a}The voltage drops substantially vertically from the potential of the solid line VDD to zero. This time change of VD8 becomes the output signal PWON of the power supply potential detection circuit via INV81 in FIG. 8, and is output along with the time change of VD8 as shown by the broken line in FIG.
[0013]
In this manner, the time change of the power supply potential VDD shown in FIG. 9 can be detected at a predetermined timing, and the output signal PWON of the power supply potential detection circuit having a steep rising / falling shape can be obtained. The detection time and pulse width of PWON are determined by the potential division ratio of the power supply potential dividing circuits R83 and R84 and the value of the threshold voltage Vthp81 of the PMOS 81.
[0014]
Next, the time constant τ of the current limiting resistor R81 from the falling time of the power supply potential VDD_RC81The problem that occurs when the length is long will be described. Time constant τ of current limiting resistor R81_RC81Is longer than the falling time of the power supply potential VDD, the time t_{2 a}The PMOS 81 is turned off at this time, and the drain potential VD8 is changed to the time constant τ through the current limiting resistor R81._RC81Since the power supply potential VDD reaches the zero potential earlier than the time when the discharge to the ground side is started, the discharge of the potential VD8 to the ground side can no longer follow the change of the power supply potential VDD._{2 a}Thus, the start point of the potential drop of VD8 is not detected.
[0015]
The potential node waveforms at this time will be described in detail with reference to FIG. The potential waveform in FIG. 10 is shown with the time axis enlarged compared to FIG. 9 in order to make it easy to see the time change of VDD at high speed. Time t₁When the PMOS 81 is turned on, the capacitance component of the current limiting resistor R81 is charged at high speed due to the large on-current of the PMOS 81. Accordingly, the drain potential VD8 rises at high speed, and the output signal PWON can detect the rise of the power supply potential VDD as shown by the broken line in FIG.
[0016]
However, time t₂If the PMOS 81 is turned off at time t in FIG.₂As indicated by the solid line VD8 below, the drain potential VD8 of the PMOS 81 has a time constant τ._RC81If the gradual change of the drain potential VD8 does not reach the threshold value for inverting the first stage of the inverter array INV81, the output signal PWON output from the next stage inverter is the output of the next stage inverter. It remains at the output high level (usually equal to VDD).
[0017]
Therefore, the output signal PWON shown by the broken line in FIG. 10 changes with time along the power supply potential VDD. That is, the output signal PWON is time t₂It changes along with the time change of VDD without detecting the potential drop of VDD.
[0018]
In this way, if the power supply potential VDD drops at a high speed, the drain potential VD8 is equal to the time constant τ of the current limiting resistor R81 even when the potential difference between the gate and source of the PMOS 81 becomes equal to or lower than the threshold value of the PMOS 81 and is turned off._RC81For this reason, it is impossible to finish the lowering, and since the gentle lowering state is not transmitted to the subsequent INV 81, it is impossible to detect the lowering of the power supply potential VDD.
[0019]
[Problems to be solved by the invention]
As described above, the conventional power supply potential detection circuit can detect a rise in the power supply potential at a high speed, but has a problem that it cannot detect a drop in the power supply potential at a high speed.
[0020]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power supply potential detection circuit capable of detecting a high-speed power supply potential fall as well as a high-speed power supply potential rise. .
[0021]
[Means for Solving the Problems]
The power supply potential detection circuit according to the present invention applies a power supply potential to the source electrode of the first PMOS transistor via the delay circuit and detects the power supply potential drop at high speed, and the first power supply potential dividing circuit to the gate electrode. Is provided so that the first PMOS transistor is turned on when the power supply potential falls, and an output signal for detecting a fast power supply potential fall using the on-current of the first PMOS transistor. Is generated.
[0022]
On the other hand, when the power supply potential is increased at high speed, the power supply potential is directly applied to the source electrode of the second PMOS transistor and the output of the second power supply potential dividing circuit is applied to the gate electrode. The second PMOS transistor is turned on, and an output signal for detecting a high-speed rise in the power supply potential is generated using a large on-current of the second PMOS transistor.
[0023]
By synthesizing the output signals detected in this way using an inverter array and a logic circuit, it is possible to provide a power supply potential detection circuit that detects both an increase and a decrease in power supply potential at high speed.
[0024]
In the above description, PMOS and NMOS are examples, and the present invention is not necessarily limited to MOS transistors. Since the present invention is generally applicable to MIS transistors (Metal-Insulator-Semiconductor transistors) as well, the PMOS illustrated in the description of the present invention is a P-type MIS transistor. The NMOS is called an N-type MIS transistor.
[0025]
Specifically, the power supply potential detection circuit of the present invention includes at least a source electrode to which a power supply potential is applied through a resistance / capacitance delay circuit, a drain electrode grounded through a current control resistor, and a power supply potential dividing circuit. It has a P-type MIS transistor provided with a gate electrode for inputting an output potential.
[0026]
The power supply potential detection circuit of the present invention includes a first P-type MIS transistor, a second P-type MIS transistor, a first inverter row to which a drain potential of the first P-type MIS transistor is input, The drain potential of the second P-type MIS transistor is high when receiving the output of the second inverter row to which the drain potential of the second P-type MIS transistor is input and the outputs of the first and second inverter rows. When the drain potential of the first P-type MIS transistor is low level, a predetermined logic signal of the first level is output, the drain potential of the second P-type MIS transistor is low level, and the first P-type MIS transistor And a logic circuit that outputs a predetermined logic signal at a second level obtained by inverting the first level when the drain potential of the type MIS transistor is at a high level. To.
[0027]
The power supply potential detection circuit according to the present invention includes a source electrode to which a power supply potential is applied through a resistance / capacitance delay circuit, a drain electrode grounded through a first current control resistor, and a first power supply potential. A first P-type MIS transistor having a gate electrode for inputting an output potential of the dividing circuit, a source electrode to which a power supply potential is applied, a drain electrode grounded through a second current control resistor, and a second A second P-type MIS transistor having a gate electrode for inputting the output potential of the power supply potential dividing circuit, an even-numbered first inverter row for inputting the drain potential of the first P-type MIS transistor, And an odd-numbered second inverter row for inputting the drain potential of the P-type MIS transistor, and a NOR gate for receiving the outputs of the first and second inverter rows.
[0028]
Preferably, the resistance / capacitance delay circuit includes a combination circuit of one or a plurality of resistors and capacitors, and the power supply potential dividing circuit includes a resistor circuit in which a plurality of resistors are connected in series, or a plurality of capacitors. It has a capacitor circuit connected in series or a combination circuit of a plurality of resistors and capacitors, and the time constant of the resistor / capacitor delay circuit is larger than that of the power supply potential dividing circuit and the current control resistor. It is characterized by.
[0029]
Preferably, a diode or a diode-connected MIS transistor is inserted between the resistor / capacitance delay circuit and the P-type MIS transistor.
[0030]
Preferably, the resistor / capacitance delay circuit includes a plurality of resistors connected in series, one end of the plurality of resistors and the ground, and a connection node of the plurality of resistors and the ground. A power supply potential is directly applied to one terminal portion of the plurality of resistors, and a power supply potential is applied to each connection node via a diode or a diode-connected MIS transistor. In addition, a source electrode of the P-type MIS transistor is connected to the other end portion of the plurality of resistors.
[0031]
The power supply potential detection circuit of the present invention includes a source electrode to which a power supply potential is applied, a drain electrode grounded via a current control resistor having first and second resistors connected in series, and a series connection. A P-type MIS transistor having a gate electrode to which the output potential of the power supply potential dividing circuit having the third and fourth resistors or the first and second capacitors connected in series is input; and the drain of the P-type MIS transistor A first inverter to which the potential of the electrode is input; a drain electrode connected directly or via the first resistor to the drain electrode of the P-type MIS transistor; a grounded source electrode; and the first An N-type MIS transistor having a gate electrode for inputting the output potential of the inverter, and the output potential of the first inverter is output via the second inverter. The features.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a diagram showing a configuration of a power supply potential detection circuit according to the first embodiment of the present invention.
[0033]
In FIG. 1, the source electrode of the PMOS 11 is connected to the power supply potential VDD via a delay circuit RC <b> 1 composed of a resistor and a capacitor, and the drain electrode is grounded via a current control resistor R <b> 11 that restricts the current of the PMOS 11. Further, the gate potential VG1 obtained by dividing the resistance between the power supply potential VDD and the ground is input to the gate electrode of the PMOS 11 using a power supply potential dividing circuit including resistors R13 and R14 connected in series. The drain potential VD1 is input to one input terminal of the two-input NOR gate NOR1 via an inverter array INV11 including two-stage inverters.
[0034]
Further, the source electrode of the PMOS 12 is directly connected to the power supply potential VDD, and the drain electrode is grounded via a current control resistor R12 that restricts the current of the PMOS 12. Also, the gate potential VG2 obtained by dividing the resistance between the power supply potential VDD and the ground using the power supply potential dividing circuits R15 and R16 is input to the gate electrode of the PMOS 12, and the drain potential VD2 is the one-stage inverter INV12. And the other input terminal of the two-input NOR gate NOR1, and the output signal PWON of the power supply potential detection circuit is output from the output terminal of NOR1. Here, the PMOS 11 and the PMOS 12 are normally-off transistors having threshold voltages Vthp11 and Vthp12 (both are negative values), respectively.
[0035]
Next, the operation of the power supply potential detection circuit according to the first embodiment will be described in detail using the potential waveform of each potential node shown in FIG.
In the process of increasing the power supply potential VDD, the difference between the power supply potential VDD and the gate potential VG2 output from the power supply potential dividing circuits R15 and R16 is the time t.₁When the threshold voltage | Vthp12 | of the PMOS 12 is exceeded, the PMOS 12 which is initially in the off state is changed to the on state, and the drain potential VD2 is rapidly increased from zero to the potential of VDD as indicated by the solid line.
[0036]
The drain potential VD2 of the PMOS 12 is output via the inverter INV12 and the NOR gate NOR1 as the output signal PWON of the power supply potential detection circuit as shown by the broken line in FIG. The potential of the output signal PWON after the PMOS 12 is turned on rises along VDD if the high level of NOR1 is equal to the power supply potential VDD. In this manner, the output signal PWON of the power supply potential detection circuit is output at a high speed from the output terminal of the 2-input NOR gate NOR1.
[0037]
Similarly, in the process of increasing the power supply potential VDD, the gate potential VG1 output from the power supply potential dividing circuits R13 and R14 is applied to the gate electrode of the PMOS 11 which is initially in the off state, but the source electrode of the PMOS 11 has resistance and capacitance. Since the source potential VDD1 of the PMOS 11 is connected to the power supply potential VDD via the delay circuit RC1 consisting of the time constant τ of the delay circuit RC1 from the rise of the power supply potential VDD._RC1As a result, the maximum value of the power supply potential VDD is reached behind the flat portion of the power supply potential VDD (after the time width tw in FIG. 2) (charging of the capacitor of RC1 is completed).
[0038]
Here, in the first embodiment, the potential difference between the maximum value of the power supply potential VDD in the flat portion and the gate potential VG1 of the PMOS 11 is set so as not to exceed the threshold voltage | Vthp11 | of the PMOS 11. . For this reason, even if the power supply potential VDD exceeds the maximum time width tw, the PMOS 11 is still in the off state.
[0039]
Next, consider a case where the power supply potential drops rapidly. Although the charge accumulated in the capacitance of the delay circuit RC1 in the previous charging process falls, the time constant τ of the resistance of RC1_RC1Therefore, the source potential VDD1 of the PMOS 11 gradually falls behind the linear drop of the power supply potential VDD as shown in FIG.
[0040]
Accordingly, the PMOS 11 is turned on at time t2 when the potential difference between the source potential VDD1 of the PMOS 11 and the gate potential VG1 output from the power source potential dividing circuits R13 and R14 exceeds the threshold voltage | Vthp11 | VD1 rises at high speed. In this manner, the high-speed falling of the output signal PWON of the power supply potential detection circuit is output from the output terminal of the 2-input NOR gate NOR1 via the two inverter rows INV11.
[0041]
In the power supply potential detection circuit according to the first embodiment, when the PMOS 12 is turned on, a rise in the power supply potential VDD is detected through a fast rise in the drain potential VD2, and when the PMOS 11 is turned on, the drain potential VD1 is increased. A drop in power supply potential VDD is detected through a fast rise.
[0042]
That is, the high rises in the drain potentials VD2 and VD1 are respectively input to the 2-input NOR gate NOR1 via the INV12 including an odd number of inverter rows and the INV11 including an even number of inverter rows, and are output as NOR1. The rising and falling edges of the output signal PWON of the power supply potential detection circuit are output at high speed. In this way, it is possible to detect a drop in the power supply potential VDD, which has been difficult in the past, at high speed.
[0043]
FIG. 1 shows a case where INV11 and INV12 are each composed of one and two inverters. In the first embodiment, the R * C time constant τ depending on the resistance value and the capacitance component of the current limiting resistor R11 is used._RC11And the R * C time constant τ of the power supply potential dividing circuits R13 and R14_RC13And τ_RC14Is the time constant τ of the resistor / capacitance delay circuit_RC1Compared to the above, the operation of the power supply potential detection circuit is not significantly affected.
[0044]
In the first embodiment, the power supply potential dividing circuit has been described in the case where a plurality of resistors (two resistors in FIG. 1) are connected in series. However, the power supply potential dividing circuit has a plurality of capacitors connected in series. Even if connected, it can operate in the same manner. In general, a power supply potential dividing circuit can be formed by combining a plurality of resistors and capacitors.
[0045]
Second Embodiment
Next, the configuration and operation of the power supply potential detection circuit according to the second embodiment will be described with reference to FIGS. The configuration of the power supply potential detection circuit shown in FIGS. 3 and 4 is a modification of the first embodiment, and is a MOS transistor diode-connected between the resistance / capacitance delay circuit and the PMOS source electrode, or Since the configuration is the same as that of the first embodiment except that a diode is connected, the same reference numerals are assigned to the corresponding circuit elements, description thereof will be omitted, and only differences will be described.
[0046]
In the power supply potential detection circuit shown in FIG. 3, a diode-connected normally-off type PMOS 33 in which the gate and drain electrodes are connected to each other between the resistance / capacitance delay circuit RC3 and the source electrode of the PMOS 31 has a common gate and drain. It is characterized in that the electrode is inserted on the PMOS 31 side and the source electrode is on the RC3 side. As described above, the diode-connected PMOS 33 has a diode characteristic in which the source electrode is the anode side and the gate / drain common electrode is the cathode side, and thus has a potential level shift function with respect to the forward current of the diode characteristic.
[0047]
As described above, in the power supply potential detection circuit shown in FIG. 3, the output signal PWON rises when the PMOS 32 is turned on, and the output signal PWON falls when the PMOS 31 is turned on. Therefore, when a level shift operation of the potential of the diode-connected PMOS 33 is applied to the source side of the PMOS 31, the PMOS 32 is turned on (PWON rises) and the PMOS 31 is turned on (PWON falls) VDD. Can be different from those of the first embodiment.
[0048]
In this way, it is possible to increase the shape of the output signal PWON and the degree of freedom in setting the output timing in the power supply potential detection circuit. In the second embodiment, the case where the PMOS is diode-connected has been described. However, the NMOS gate-drain common electrode is diode-connected as the anode electrode, and the gate-drain common electrode is on the RC4 side, and the NMOS source is connected. A similar effect can be obtained by inserting an NMOS with the electrode on the source side of the PMOS 41.
[0049]
In the power supply potential detection circuit shown in FIG. 4, a diode Di41 is inserted between the resistance / capacitance delay circuit RC4 and the source electrode of the PMOS 41 with the cathode electrode on the PMOS 41 side and the anode electrode on the RC4 side. It goes without saying that the same effect can be obtained if the diode itself is used instead of the diode-connected MOS transistor.
[0050]
<Third Embodiment>
Next, a third embodiment will be described with reference to FIG. In the third embodiment, a modification of the resistance / capacitance delay circuit according to the first and second embodiments will be described.
[0051]
FIG. 5A is characterized in that a power supply potential VDD is applied to each connection node between the resistor and the capacitor constituting the resistor / capacitance delay circuit RC5a via a diode-connected NMOS. Similarly, in FIG. 5B, the power supply potential VDD is applied to each connection node between the resistor and the capacitor constituting the resistor / capacitance delay circuit RC5b via the diode-connected PMOS. Similarly, in FIG. 5C, the power supply potential VDD is applied to each connection node between the resistor and the capacitor constituting the resistor / capacitance delay circuit RC5c via a diode. 5 is a circuit obtained by removing the resistor / capacitance delay circuit RC1 from the circuit shown in FIG.
[0052]
In this way, when the power supply potential VDD rises, each capacitor constituting the resistor / capacitance delay circuit is rapidly connected to VDD−Vth by the forward current of the diode-connected NMOS, the diode-connected PMOS, or the diode Di, or Since it is charged up to VDD-Vbi (Vbi is the built-in potential of the diode), the connection nodes of these capacitors and resistors, and the circuit in FIGS. 5 (a), 5 (b) and 5 (c) The source potentials VDD5a, VDD5b, and VDD5c of the PMOS included in 1 (PMOS 11 in FIG. 1) rise to the region of the time width tw (see FIG. 2) that becomes the maximum potential as the power supply potential VDD increases.
[0053]
Here, the difference Vth from the power supply potential VDD when the diode-connected NMOS and PMOS are used, and the difference Vbi from the power supply potential VDD when the diode Di is used are shown in FIG. 5 (a), FIG. As shown in FIG. 5 (c), it is supplemented by directly connecting one terminal of the delay circuits RC5a, RC5b, and RC5c to VDD, and it becomes possible to reach the maximum potential almost along the rise of VDD. .
[0054]
Therefore, the time constant τ of the resistance / capacitance delay circuit RC1 in the process of increasing the power supply potential VDD described above with reference to FIGS._RC1The delay of the potential rise at the source potential VDD1 of the PMOS 11 due to the output is eliminated, and the time width tw required as a waiting time until the charging of the capacitor of the resistor / capacitance delay circuit RC1 is completed can be made substantially zero. .
[0055]
Next, in the process of lowering the power supply potential VDD, the accumulated charge of each capacitor constituting the resistor / capacitance delay circuit reversely biases the diode-connected NMOS, PMOS, or diode Di. As is the case with the first embodiment, it is possible to detect a decrease in the power supply potential VDD by turning on the PMOS 11 in the process of decreasing the power supply potential VDD.
[0056]
As described above, according to the third embodiment, the time width tw for maintaining the maximum value of VDD necessary to detect a rapid decrease in the power supply potential VDD is shortened as compared with the first embodiment. Therefore, it is possible to further increase the shape of the output signal PWON and the degree of freedom in setting the output timing in a particularly high-speed power supply potential detection circuit.
[0057]
<Fourth embodiment>
Next, a fourth embodiment will be described with reference to FIGS. The fourth embodiment is characterized in that, in addition to the PMOS for detecting the rise and fall of the power supply potential VDD, in particular, a feedback circuit made of NMOS for enhancing the detection capability of the power supply potential VDD at a high speed is formed. is there.
[0058]
The power supply potential detection circuit shown in FIG. 6 includes a source electrode to which a power supply potential VDD is directly applied, a drain electrode grounded via a current control resistor including resistors R61 and R62 connected in series, and a resistor connected in series. A PMOS 61 including a gate electrode to which an output of a power supply potential dividing circuit composed of R63 and R64 (or first and second capacitors connected in series) is input as a gate potential VG6 is provided.
[0059]
The drain potential VD6 of the PMOS 61 is input to the inverter INV61, and the output of the inverter INV61 is input to the gate of the NMOS 61 as the gate potential VGN61. The drain of the NMOS 61 is fed back directly to the drain of the PMOS 61 or to the drain of the PMOS 61 via the resistor R61.
[0060]
The source of the NMOS 61 is grounded, and the output potential of the inverter INV61 is output as the output signal PWON via the inverter INV62. Here, the threshold voltage of the PMOS 61 is Vthp61, the threshold voltage of the circuit of the inverter INV61 is Vthinv61, and the threshold voltage of the NMOS 61 is Vthn61.
[0061]
Next, the operation of the power supply potential detection circuit according to the fourth embodiment will be described with reference to FIG. Time t₁When the power supply potential VDD rises to a predetermined value in FIG. 5 and the potential difference with the gate potential VG6 of the PMOS 61 output from the power supply potential voltage dividing circuits R63 and R64 exceeds the threshold voltage | Vthp61 | Thus, the rise of the power supply potential VDD is detected by setting the output signal PWON to a high level.
[0062]
Next, time t₂When the power supply potential VDD falls to a predetermined value at the time point and the potential difference from the gate potential VG6 of the PMOS 61 becomes equal to or lower than the threshold voltage | Vthp61 | of the PMOS 61, the PMOS 61 is turned off and the drain potential VD6 starts to fall. As shown in FIG. 7, when the drain potential VD6 becomes lower than the threshold voltage Vthinv61 of the circuit of the inverter INV61, the output potential VGN61 of the INV61 starts to become a high level.
[0063]
If VGN61 input to the gate of NMOS61 exceeds the threshold voltage Vthn61 of NMOS61, NMOS61 is turned on and the connection point between R61 and R62 is grounded, so that drain potential VD6 of PMOS61 is pulled down at high speed, By setting the output signal PWON indicated by the broken line to a low level, it is possible to detect a rapid decrease in the power supply potential VDD.
[0064]
In this way, the resistor / capacitance delay circuit is not required as compared with the power supply potential detection circuits according to the first to third embodiments, and other circuit configurations are simplified. Thus, the number of power supply potential detection circuits can be reduced, and the chip area can be reduced.
[0065]
The present invention is not limited to the above embodiment. For example, when the second and third embodiments are combined, a power supply potential detection circuit with a higher degree of design freedom can be configured. In the third embodiment, the resistance / capacitance delay circuit is represented by an equivalent circuit composed of an R * C ladder, and the MOS transistor is diode-connected to each equivalent capacitor except the terminal portion to which the power supply potential VDD is directly applied. It was explained as connecting a diode. However, in an actual circuit, the values of the potentials VDD5a, VDD5b, and VDD5c at the connection point with the circuit 1 in FIG. 5 are determined including the capacitance component. It is desirable to connect. Various other modifications can be made without departing from the scope of the present invention.
[0066]
【The invention's effect】
As described above, according to the power supply potential detection circuit of the present invention, it is possible to provide a power supply potential detection circuit that detects a high-speed power supply potential drop as well as a high-speed power supply potential rise.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a power supply potential detection circuit according to a first embodiment.
FIG. 2 is a potential waveform diagram showing the operation of the power supply potential detection circuit according to the first embodiment.
FIG. 3 is a diagram showing a configuration of a power supply potential detection circuit according to a second embodiment.
FIG. 4 is a diagram showing another configuration of the power supply potential detection circuit according to the second embodiment.
FIG. 5 is a diagram showing a configuration of a resistance / capacitance delay circuit according to a third embodiment;
FIG. 6A is a diagram showing a circuit configuration using a diode-connected NMOS.
FIG. 6B is a diagram illustrating a circuit configuration using a diode-connected PMOS.
(C) is a figure which shows the circuit structure using a diode.
FIG. 6 is a diagram showing a configuration of a power supply potential detection circuit according to a fourth embodiment.
FIG. 7 is a potential waveform diagram showing an operation of a power supply potential detection circuit according to a fourth embodiment.
FIG. 8 is a diagram showing a configuration of a conventional power supply potential detection circuit.
FIG. 9 is a potential waveform diagram showing the operation of the conventional power supply potential detection circuit when the power supply potential is changed slowly.
FIG. 10 is a potential waveform diagram showing the operation of the conventional power supply potential detection circuit when the power supply potential changes at high speed.
[Explanation of symbols]
1 ... Circuit according to the first embodiment excluding a resistor / capacitance delay circuit
RC1, RC3, RC4, RC5a, RC5b, RC5c ... Resistance / capacitance delay circuit
INV11, INV31, INV41 ... Even number stage inverter
INV12, INV32, INV42 ... Odd stage inverter
INV61, INV62 ... Inverter
Vthp11, Vthp12, Vthp61: PMOS threshold voltage
Vthn61: NMOS threshold voltage
Vthinv61 ... INV61 circuit threshold voltage
VDD: Power supply potential
PWON: Power supply potential detection circuit output signal

Claims (5)

Inputs the source electrode provided with the internal power supply potential generated inside the circuit, the drain electrode grounded via the first current control resistor, and the output potential of the first power supply potential dividing circuit for dividing the external power supply potential A first P-type MIS transistor having a gate electrode to be
The source electrode to which the external power supply potential is applied, the drain electrode grounded through the second current control resistor, and the gate electrode for inputting the output potential of the second power supply potential dividing circuit for dividing the external power supply potential A second P-type MIS transistor comprising:
A first inverter row to which the drain potential of the first P-type MIS transistor is input;
A second inverter row to which the drain potential of the second P-type MIS transistor is input;
When the drain potential of the second P-type MIS transistor is high level and the drain potential of the first P-type MIS transistor is low level in response to the outputs of the first and second inverter arrays, When the first level predetermined logic signal is output and the drain potential of the second P-type MIS transistor is low level and the drain potential of the first P-type MIS transistor is high level, And a logic circuit that outputs a predetermined logic signal of a second level with the level inverted. A source electrode to which a power supply potential is applied via a resistance / capacitance delay circuit, a drain electrode grounded via a first current control resistor, and a gate electrode for inputting an output potential of the first power supply potential dividing circuit A first P-type MIS transistor provided;
A second P-type MIS having a source electrode to which a power supply potential is applied, a drain electrode grounded via a second current control resistor, and a gate electrode for inputting an output potential of the second power supply potential dividing circuit A transistor,
An even number of first inverter rows for inputting a drain potential of the first P-type MIS transistor;
An odd-numbered second inverter row for inputting a drain potential of the second P-type MIS transistor;
A NOR gate receiving the outputs of the first and second inverter trains;
A power supply potential detection circuit comprising: 3. The power supply potential detecting circuit according to claim 2 , wherein a time constant of the resistance / capacitance delay circuit is larger than that of the first power supply potential dividing circuit and the first current control resistor. 4. The power supply potential detection circuit according to claim 2 , wherein a diode or a diode-connected MIS transistor is inserted between the resistance / capacitance delay circuit and the first P-type MIS transistor. . A source electrode to which a power supply potential is applied, a drain electrode grounded via a current control resistor having first and second resistors connected in series, and a third and fourth resistor connected in series, or a series A P-type MIS transistor including a gate electrode to which an output potential of a power supply potential dividing circuit having first and second capacitors connected is input;
A first inverter to which the potential of the drain electrode of the P-type MIS transistor is input;
N having a drain electrode connected directly to the drain electrode of the P-type MIS transistor or via the first resistor, a grounded source electrode, and a gate electrode for inputting the output potential of the first inverter. Type MIS transistor;
Comprising
An output potential of the first inverter is output via a second inverter.

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