JP3855874B2 - Electronic component mounting method, IC chip mounting method, and IC chip - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an electronic component that is solder-mounted on a substrate by a plurality of terminals having two or more different connection areas.ofImplementation method, IC chip mounting method and IC chipThe present invention can be applied to, for example, a wafer level CSP and a flip chip mounting structure.
[0002]
[Prior art]
An electronic component having a plurality of terminals is mounted on a substrate having a plurality of terminals corresponding to the terminals of the electronic component, and each terminal of the electronic component and the terminal of the substrate are electrically and thermally connected via solder. There is a conventional mounting structure.
[0003]
For example, as an electronic component, there is a semiconductor element provided with a transistor, and the semiconductor element is provided with bump electrodes as a plurality of terminals. In this case, with the miniaturization of transistors, the bump electrodes are also required to have a narrow pitch. On the other hand, a higher power IC is required for a semiconductor element including a logic circuit and a power MOS transistor.
[0004]
For this reason, when mounting electronic components on a board, there are conflicting demands for reducing the pitch of terminals according to miniaturization of electronic components and ensuring heat dissipation according to higher power (that is, expanding the heat dissipation area). It is necessary to satisfy.
[0005]
Conventionally, when narrowing the pitch of bump electrodes arranged on the surface, the number of wirings for rearrangement increases with the increase in the number of arrangements, and the bump electrode dimensions are made smaller than the shrink rate of the bump electrode pitch. The need arises. That is, it is not necessary to make the bump electrode smaller in proportion to the degree to which the pitch of the bump electrode is made smaller, and it is necessary to make the bump electrode smaller.
[0006]
This will be specifically described with reference to FIG. FIG. 8 is a diagram showing a planar shape on the terminal surface side of the IC chip 10 as an electronic component having the heat generating portion (power element portion) 11. A plurality of solder bumps as terminals are formed on the terminal surface of the IC chip 10. The bump electrodes 12 are arranged. Then, as shown in FIGS. 8A to 8B, the pitch of the bump electrodes 12 as terminals is reduced.
[0007]
For example, in FIG. 8A, the bump electrode diameter d is φ0.25 mm, and the pitch P of the bump electrodes 12 is 0.5 mm. In this configuration, as shown in FIG. 8B, when the bump electrode pitch P ′ is reduced, for example, P ′ = 0.3 mm, the bump electrode diameter d ′ is about φ0.125 mm. Then, the area occupation ratio of the bump electrode 12 on the heat generating portion 11 is 20% in (a) but drops to 14% in (b).
[0008]
Furthermore, in the simplest case, the path through which the heat generated in the heat generating portion 11 is conducted to the substrate depends on the area of the bump electrode 12 formed immediately above the heat generating portion 11. In such a case, the thermal resistance against the heat radiation from the heat generating portion 11 can be calculated by the inverse proportion of the change in the area of the bump electrode accompanying the miniaturization as described above. For example, if the thermal resistance in FIG. 8 (a) is 1, it will be 1.5 in (b) and will be about 50% higher.
[0009]
For this reason, in order to ensure heat dissipation, as shown in FIG.8 (c), it is possible to make the bump electrode 12 on the heat generating part 11 larger than the bump electrode 12 other than that. However, in this case, the following problem occurs.
[0010]
In the case of the IC chip 10 shown in FIG. 8C, as shown in FIG. 9A, an amount of solder paste 30a proportional to the electrode area is applied to the bump electrodes 12 having different electrode areas (that is, connection areas). Supply by printing method.
[0011]
Here, the supply of the solder paste 30a to the IC chip 10 is normally performed at the wafer level, not in the chip state, and then the wafer to which the solder paste 30a is supplied is reflowed (wet back). This is to make the solder stable in order to perform electrical inspection of the element at the wafer level and to perform dicing cut thereafter.
[0012]
Therefore, as shown in FIG. 9B, after reflow, the solder 30 becomes extremely high as the bump electrode 12 has a larger connection area due to the surface tension of the solder, and the bump electrode 12 having a smaller connection area is connected. This causes a problem that it cannot be mounted.
[0013]
In order to avoid this problem, a method has been proposed in which solder is supplied only to the substrate side and the amount of solder supplied is controlled in accordance with the bump electrode dimensions, as disclosed in JP-A-7-263449. Specifically, when supplying solder by the vapor deposition method, the amount of solder supplied per unit area is reduced with a large bump electrode compared to the amount of solder supplied to a small bump electrode.
[0014]
[Problems to be solved by the invention]
If the technique for controlling the supply amount of solder according to the bump electrode dimensions as in the above-mentioned conventional publication is applied to an electronic component that requires reflow, the height of the solder after reflow is considered to be substantially uniform. .
[0015]
However, in the above-mentioned conventional publication, the solder is supplied by relatively expensive vapor deposition, and as a result, it becomes extremely expensive. Further, it is difficult to control the solder supply amount according to the electrode dimensions by a relatively inexpensive printing method.
[0016]
In addition, even if the current mainstream method is to use an inexpensive solder ball method, it is necessary to change the diameter of the solder ball to be supplied in accordance with the size of each electrode, resulting in an increase in cost.
[0017]
In any case, conventionally, when at least one terminal of the electronic component and the substrate is composed of two or more types of terminals having different connection areas, the electronic component terminal and the substrate terminal are appropriately connected and mounted. There was no method that could be realized at low cost. Under such circumstances, it is difficult to cope with a narrow pitch and high power of terminals in electronic components.
[0018]
Therefore, in view of the above problems, the present invention has attempted to reduce the pitch of terminals and increase the power in electronic components when soldering electronic components on a substrate via two or more types of terminals having different connection areas. However, an object is to enable solder connection between the electronic component and the substrate at low cost.
[0019]
[Means for Solving the Problems]
  In order to achieve the above object, according to the first aspect of the present invention, an electronic component (10) having a plurality of terminals (12) is replaced with a substrate having a plurality of terminals (22) corresponding to the terminals of the electronic components ( 20), the terminal of the electronic component and the terminal of the board are electrically and thermally connected via the solder (30), and the terminal of the board has at least two types of connection areas. In the electronic component mounting method, the terminal (22b) having a relatively large connection area among the terminals of the board is supplied with solder to the board side, and the solder supplied to the board side is reflowed, followed by pressure molding. As for the terminal (22a) having a relatively small connection area, the height of the electronic component side terminal corresponding to the terminal is adjusted.(12a)It is characterized by supplying solder.
[0020]
According to the mounting method of the present invention, for terminals having a relatively large connection area, the solder is supplied to the substrate side that does not require reflow after the solder is supplied.
[0021]
  According to a second aspect of the present invention, an IC chip (10) having a plurality of terminals (12) is mounted on a substrate (20) having a plurality of terminals (22) corresponding to the terminals of the IC chip. A method of mounting an IC chip, wherein the terminal of the IC chip and the terminal of the substrate are electrically and thermally connected via solder (30), and the terminal of the substrate has at least two types of connection areas InThe IC chip includes a logic circuit and a power MOS transistor,Of the terminals on the board, the terminal (22b) having a relatively large connection area is supplied with solder, and the terminal (22a) having a relatively small connection area is a terminal on the IC chip side corresponding to the terminal.(12a)It is characterized by supplying solder.According to a third aspect of the present invention, an IC chip (10) having a plurality of terminals (12) is mounted on a substrate (20) having a plurality of terminals (22) corresponding to the terminals of the IC chip. A method of mounting an IC chip, wherein the terminal of the IC chip and the terminal of the substrate are electrically and thermally connected via solder (30), and the terminal of the substrate has at least two types of connection areas The terminal (12b) on the IC chip side corresponding to the terminal (22b) having a relatively large connection area among the terminals on the substrate is a power MOS electrode, and the relatively large connection area among the terminals on the substrate is Solder is supplied to the substrate side for the terminal (22b) having it, and solder is supplied to the terminal (12a) on the IC chip side corresponding to the terminal (22a) having a relatively small connection area. And it said that there was Unishi. theseAccording to the mounting method of the invention, the solder having a relatively large connection area is supplied to the substrate side that does not require reflow after the solder is supplied. Therefore, the claim4And claims5When the solder paste or the solder sheet is supplied to the substrate side as in the mounting method described in 1), the IC chip can be mounted on the substrate without reflowing them.
[0022]
  In other words, even if these solder pastes and solder sheets are supplied in proportion to the area of the terminals with a large connection area,IC chipCan be reflowed after mounting, so the solder rises high during the reflowIC chipHowever, there is no problem that cannot be implemented.
[0023]
  Claims6If the height is adjusted by pressure forming after reflowing the solder supplied to the board side, as in the mounting method described in 1. Can be easily corrected.
[0024]
  Thus, the claims 2 to 26In the mounting method described in the above, since it is not necessary to control and supply the solder amount per unit area to terminals having different connection areas, it is possible to supply by printing using the above-described solder paste or use a solder sheet. For example, solder can be supplied at low cost.
[0025]
  AndIC chipWhen installingIC chipBetween the terminals and the substrate, contact via solder is reliably performed even between terminals having a small connection area. Then, the solder connection between each terminal is performed by reflowing the solder between each terminal, and the mounting structure is completed.
[0026]
  As described above, among the terminals on the board, solder is supplied to the board side for terminals having a relatively large connection area, and for terminals having a smaller connection area, this is supported.IC chipBy supplying the solder to the terminal on the side, it is possible to prevent connection failure due to the rise of solder in the terminal having a large connection area.
[0027]
  Accordingly, claims 2 to claim6According to the mounting method described in (4), even if the terminal pitch is narrowed or the power is increased in the IC chip,IC chipCan be soldered to the substrate.
[0032]
  Claims7In the invention described inA logic circuit and a power MOS transistor;In an IC chip including a plurality of terminals (12) having two or more different connection areas, solder (30) is supplied to a terminal (12a) having a relatively small connection area among the plurality of terminals, and relatively connected. Solder is not supplied to the terminal (12b) having a large area.In the invention according to claim 8, in an IC chip including a plurality of terminals (12) having two or more different connection areas, a terminal (12b) having a relatively large connection area among the plurality of terminals is provided. It is a power MOS electrode, and solder (30) is supplied to a terminal (12a) having a relatively small connection area among a plurality of terminals, and solder is supplied to a terminal (12b) having a relatively large connection area. It is characterized by not.
[0033]
  Claims 7 and 8The IC chip of the present invention is claimed in claims 2 to 2.6In this case, even if the terminal pitch is narrowed or the power is increased in the IC chip as described above, the solder connection between the IC chip and the substrate can be performed at a low cost. It can be carried out.
[0036]
In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. In the following embodiments, the same parts are denoted by the same reference numerals in the drawings.
[0038]
(First embodiment)
1A and 1B are views showing an electronic component and a mounting structure thereof according to the first embodiment of the present invention. FIG. 1A is a plan view of a terminal surface on which terminals of the electronic component 10 are formed, and FIG. 2 is a schematic cross-sectional view of a mounting structure in which the electronic component 10 shown in FIG.
[0039]
The electronic component 10 shown in FIG. 1 is not particularly limited, but is an IC chip 10 as a semiconductor circuit substrate in this example, and includes a logic circuit and a power MOS transistor (not shown). In FIG. 1A, a region surrounded by a broken line is a power MOS portion 11 as a heat generating portion in the IC chip 10.
[0040]
A plurality of terminals 12 having two or more different connection areas are formed on the terminal surface of the IC chip 10. The terminals 12 of the IC chip 10 have signal electrodes 12a arranged in a uniform size and a uniform pitch, and a power MOS portion formed in an arbitrary shape so as to cover the power MOS portion 11 and having a larger connection area than the signal electrodes 12a. Electrode 12b.
[0041]
The signal electrode 12a as an electronic component terminal having a relatively small connection area and the power MOS portion electrode 12b as an electronic component terminal having a relatively large connection area can be formed by using a normal bump forming technique. For example, an anti-oxidation Au film may be laminated on the surface of Ni or Cu by electroplating or electroless plating.
[0042]
These terminals 12 are electrically connected to an Al wiring (not shown) of the semiconductor circuit in the IC chip 10. In particular, the power MOS part electrode 12b may be used in a non-conducting state exclusively for heat dissipation of the power MOS part 11, or may be used in a state of being conducted to a power MOS circuit through which a large current flows.
[0043]
On the other hand, an arbitrary wiring board such as a printed board or a ceramic board can be adopted as the board 20. A plurality of terminals 22 having two or more different connection areas corresponding to the terminals 12 of the IC chip 10 are formed on the mounting surface (electronic component mounting surface) of the IC chip 10 on the substrate 20.
[0044]
These terminals 22 of the substrate 20 are electronic component connection lands, and are electrically connected to a wiring portion (not shown) of the substrate 20. In this embodiment, the terminal 22 of the board | substrate 20 when it sees from an electronic component mounting surface has the same arrangement | positioning and the same shape as the terminal 12 of the IC chip 10 shown by Fig.1 (a).
[0045]
That is, the terminal 22 of the substrate 20 includes signal lands 22a formed at a position corresponding to the signal electrode 12a of the IC chip 10 and arranged at a uniform pitch and a power MOS portion electrode 12b of the IC chip 10. And a power MOS portion land 22b having a larger connection area than the signal land 22a.
[0046]
The signal land 22a as a substrate terminal having a relatively small connection area and the power MOS portion land 22b as a substrate terminal having a relatively large connection area, as in the case of the terminal 12 of the IC chip 10, are formed by a normal bump forming technique. Can be used. For example, like the terminal 12 of the IC chip 10, an anti-oxidation Au film can be laminated on the surface of Ni or Cu by electroplating or electroless plating.
[0047]
Then, as shown in FIG. 1B, the IC chip 10 is mounted on the substrate 20 in a state where the electronic component mounting surface of the substrate 20 and the terminal surface of the IC chip 10 face each other and the terminals 12 and 22 thereof coincide with each other. It is mounted on. Each terminal 12 of the IC chip 10 and each terminal 22 of the substrate 20 are electrically and thermally connected via a solder 30 made of Sn-Ag solder or the like.
[0048]
In addition, an underfill material 40 made of an epoxy resin or the like is filled between the IC chip 10 and the substrate 20 to supplement the mechanical strength of the connection portion connected by the solder 30.
[0049]
According to such an electronic component mounting structure, it is possible to reduce the pitch of the terminals of the IC chip 10 by the signal electrodes and the lands 12a and 22a. In addition, since the heat dissipation of the power MOS portion 11 is ensured by the power MOS portion electrodes and the lands 12b and 22b having a large area, the power of the IC chip 10 can be increased.
[0050]
Next, a mounting method for making the mounting structure of the electronic component will be described with reference to FIG. FIG. 2 is a process diagram showing the present mounting method.
[0051]
In this mounting method, first, the solder 30 is supplied only to the signal electrode 12a having a relatively small connection area with respect to the IC chip 10 including the plurality of terminals 12a and 12b having two or more different connection areas. Solder is not supplied to the power MOS portion electrode 12b having a larger connection area than the signal electrode 12a.
[0052]
The solder 30 is supplied to the signal electrode 12a of the IC chip 10 at low cost by a solder ball method using a solder ball of a uniform size corresponding to the signal electrode 12a or a printing method of printing as a solder paste. it can.
[0053]
Thus, in the IC chip 10 to which the solder 30 is supplied, the solder 30 is supplied to the terminal 12a having a relatively small connection area among the plurality of terminals 12, and the solder is supplied to the terminal 12b having a relatively large connection area. It is configured as an electronic component that is not supplied.
[0054]
On the other hand, on the electronic component mounting surface of the substrate 20, solder is supplied only to the power MOS portion land 22b having a relatively large connection area among the terminals 22 of the substrate 20, and the connection area is smaller than that of the power MOS portion land 22b. Solder is not supplied to the signal land 22a having
[0055]
In the example shown in FIG. 2, the solder is supplied to the substrate 20 side by a cheap printing method using the solder paste 30a. In the state of the solder paste 30a, the solder does not rise due to the surface tension.
[0056]
Thus, in this mounting method, the solder 22 is supplied to the substrate 20 side of the terminals 22b having a relatively large connection area among the terminals 22 of the substrate 20 having two or more types of connection areas, and thus has a relatively small connection area. As for the terminal 22a, solder is supplied to the terminal 12a on the electronic component 10 side corresponding to the terminal 22a.
[0057]
After each solder is supplied in this way, the IC 20 is mounted on the substrate 20 by aligning the IC chip 10 and the terminals 12 and 22 of the substrate 20 without reflowing the solder on the substrate 20.
[0058]
At this time, since the solder is in a paste state, the board 20 does not rise high. Therefore, the terminals 12 a and 22 a having a small connection area are also in contact with each other through the solder 30.
[0059]
Then, by reflowing the solder between the IC chip 10 and the substrate 20, the solder connection between all the terminals 12a and 22a and 12b and 22b is performed. Thereafter, the underfill 40 is injected and filled to complete the mounting structure shown in FIG.
[0060]
As described above, according to the present mounting method, the solder having a relatively large connection area is supplied to the substrate 20 side that does not require reflow after the solder is supplied. Therefore, the IC chip 10 can be mounted on the substrate 20 without reflowing the solder supplied to the substrate 20 as the solder paste 30a.
[0061]
Therefore, the amount per unit area of the solder paste 30a supplied to the power MOS portion land 22b having a large connection area is not reduced compared to the amount of solder supplied to the signal electrode 12a of the IC chip 10 having a small connection area. Can be supplied. That is, solder can be supplied in proportion to the connection area.
[0062]
Even if such solder is supplied, since the solder is reflowed after the IC chip 10 is mounted on the substrate 20, there is no problem that the IC chip 10 cannot be mounted because the solder rises high during the reflow.
[0063]
For this reason, in this mounting method, it is not necessary to control and supply the amount of solder per unit area for terminals having different connection areas, so that supply by printing using the above-described solder paste can be adopted, and solder supply Can be done inexpensively. In addition, it is possible to prevent a connection failure due to solder swell at a terminal having a large connection area as in the prior art.
[0064]
Therefore, according to this mounting method, even if the pitch of the signal electrodes 12a (that is, the pitch of the terminals) is reduced and the power of the power MOS unit 11 is increased in the IC chip 10, the IC chip 10 can be manufactured at low cost. Solder connection with the substrate 20 can be made.
[0065]
Next, a modification of the mounting method according to the first embodiment will be described. These are variations of the method of supplying solder to the substrate 20. FIG. 3 shows a first modification in which solder is supplied to the substrate 20 side using a solder sheet 30b. The solder sheet 30b is obtained by forming the solder 30 into a sheet shape.
[0066]
When the solder sheet 30b is used, the solder sheet 30b is cut into the shape of the power MOS portion land 22b of the substrate 20 and placed on the power MOS portion land 22b. Subsequently, without reflowing this, the IC chip 10 is mounted on the substrate 20 and then reflowed to perform solder connection.
[0067]
FIG. 4 shows a second modification. The solder 30 supplied to the power MOS portion land 22b of this example is obtained by reflowing the solder supplied in the form of a paste or a sheet on the substrate 20 side. Thereafter, the height is adjusted by pressure molding with a jig or the like.
[0068]
According to this, even if the substrate 20 is reflowed before mounting the electronic component, the height of the solder 30 that has been raised excessively by reflow in the power MOS land 22b having a large connection area can be easily corrected.
[0069]
Therefore, also in these modified examples, since it is possible to supply solder without changing the amount of solder per unit area with terminals having different connection areas, it is possible to employ an inexpensive supply method such as a printing method, a solder sheet, or a solder ball.
[0070]
For this reason, even with these modifications, even if the pitch of the signal electrodes 12a in the IC chip 10 is reduced and the power of the power MOS unit 11 is increased, the solder connection between the IC chip 10 and the substrate 20 can be performed at low cost. Can do.
[0071]
In the first embodiment, it is sufficient that the terminals of the substrate 20 have at least two types of connection areas, and the plurality of terminals on the IC chip 10 side may have the same connection area. good.
[0072]
For example, in FIG. 1, for the IC chip 10, the terminals located in the power MOS section 11 may have the same dimensions and the same pitch as the signal electrodes 12a. The terminal surface shape of the IC chip 10 in this case is the same as the terminal arrangement as shown in FIGS. 9 (a) and 9 (b).
[0073]
In this case, the terminals 22 of the substrate 20 are the same as those in FIG. Therefore, when the IC chip 10 is solder-connected to the substrate 20, the small terminal of the power MOS unit 11 in the IC chip 10 is electrically and thermally connected to the large power MOS unit land 22 b of the substrate 20. Further, since the small terminals of the power MOS unit 11 are connected by solder, heat dissipation is ensured.
[0074]
(Second Embodiment)
FIG. 5 is a schematic cross-sectional view showing the electronic component mounting method according to the second embodiment of the present invention. In the mounting method of this embodiment, the same IC chip 10 and substrate 20 as those shown in FIG. 1 are used.
[0075]
As shown in FIG. 5, an amount of solder proportional to the connection area was supplied to the terminals 12a and 12b of the IC chip 10 having at least two types of connection areas, and the supplied solder was reflowed. Thereafter, the height of the solder 30 is adjusted to be the same between the terminals 12a and 12b by pressure molding by pressing a jig against the solder.
[0076]
When an amount of solder proportional to the connection area is supplied to each terminal 12a, 12b on the IC chip 10 side having a different connection area by a simple printing method or a solder ball method, the connection is made after reflow performed in an electronic component. Solder height differs between terminals with different areas.
[0077]
However, in this embodiment, as shown in FIG. 5, the solder 30 of the power MOS portion electrode 12b that has become too high due to reflow is easily lowered by pressure molding, and the solder 30 is between the terminals 12a and 12b. Can be made the same height.
[0078]
In the IC chip 10 in which the height of the solder 30 is adjusted in this way, an amount of solder 30 proportional to the connection area is supplied to the plurality of terminals 12a and 12b, and the supplied solder 30 Is provided as an electronic component that is adjusted so that the heights are the same between the terminals 12a and 12b by pressure molding after reflow.
[0079]
The IC chip 10 shown in FIG. 5 is mounted on the substrate 20. At this time, solder is not supplied to the substrate 20. In this mounting, contact between the IC chip 10 and the substrate 20 through the solder 30 is reliably performed between the terminals having different connection areas. Then, the solder connection between the terminals 12 and 22 is performed by reflowing the solder 30.
[0080]
As described above, even with the mounting method of the present embodiment, even if the pitch of the signal electrodes 12a in the IC chip 10 is reduced or the power of the power MOS unit 11 is increased, the IC chip 10 and the substrate 20 can be inexpensively connected. Solder connection can be made.
[0081]
Further, as can be said in common with the first and second embodiments, the solder supply to the power MOS portion electrode 12b provided in the power MOS portion 11 of the IC chip 10 is performed by a printing method using a solder paste. Can be done. For this reason, since the degree of freedom of the electrode shape is greater than when formed with solder balls, the above-described arbitrary shape can be obtained, and the connection area can be increased, which is advantageous in improving heat dissipation.
[0082]
(Other embodiments)
6 and 7 show modified examples of the electrode arrangement on the terminal surface of the IC chip 10. FIG. 6 shows a first modification, and FIG. 7 shows a second modification.
[0083]
As shown in these modified examples, there may be a plurality of power MOS units 11, and the power MOS unit electrode 12 b may protrude from the region of the power MOS unit 11.
[Brief description of the drawings]
FIG. 1 is a diagram showing an electronic component and its mounting structure according to a first embodiment of the present invention.
FIG. 2 is a process diagram showing a mounting method for making the mounting structure shown in FIG. 1;
FIG. 3 is a diagram showing a first modification of the first embodiment.
FIG. 4 is a diagram showing a second modification of the first embodiment.
FIG. 5 is a schematic cross-sectional view showing a method for mounting an electronic component according to a second embodiment of the present invention.
FIG. 6 is a schematic plan view showing a first modification of electrode arrangement on the terminal surface of the IC chip.
FIG. 7 is a schematic plan view showing a second modification of the electrode arrangement on the terminal surface of the IC chip.
FIG. 8 is a diagram showing various planar configurations on the terminal surface side of an IC chip having a heat generating portion.
FIG. 9 is a cross-sectional view showing a process of supplying solder to electrode bumps having different electrode areas on an IC chip.
[Explanation of symbols]
10 ... IC chip, 12 ... IC chip terminal, 12a ... Signal electrode,
12b ... Power MOS part electrode, 20 ... Substrate, 22 ... Substrate terminal,
22a ... Signal land, 22b ... Power MOS part land, 30 ... Solder,
30a ... Solder paste, 30b ... Solder sheet.

Claims (8)

An electronic component (10) having a plurality of terminals (12) is mounted on a substrate (20) having a plurality of terminals (22) corresponding to the terminals of the electronic components,
The terminals of the electronic component and the terminals of the substrate are electrically and thermally connected via solder (30),
In the mounting method of the electronic component in which the terminal of the substrate has at least two types of connection areas,
The terminal (22b) having a relatively large connection area among the terminals of the substrate is supplied with solder to the substrate side, reflowed with the solder supplied to the substrate side, and then subjected to pressure molding to increase the height. A method of mounting an electronic component, characterized in that, for the terminal (22a) having a relatively small connection area, solder is supplied to the terminal (12a) on the electronic component side corresponding to the terminal. An IC chip (10) having a plurality of terminals (12) is mounted on a substrate (20) having a plurality of terminals (22) corresponding to the terminals of the IC chip,
The terminal of the IC chip and the terminal of the substrate are electrically and thermally connected via solder (30),
In the mounting method of the IC chip in which the terminal of the substrate has at least two kinds of connection areas,
The IC chip includes a logic circuit and a power MOS transistor,
Of the terminals of the substrate, the terminal (22b) having a relatively large connection area supplies solder to the substrate side, and the terminal (22a) having a relatively small connection area is on the IC chip side corresponding to the terminal. A method for mounting an IC chip, characterized in that solder is supplied to the terminal (12a) . An IC chip (10) having a plurality of terminals (12) is mounted on a substrate (20) having a plurality of terminals (22) corresponding to the terminals of the IC chip,
The terminal of the IC chip and the terminal of the substrate are electrically and thermally connected via solder (30),
In the IC chip mounting method in which the terminals of the substrate have at least two types of connection areas,
The terminal (12b) on the IC chip side corresponding to the terminal (22b) having a relatively large connection area among the terminals of the substrate is a power MOS electrode,
Among the terminals of the substrate, the terminal (22b) having a relatively large connection area supplies solder to the substrate side, and the terminal (22a) having a relatively small connection area corresponds to the IC chip corresponding to the terminal. A method for mounting an IC chip, characterized in that solder is supplied to the terminal (12a) on the side. The method for mounting an IC chip according to claim 2 or 3 , wherein the solder is supplied to the substrate (20) using a solder paste (30a). The method for mounting an IC chip according to claim 2 or 3 , wherein the solder is supplied to the substrate (20) using a solder sheet (30b). After reflow the solder supplied to said substrate (20) side, IC chip mounting method according to claim 2 or 3, characterized in that adjusting the height by pressure molding. In an IC chip comprising a logic circuit and a power MOS transistor and comprising a plurality of terminals (12) having two or more different connection areas,
Solder (30) is supplied to the terminal (12a) having a relatively small connection area among the plurality of terminals, and no solder is supplied to the terminal (12b) having a relatively large connection area. Chip. In an IC chip comprising a plurality of terminals (12) having two or more different connection areas,
Among the plurality of terminals, a terminal (12b) having a relatively large connection area is a power MOS electrode. And
Solder (30) is supplied to a terminal (12a) having a relatively small connection area among the plurality of terminals, and solder is not supplied to the terminal (12b) having a relatively large connection area. IC chip.

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