JP3863211B2 - Semiconductor silicon wafer and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of a dicing line portion of a semiconductor device.
[0002]
[Prior art]
In general, a semiconductor wafer that has completed a wafer process and completed a test is divided into semiconductor chips. This operation is called dicing. There are several dicing methods, but at present, the cutting method using a dicing saw is the mainstream. This cutting method using a dicing saw is a method of cutting silicon by rotating a thin disk embedded with diamond powder at a high speed. However, there is a problem that dicing causes cracks and reduces the reliability of the semiconductor device. It was.
[0003]
However, for silicon, which is a single crystal, the technology for suppressing the occurrence of cracks has been almost completed by various research and development. For this reason, dicing is performed by removing all the other films formed on the silicon in the dicing line portion, which is a portion to be diced, and forming only the silicon.
[0004]
However, in recent years, a technique for forming a W plug by embedding tungsten (hereinafter referred to as W) in a contact hole when forming a contact hole for wiring in a semiconductor device that conducts a large amount of current, such as a logic device. It is used. In this W plug formation process, first, a W film is deposited using WF ₆ gas, and then the entire surface is etched back to bury W in the contact hole.
[0005]
FIG. 3 is a plan view showing a semiconductor wafer on which a plurality of conventional semiconductor chips having W plugs are formed. In the figure, 1 is a silicon substrate on which a semiconductor wafer is formed, 2 is a plurality of semiconductor chips formed on the silicon substrate 1, and 3 is a dicing line formed between the semiconductor chips 2. At this time, when a W plug is formed in the semiconductor device formed on the semiconductor chip 2, if the silicon substrate 1 is exposed in the dicing line 3, the WF ₆ gas reacts with the silicon substrate 1 during the W film deposition. As a result, an alloy of W and Si is formed on the dicing line 3. Thereafter, when the W film is etched back, the shape of the dicing line 3 is remarkably deteriorated. Accordingly, the dicing line 3 between the semiconductor chips 2 having the W plug cannot be made of a silicon-only structure, and must have a structure in which an oxide film is left on the silicon.
[0006]
4 is a cross-sectional view taken along the line AA ′ of FIG. In the figure, 4 is an interlayer oxide film formed on the silicon substrate 1, 5 is a passivation film, 6 is chipping during dicing, 7 is a dicing width, 8 is a crack, and 9 is a crack propagation amount. As shown in FIG. 4, an interlayer oxide film 4 is present on the silicon substrate 1 in the dicing line 3 portion.
[0007]
[Problems to be solved by the invention]
The structure of the conventional dicing line portion is as described above. As shown in FIG. 4, the dicing line 3 has a structure having an interlayer oxide film 4 on the silicon substrate 1. Since the oxide film is glassy and very brittle, it has been difficult to prevent the generation of cracks 8 in the interlayer oxide film 4 by conventional crack prevention techniques for silicon. For this reason, a crack 8 is generated in the interlayer oxide film 4 during dicing, propagates to the passivation film 5, moisture enters the semiconductor device from the crack 8, and the moisture resistance of the semiconductor device is remarkably lowered. there were.
[0008]
As a solution to this, a method of sufficiently opening the dicing line 3 width, which is the pattern interval of the passivation film 5, can be considered. For example, in FIG. 4, the dicing width 7 is about 80 μm and the crack propagation amount 9 to the interlayer oxide film 4 is about 20 μm. Therefore, if the pattern interval of the passivation film 5 is 120 μm or more, the interlayer oxide film 4 It is possible to prevent the crack 8 generated in step 1 from being propagated to the passivation film 5 and the crack 8 from being generated in the passivation film 5. However, for this purpose, the width of the dicing line 3 must be 120 μm or more, and the number of semiconductor chips that can be formed on the semiconductor wafer is reduced.
[0009]
Japanese Laid-Open Patent Publication No. 2-188942 discloses that a dicing line has an interlayer insulating film and a moisture-resistant ring is formed on the interlayer insulating film, but the passivation film is formed to cover the moisture-resistant ring. Therefore, it is impossible to prevent the crack propagated through the interlayer insulating film from reaching the passivation film. Therefore, the interval between the passivation film patterns for determining the dicing line width must be increased by the amount of crack propagation, and again, there is a problem that the number of semiconductor chips that can be formed on the semiconductor wafer is reduced. It was.
[0010]
The present invention has been made to solve the above-described problems. In the case where an oxide film is provided in the dicing line portion, the present invention can reduce the number of chips formed on the semiconductor wafer without reducing the number of chips formed during dicing. aims at the provided dicing line structure can be prevented cracking propagation, to provide high-quality semiconductor silicon wafer and a semiconductor equipment which is excellent in mass productivity.
[0011]
[Means for Solving the Problems]
Semiconductor silicon wafer according to claim 1 of the present invention, the semiconductor silicon wafer and a dicing line located between the plurality of semiconductor chip regions and said plurality of semiconductor chip regions on a semiconductor substrate surface, the semiconductor chip area An interlayer insulating film, a tungsten plug, a wiring, and a passivation film are formed on the semiconductor substrate, and the dicing line is covered with an interlayer insulating film formed on the semiconductor substrate, and the semiconductor chip region and the dicing line are In the boundary region, a crack preventing film is formed on the interlayer insulating film, and further a passivation film is formed on the crack preventing film, and the interlayer insulating film is formed on the dicing line without forming the crack preventing film and the passivation film. Is exposed, and the anti-cracking film on the dicing line side in the boundary region Parts are to be located on the dicing line side than the end portion of the dicing line side of the passivation film, characterized by.
[0012]
A semiconductor silicon wafer according to a second aspect of the present invention is the semiconductor silicon wafer according to the first aspect, wherein the crack preventing film is made of aluminum containing Cu or Si .
[0013]
A semiconductor silicon wafer according to a third aspect of the present invention is the semiconductor silicon wafer according to the second aspect, wherein the crack preventing film extends along a dicing line.
[0014]
According to a fourth aspect of the present invention, there is provided the semiconductor silicon wafer according to the third aspect, wherein the crack preventing film is formed around the semiconductor chip region .
[0015]
A semiconductor silicon wafer according to a fifth aspect of the present invention is a semiconductor silicon wafer having a plurality of semiconductor chip regions and dicing lines located between the plurality of semiconductor chip regions on the surface of the semiconductor substrate. An interlayer insulating film, a tungsten plug, a wiring, and a passivation film are formed on the semiconductor substrate. The interlayer insulating film continuously extends from two adjacent semiconductor chip regions to the dicing line and covers the dicing line. In the boundary region between the semiconductor chip region and the dicing line, a crack prevention film having an end on the dicing line side is formed on the interlayer insulating film, and a passivation film extends from the semiconductor chip region on the crack prevention film. It has an end on the dicing line side and the dicing line is crack-proof. The interlayer insulating film is exposed without forming a film and a passivation film, and the distance between the end portions of the two crack prevention films located on both sides of the dicing line is the end of the two passivation films located on both sides of the dicing line. It is smaller than the interval of the parts.
[0016]
A semiconductor silicon wafer according to a sixth aspect of the present invention is the semiconductor silicon wafer according to the fifth aspect, wherein the crack preventing film is made of aluminum containing Cu or Si .
[0017]
A semiconductor silicon wafer according to a seventh aspect of the present invention is the semiconductor silicon wafer according to the sixth aspect, wherein the crack preventing film extends along a dicing line.
[0018]
According to an eighth aspect of the present invention, in the semiconductor silicon wafer according to the seventh aspect, the crack preventing film is formed around the semiconductor chip region.
[0019]
A semiconductor device according to a ninth aspect of the present invention is a semiconductor device formed on the surface of a semiconductor substrate and having a semiconductor chip region and a dicing line around the semiconductor chip region. The semiconductor chip region includes an interlayer insulating film on the semiconductor substrate, A tungsten plug, wiring, and a passivation film are formed, and the dicing line is covered with an interlayer insulating film formed on the semiconductor substrate, and on the interlayer insulating film in the boundary region between the semiconductor chip region and the dicing line. A crack prevention film is formed, and a passivation film is formed on the crack prevention film, and the interlayer insulating film is exposed on the dicing line without forming the crack prevention film and the passivation film. The end of the crack prevention film on the dicing line side is the passivation film dicing line. Than the end to be located to the dicing line side, characterized by.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1A is a plan view showing a semiconductor wafer on which a plurality of semiconductor chips of the present invention are formed, and FIG. 1B is a partially enlarged view of FIG. In the figure, 1 is a silicon substrate on which a semiconductor wafer is formed, 2 is a plurality of semiconductor chips formed on the silicon substrate 1, and the surface is a passivation film 5 as a protective film. Reference numeral 3 denotes a dicing line formed between the semiconductor chips 2. Reference numeral 10 denotes a metal ring pattern as a crack preventing film formed around the semiconductor chip 2. In FIG. .
[0021]
FIG. 2 is a cross-sectional view taken along the line BB ′ of FIG. In the figure, 4 is an interlayer oxide film formed on the silicon substrate 1, 5 is a passivation film, 6 is chipping during dicing, 7 is a dicing width, 8 is a crack, and 9 is a crack propagation amount. As shown in FIGS. 1B and 2, the metal annular pattern 10 uses aluminum containing Si or Cu, and can cover a region where cracks propagate during dicing (about 5 to 20 μm). Thus, it is formed around each semiconductor chip 2 so as to surround the semiconductor chip 2. At this time, the pattern edge of the passivation film 5 is located on the metal annular pattern 10. Aluminum can not only easily form the metal annular pattern 10 simultaneously with the formation of the element, but also can prevent the propagation of the crack 8 in such a manner as to absorb the crack 8 due to the malleability of the aluminum.
[0022]
If such a dicing line 3 structure is used, even if cracking 8 occurs from the chipping 6 portion and propagates through the interlayer oxide film 4 when dicing is performed, the crack 8 stops at the metal annular pattern 10 and reaches the passivation film 5. It does not propagate. Therefore, moisture can be prevented from entering the semiconductor device, and the moisture resistance of the semiconductor device can be improved.
[0023]
Further, the width of the dicing line 3 is determined by the interval between the metal annular patterns 10, and it is not necessary to form the passivation film 5 with a wider pattern interval. That is, since the dicing width 7 is about 80 μm including the dicing deviation width, the interval between the metal annular patterns 10 can be formed to a minimum of 80 μm. Further, even if the passivation film 5 is formed with a margin of about 5 μm so that the pattern edge of the passivation film 5 can be surely formed on the metal annular pattern 10, the pattern interval of the passivation film 5 can be formed to about 90 μm. Therefore, the number of semiconductor chips 2 that can be formed on the semiconductor wafer is not reduced, and the mass productivity is improved.
[0024]
【The invention's effect】
As described above, according to the present invention, in the semiconductor chip region, the interlayer insulating film, tungsten plug, wiring, and passivation film are formed on the semiconductor substrate, and the dicing line is formed on the interlayer insulating film formed on the semiconductor substrate. In the boundary region between the semiconductor chip region and the dicing line, a crack prevention film is formed on the interlayer insulating film, and a passivation film is further formed on the crack prevention film. The crack prevention film and passivation film are not formed and the interlayer insulating film is exposed, and the end of the crack prevention film on the dicing line side in the boundary region is closer to the dicing line side than the end of the passivation film on the dicing line side. Even if cracks occur during dicing, It is possible to prevent the propagation of cracks to the protective film without widening the width of the icing line, improve the moisture resistance of the semiconductor device without reducing the number of semiconductor chips, and to produce a high-quality semiconductor silicon wafer with excellent mass productivity There is an effect that can be obtained.
[0025]
According to the next invention, since the crack prevention film is made of aluminum containing Cu or Si , the crack prevention film can be easily manufactured at the same time as the element is formed. Therefore, there is an effect that the propagation of cracks can be surely prevented.
[0026]
Further, according to the next invention, since the crack preventing film extends along the dicing line, even if a crack occurs at the time of dicing, the crack to the protective film is not increased without increasing the width of the dicing line. Propagation can be prevented, the moisture resistance of the semiconductor device can be improved without reducing the number of semiconductor chips, and a high-quality semiconductor silicon wafer excellent in mass productivity can be obtained.
[0027]
Further, according to the next invention, since the crack preventing film is formed around the semiconductor chip region, even if a crack is generated during dicing, the crack preventing film is formed without increasing the width of the dicing line. The propagation of cracks can be prevented, the moisture resistance of the semiconductor device can be improved without reducing the number of semiconductor chips, and a high-quality semiconductor silicon wafer excellent in mass productivity can be obtained.
[0028]
According to the next invention, there is provided a semiconductor silicon wafer having a plurality of semiconductor chip regions and dicing lines positioned between the plurality of semiconductor chip regions on a semiconductor substrate surface, wherein the semiconductor chip region includes the semiconductor An interlayer insulating film, a tungsten plug, a wiring, and a passivation film are formed on the substrate, and the interlayer insulating film continuously extends from the two adjacent semiconductor chip regions to the dicing line so as to connect the dicing line. A crack preventing film having an end on the dicing line side is formed on the interlayer insulating film in a boundary region between the semiconductor chip region and the dicing line, and further on the crack preventing film, the crack preventing film is formed. extending passivation film from the semiconductor chip area, have the end portions in the dicing line side The crack prevention film and the passivation film are not formed on the dicing line, and the interlayer insulating film is exposed, and the distance between the ends of the two crack prevention films located on both sides of the dicing line is the dicing line. Propagation of cracks to the protective film without increasing the width of the dicing line even if cracks occur during dicing because the distance between the edges of the two passivation films located on both sides of the line is smaller than the distance between them. Thus, it is possible to improve the moisture resistance of the semiconductor device without reducing the number of semiconductor chips, and to obtain a high-quality semiconductor silicon wafer excellent in mass productivity.
[0029]
According to the next invention, since the crack prevention film is made of aluminum containing Cu or Si , the crack prevention film can be easily manufactured at the same time as the element is formed. Therefore, there is an effect that the propagation of cracks can be surely prevented.
[0030]
Further, according to the next invention, since the crack preventing film extends along the dicing line, even if a crack occurs during dicing, the crack to the protective film is not increased without increasing the width of the dicing line. Propagation can be prevented, the moisture resistance of the semiconductor device can be improved without reducing the number of semiconductor chips, and a high-quality semiconductor silicon wafer excellent in mass productivity can be obtained.
[0031]
Further, according to the next invention, since the crack preventing film is formed around the semiconductor chip region, even if a crack is generated during dicing, the crack preventing film is formed without increasing the width of the dicing line. The propagation of cracks can be prevented, the moisture resistance of the semiconductor device can be improved without reducing the number of semiconductor chips, and a high-quality semiconductor silicon wafer excellent in mass productivity can be obtained.
[0032]
According to the next invention, there is provided a semiconductor device formed on a semiconductor substrate surface and having a semiconductor chip region and a dicing line around the semiconductor chip region, wherein the semiconductor chip region has an interlayer insulating film, tungsten on the semiconductor substrate. A plug, a wiring, and a passivation film are formed, the dicing line is covered with an interlayer insulating film formed on the semiconductor substrate, and the interlayer is formed in a boundary region between the semiconductor chip region and the dicing line. A crack prevention film is formed on the insulating film, and further, the passivation film is formed on the crack prevention film, and the interlayer insulation film is formed on the dicing line without forming the crack prevention film and the passivation film. Is exposed and the dicing line of the crack prevention film in the boundary region Since the end portion of the passivation film is positioned closer to the dicing line side than the end portion of the passivation film on the dicing line side, even if a crack occurs during dicing, the protective film is not expanded without increasing the width of the dicing line. Propagation of cracks can be prevented, the moisture resistance of the semiconductor device can be improved without reducing the number of semiconductor chips, and a high-quality semiconductor device excellent in mass productivity can be obtained.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor wafer on which a plurality of semiconductor chips of the present invention are formed.
FIG. 2 is a cross-sectional view of FIG.
FIG. 3 is a plan view showing a semiconductor wafer on which a plurality of conventional semiconductor chips are formed.
4 is a cross-sectional view of FIG. 3. FIG.
[Explanation of symbols]
1 silicon substrate, 2 semiconductor chip, 3 dicing line, 4 interlayer oxide film, 5 passivation film, 8 crack, 10 metal ring pattern.

Claims (9)

A semiconductor silicon wafer having a plurality of semiconductor chip regions and dicing lines located between the plurality of semiconductor chip regions on the surface of the semiconductor substrate,
In the semiconductor chip region, an interlayer insulating film, a tungsten plug, a wiring, and a passivation film are formed on the semiconductor substrate.
The dicing line is covered with an interlayer insulating film formed on the semiconductor substrate,
In the boundary region between the semiconductor chip region and the dicing line, a crack prevention film is formed on the interlayer insulating film, and further, the passivation film is formed on the crack prevention film,
In the dicing line, the interlayer insulating film is exposed without forming the crack preventing film and the passivation film,
An end of the crack prevention film on the dicing line side in the boundary region is located on the dicing line side of an end of the passivation film on the dicing line side;
A semiconductor silicon wafer characterized by 2. The semiconductor silicon wafer according to claim 1, wherein the crack preventing film is made of aluminum containing Cu or Si .   The semiconductor silicon wafer according to claim 2, wherein the crack preventing film extends along the dicing line.   4. The semiconductor silicon wafer according to claim 3, wherein the crack preventing film is formed around the semiconductor chip region. A semiconductor silicon wafer having a plurality of semiconductor chip regions and dicing lines located between the plurality of semiconductor chip regions on the surface of the semiconductor substrate,
In the semiconductor chip region, an interlayer insulating film, a tungsten plug, a wiring, and a passivation film are formed on the semiconductor substrate.
The interlayer insulating film continuously extends from the two adjacent semiconductor chip regions to the dicing line and covers the dicing line,
In the boundary region between the semiconductor chip region and the dicing line,
A crack prevention film having an end on the dicing line side is formed on the interlayer insulating film, and the passivation film extends from the semiconductor chip region on the crack prevention film and ends on the dicing line side. Part
In the dicing line, the interlayer insulating film is exposed without forming the crack preventing film and the passivation film,
The interval between the end portions of the two crack prevention films located on both sides of the dicing line is smaller than the interval between the end portions of the two passivation films located on both sides of the dicing line,
A semiconductor silicon wafer characterized by 6. The semiconductor silicon wafer according to claim 5, wherein the crack preventing film is made of aluminum containing Cu or Si .   The semiconductor silicon wafer according to claim 6, wherein the crack preventing film extends along the dicing line.   8. The semiconductor silicon wafer according to claim 7, wherein the crack preventing film is formed around the semiconductor chip region. A semiconductor device formed on the surface of a semiconductor substrate and having a semiconductor chip region and a dicing line around it,
In the semiconductor chip region, an interlayer insulating film, a tungsten plug, a wiring, and a passivation film are formed on the semiconductor substrate.
The dicing line is covered with an interlayer insulating film formed on the semiconductor substrate,
In the boundary region between the semiconductor chip region and the dicing line, a crack prevention film is formed on the interlayer insulating film, and further, the passivation film is formed on the crack prevention film,
In the dicing line, the interlayer insulating film is exposed without forming the crack preventing film and the passivation film,
An end of the crack prevention film on the dicing line side in the boundary region is located on the dicing line side of an end of the passivation film on the dicing line side;
A semiconductor device characterized by the above.

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