JP3866586B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, for example, a nonvolatile semiconductor memory device using a nonvolatile memory cell in which a charge storage layer and a control gate are stacked.
[0002]
[Prior art]
In recent years, a nonvolatile semiconductor memory device (EEPROM) using a nonvolatile semiconductor memory cell in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film has attracted attention as a kind of semiconductor memory device. ing. In this EEPROM, memory cells are arranged in a matrix form by arranging memory cells at each intersection of a word line and a bit line. At this time, a word line is generally formed by a control gate, and a bit line is formed by contacting an Al wiring to the drain portion of each cell. However, various problems have arisen in the EEPROM in which memory cells are connected in a matrix, due to miniaturization.
[0003]
For example, a NAND cell type EEPROM will be described below as an example. A NAND cell type EEPROM is a NAND cell configured by connecting a plurality of memory cells in series, and the control gate of each memory cell is shared with the adjacent memory cell with element isolation in between, and the word line and It has become. In addition, a wiring is connected to the drain side of each NAND cell via a selection transistor, and this wiring is shared in a direction orthogonal to the word line to constitute a bit line. Further, the source side of each NAND cell is connected to a source line in a direction parallel to the word line via a selection transistor.
[0004]
Here, in a NAND cell array that forms a matrix, a contact portion (bit line contact portion) to the drain of each NAND cell is located directly beside a NAND cell adjacent in the word line direction. In the contact portion, it is necessary to provide a margin in anticipation of the PEP shift, and the diffusion layer region of the contact portion must be enlarged. For this reason, the diffusion layer region of the adjacent bit line contact portion is closer to the interval between adjacent bit lines, and the breakdown voltage between the adjacent NAND cells in the word line direction is limited by the breakdown voltage in this portion, and the word line direction However, there is a drawback that it is difficult to miniaturize the element isolation region.
[0005]
Such a problem also occurs in other semiconductor memory devices in which a plurality of memory cells are connected in series to form a memory cell unit, for example, a NAND DRAM cell. For example, regarding the bit line contact position of a NAND type DRAM cell, as shown in FIGS. 3, 13, and 14 of Japanese Patent Laid-Open No. 4-147490, conventionally, adjacent bit line contacts are arranged in the word line direction. It is arranged in parallel with.
[0006]
In the NAND cell type EEPROM, each NAND cell constitutes an array in such a manner that those belonging to the same column share a bit line and those belonging to the same row share a source line. At this time, in the conventional case, there is no element isolation region in the common source line portion, and the source diffusion layers of the source side selection transistors of the NAND cells belonging to the same row adjacent to each other are connected. The element isolation region is divided by the common source line.
[0007]
In such a configuration, the end of the element isolation region may be applied to the source-side selection transistor, which causes the breakdown voltage of the selection transistor to drop. FIG. 6 shows a conventional NAND cell array. When a bent portion of the common source line is bent as shown by a broken line in the drawing, this portion is applied to the source side select transistor. In order to prevent this, increasing the distance between the gates of the common source and the source side selection transistor leads to a decrease in the degree of integration.
[0008]
In addition, in the process of forming a resist pattern for forming an element isolation region, even when the phase shift method is used, there is a drawback that the phase shift method is difficult to use because the phase shifter is in an abnormal arrangement at the common source line. .
[0009]
[Problems to be solved by the invention]
As described above, in the conventional NAND cell type semiconductor memory device in which the array is arranged in a matrix, the withstand voltage between the memory cells is controlled by the adjacent bit line contact portion, thereby reducing the element isolation region between the memory cells. There is a problem that (word line direction) becomes difficult.
[0010]
In addition, the element isolation region separating the memory cells is interrupted at the common source line, and when the NAND cell is used, the end of the element isolation region may be applied to the source side select transistor, which is the withstand voltage of the select transistor. Was the cause of dropping.
[0011]
The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent a decrease in the reliability of memory cells due to a common source line, and to improve the degree of integration and the reliability. An object of the present invention is to provide a semiconductor memory device.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, the present invention adopts the following configuration.
[0013]
That is, according to the present invention, a nonvolatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor substrate, a plurality of the memory cells are connected in series, and the drain side is selected as the drain side of the series connection portion. In a semiconductor memory device in which a NAND cell unit having a gate and a source side select gate on the source side is arranged in a matrix, the drain of the drain side select gate of the NAND cell unit is connected to a bit line, and the source The source of the side selection gate is connected to a common connection line, and the common source line is arranged separately and in parallel with the gate wiring of the source side selection gate on the substrate to form an element over a plurality of NAND cell units. The region and the element isolation region are formed continuously without being separated by the common source line portion.
[0014]
Here, preferred embodiments of the present invention include the following.
[0015]
(1) The memory cell has a NAND cell structure in which a plurality of single cells are connected in series.
[0016]
(2) Memory cells must be placed at each intersection of word lines and bit lines.
[0017]
(3) The common source line is taken by polysilicon or Al wiring so that the element isolation region in the memory cell array continues without interruption by the common source line.
[0018]
(4) The element isolation region in the cell array must be formed so as to be orthogonal to the control gate or word line of the memory cell, regardless of the portion.
[0019]
(5) The memory cell may be a non-volatile memory cell or another memory cell such as a DRAM, particularly a NAND DRAM cell.
[0020]
[Action]
In the present invention, since the element isolation region in the array is not interrupted by the common source line, the end of the element isolation region may be applied to a part of the memory cell array (for example, the source side selection transistor in the NAND cell). Therefore, the device characteristics are not deteriorated (the breakdown voltage of the selection transistor is not deteriorated). Further, even in a resist pattern type process for forming an element isolation region, an abnormal arrangement of phase shifters due to interruption by a common source line does not appear, and the phase shift method is easy to use.
[0021]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0022]
(Reference example)
FIG. 1 is a plan view showing an array configuration of a NAND cell type EEPROM according to a reference example of the present invention. In the figure, 1 is a bit line, 2 is a bit line contact, 3 is a source line, 4 is a memory cell, 5 is a drain side select transistor, and 6 is a source side select transistor.
[0023]
In the memory cell 4, a floating gate (charge storage layer) FG made of p-type polysilicon is formed on a semiconductor substrate via a tunnel oxide film (for example, 10 nm), and a gate oxide film (for example, a film thickness of 20 nm) is formed thereon. A control gate CG made of polysilicon is formed therethrough. The control gate CG becomes a word line. Eight memory cells 4 are connected in series, and select transistors 5 and 6 are connected before and after that to form one NAND cell.
[0024]
Then, a contact (bit line contact) 2 is formed on the drain portion of the upper selection transistor 5 and an Al wiring is formed in a direction orthogonal to the word line. This is used as a bit line (BL) 1. The source portion of the lower selection transistor 6 is connected to the source line 3 in the direction parallel to the word line.
[0025]
Here, in this reference example, the bit line contacts 2 are not shifted in the word line direction but are alternately shifted in the bit line direction. By doing so, the distance between the contacts can be realized with a smaller element isolation region than that in the conventional case. For reference, FIG. 7 shows an array plan view of a conventional NAND type EEPROM. As shown in the figure, the bit line contacts 2 are arranged in the word line direction.
[0026]
Let us estimate the cell reduction when configured as in this reference example. First, the element isolation width is L1, the length of the NAND cell in the bit line direction is L2, and the cell width is L3. In the conventional NAND cell array, the area S1 of one NAND cell including the element isolation region is as shown in FIG.
S1 = (L1 + L3) × L2
It becomes. In the NAND cell array of this reference example, as shown in FIG.
S2 = (L1 cos θ + L3) × (L2 + L1 sin θ)
It becomes. Accordingly, if L1, L2, L3, and θ are, for example, L1 = 1.8 μm, L2 = 16 μm, L3 = 0.7 μm, and θ = 45 °, the difference in area between this reference example and the conventional example is
S1 -S2 = 40.0-34.0 = 6.0
Is reduced by 6.0 μm ² .
[0027]
In the above description, L1 in the conventional example is the length between adjacent bit lines, and L1 in the reference example is a length connecting between the contact centers of the adjacent bit lines. However, for more accurate estimation, L1 ′ in the conventional example is The length between adjacent bit line contacts, L1 ′ in the reference example, may be calculated as the shortest length between edges of adjacent bit line contacts.
[0028]
Example 1
FIG. 2 is a plan view showing the array configuration of the EEPROM according to the first embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.
[0029]
In this embodiment, the control gate CG and the selection gate SG are alternately bent in accordance with the bit line contacts 2 being alternately shifted. With this configuration, the distance from the bit line contact 2 to the selection gate SGD can be made equal in each NAND cell (the resistance from the contact to the selection transistor is equal), which is effective for uniform cell characteristics. It is.
[0030]
Further, in this embodiment, instead of using the common source line (diffusion layer) 3 as the source line, a source contact is provided to connect adjacent sources in the word line direction as will be described in an embodiment described later. Of course, the common source line 3 may also be provided as in the first embodiment.
[0031]
The layouts in the reference example and the first embodiment are also suitable for applying a self-alignment contact process. In the reference example and the first embodiment, the NAND cell is used. However, the present invention is not limited to this and can be applied to an EEPROM using a nonvolatile memory cell. The embodiment of the present invention can also be applied to the NAND type cell having the structure disclosed in Japanese Patent Laid-Open No. 4-147940 described in the above prior art.
[0032]
(Example 2)
FIG. 3 is a plan view showing an array configuration of a NAND cell type EEPROM according to the second embodiment of the present invention, and FIGS. 4 (a) and 4 (b) are cross sections taken along arrows AA 'and BB'. FIG. FIG. 5 is an equivalent circuit of a NAND cell.
[0033]
In this embodiment, four memory cells M1 to M4 are connected in series so that their adjacent source and drain diffusion layers are shared by each other to constitute a NAND cell. Such NAND cells are arranged in a matrix to form a NAND cell array.
[0034]
Drain side of one end of the NAND cell is connected to the bit line BL via a select gate SG _D, the source of the other end is connected to the polysilicon wiring, etc. Calalou common source line via select gates SG _S (ground line) Yes. The control gates CG _{1 to} CG ₄ of each memory cell are arranged in a direction crossing the bit line BL and become the word line WL.
[0035]
In this embodiment, one NAND cell is composed of four memory cells, but in general, one NAND cell can be composed of 2 n (n = 1, 2,...) Memory cells. it can.
[0036]
A specific memory cell structure is as shown in FIGS. A p-type well 11 ′ is formed in the n-type silicon substrate 11, and memory cells are arranged in the p-type well 11 ′. The peripheral circuit is formed in a p-type well different from the memory cell. Four memory cells and two select gates are formed in a region surrounded by the element isolation insulating film 12 of the p-type well 11 ′.
[0037]
Each memory cell is, p-type well 11 'made of a thermal oxide film 5~20nm on the first gate insulating film 13 ₁ float by the first-layer polycrystalline silicon of 50~400nm formed via a gate 14 (14 _{2 to} 14 ₅ ), and a control gate 16 (16 ₁ ) is formed by a second layer polycrystalline silicon of 100 to 400 nm formed thereon via a second gate insulating film 15 made of a thermal oxide film of 15 to 40 nm. ~ 16 ₅ ) are formed. The n-type layer 19 serving as the source and drain diffusion layers of each memory cell is shared by adjacent ones, and four memory cells are connected in series.
[0038]
The source end of the NAND cell, selecting that with the p-type well 11 'gate insulating film 13 _{and second} gate electrode 141 formed by the first-layer polycrystalline silicon via made of a thermal oxide film 5~40nm on A selection gate (SG _S ) having a gate (SG _D ) and a gate electrode 14 ₆ is formed. Here, the gate insulating film 13 ₂ may be the same as the first gate insulating film 13 ₁ . On the gate electrodes 14 ₁ and 14 ₆ , wirings 16 ₁ and 16 ₆ made of second polycrystalline silicon are disposed so as to overlap each other. The gate electrode 14 ₁ and the wirings 16 ₁ and 14 ₆ and 16 ₆ are connected by through holes at predetermined intervals to reduce the resistance.
[0039]
Here, the floating gates 14 _{2 to} 14 ₅ and the control gates 16 _{2 to} 16 _{5 of} each memory cell, the gate electrodes 14 ₁ and 14 _{6 of} the selection gates, and the wirings 16 ₁ and 16 ₆ are etched in the channel length direction. They are aligned by patterning using a mask. The n-type layer 19 serving as a source / drain diffusion layer is formed by ion implantation of arsenic or phosphorus using these electrodes as a mask.
[0040]
The substrate on which the element is formed is covered with a CVD insulating film 17, on which a common source line 20 is formed by third-layer polycrystalline silicon, and is connected to the source diffusion layer by a contact hole 21. Further, this is covered with a CVD insulating film 17 ', and a bit line 18 is provided thereon with an Al film.
[0041]
The operation of the NAND cell array configured in this way is exactly the same as the conventional one. However, in the structure of this embodiment, the reliability of the source side selection gate can be improved as compared with the conventional case.
[0042]
In the conventional case, as shown in FIG. 6, the element isolation region separating the NAND cells by the common source line is divided. The part where the element isolation region is cut off by the common source line is rounded as shown by a broken line in the actual case, and this rounded part is applied to the source side selection gate, thereby degrading the breakdown voltage. This tendency becomes more prominent as the element is miniaturized and the distance from the source side selection gate to the common source line is reduced.
[0043]
On the other hand, in the case of the present embodiment, since the element isolation region is not divided by the common source line 20, the above problem does not occur, and the breakdown voltage of the source side selection gate is improved compared to the conventional one. In this embodiment, since the element isolation region is continuous without being divided, a resist pattern for forming the element isolation region can be formed in a pattern close to a line and space. For this reason, the phase shift method can be used effectively, and the pattern accuracy can be improved.
[0044]
In this embodiment, the third polycrystalline silicon line is used as the common source line, but this may be a second layer Al line or the like, or a first layer Al wiring by changing the material of the bit line. . In the embodiment, the NAND cell is used. However, the present invention is not limited to this, and the present invention can be applied to an EEPROM using a nonvolatile memory cell.
[0045]
【The invention's effect】
As described above in detail, according to the present invention, the element isolation region is continuously formed across the plurality of nonvolatile memory cells without being divided by the common source line. Thus, a highly reliable NAND cell type EEPROM can be realized. In addition, the phase shift method is easy to use, and higher integration becomes easier.
[Brief description of the drawings]
FIG. 1 is a plan view showing an array configuration of an EEPROM according to a reference example of the present invention.
FIG. 2 is a plan view showing an array configuration of an EEPROM according to the first embodiment;
FIG. 3 is a plan view showing an array configuration of an EEPROM according to a second embodiment;
4 is a cross-sectional view taken along arrows AA ′ and BB ′ of the NAND cell in FIG. 3;
FIG. 5 is an equivalent circuit diagram of the NAND cell of FIG. 3;
FIG. 6 is a plan view showing an array configuration of a conventional NAND cell.
FIG. 7 is a plan view showing an array configuration of a conventional NAND cell.
[Explanation of symbols]
1 ... Bit line (BL)
2 ... bit line contact 3 ... source line 4 ... memory cell 5 ... drain side select transistor 6 ... source-side selection transistor CG (CG ₁ ~CG ₈₎ ... control gate FG ... floating gate (charge storage layer)
SG (SG _D , SG _S ) ... selection gate

Claims (1)

A nonvolatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor substrate, a plurality of the memory cells are connected in series , a drain side selection gate is provided on the drain side of the series connection portion , and the source side In a semiconductor memory device in which NAND cell units provided with source-side selection gates are arranged in a matrix,
The side opposite to the series connection part of the drain side selection gate is connected to a bit line, and the side opposite to the series connection part of the source side selection gate is connected to a common source line,
The common source line is arranged separately and in parallel with the gate wiring of the source side selection gate on the substrate,
A semiconductor memory device, wherein an element formation region and an element isolation region are formed continuously without being separated by a common source line portion over a plurality of NAND cell units.

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