JP3867911B2 - State transition type communication processing apparatus and processing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a state transition processing apparatus and method used for complicated processing such as communication protocol processing in a communication processing apparatus.
[0002]
[Prior art]
A terminal interface in data communication includes, for example, a V series interface for analog data transmission called a modem interface (CCITT standard).
[0003]
A plurality of communication methods are recommended in the V series recommendation. For example, V. 21, V.R. 22, V.R. 22bis, V.M. 32, V.I. 32bis, V.M. 34, V.I. 90, V.I. 92 and the like. These communication methods are devised so that the communication methods can be determined between terminals at the time of connection, but the determination method requires a complicated and complicated procedure. While performing modulation / demodulation signal processing such as FSK, BPSK, and QAM, tone detection signal processing, and the like in parallel or switching, data necessary for establishing connection with the other modem is transferred and the communication method is determined.
[0004]
These communication processing programs are configured by a sequence processing program that performs the above-described complicated connection processing in addition to various signal processing programs such as modulation / demodulation processing. Supporting the communication method increases the capacity of the sequence processing program.
In addition, this sequence processing is the most important for connectivity with the partner modem. When a problem occurs in the sequence, the timing and the like are readjusted, and the program must be changed.
[0005]
In recent years, semiconductor miniaturization has progressed, and large-scale system LSIs can be manufactured. Therefore, it is possible to mount a large capacity RAM / ROM in the communication processing LSI.
However, considering the cost, it is necessary to design the LSI as small as possible. Therefore, it is necessary to make the built-in memory as small as possible.
In the case of the built-in ROM, since the program cannot be changed, the LSI mask must be revised each time the program is modified, resulting in an increase in cost.
Usually, a communication processing LSI is realized by a high-speed CPU or DSP (digital signal processor) mainly for signal processing, and if a ROM or RAM is arranged outside, the bus speed is not in time. Therefore, the LSI size cannot be reduced by arranging the memory outside.
[0006]
In order to avoid the mask revision and facilitate the program revision, a rewritable ROM such as an embedded flash ROM can be used as the built-in ROM. However, there are many cases where the cost is increased as compared with Mask ROM. A method of installing a program externally, downloading the program to the internal RAM at the time of initialization, and executing the program using the internal RAM is conceivable. However, a large-capacity program size RAM is provided inside the LSI. This also increases the cost.
[0007]
As described above, how to handle the program memory in configuring the communication processing LSI is a very important factor in terms of cost and code revision, and the program that can be changed externally with the internal memory as small as possible Arranging the memory is an important issue.
[0008]
As a conventional method for solving the above problem in the protocol processing of the communication processing apparatus, the technique of Japanese Patent Laid-Open No. 05-048669 is the only countermeasure for the above problem.
However, in this method, since the program is switched for each communication method, the memory cannot be reduced sufficiently.
Further, adaptation is difficult when the communication method is determined during the connection sequence as in the V series.
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 05-048669
[Problems to be solved by the invention]
In order to solve these problems, the object of the present invention is to transfer only the modules required for each state of communication processing to the internal RAM and operate them, so that the state transition type can be flexibly changed at low cost. It is to realize a communication processing apparatus and method.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the state transition type communication processing device according to the present invention has a large capacity so that the program size loaded in the internal RAM is limited to only modules related to each state in the entire sequence. The communication processing program is arranged outside, and a sequence-related program is arranged using a changeable memory as an external memory.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The principles and embodiments of the present invention will be described below with reference to the drawings.
[0013]
(principle)
In the connection with the other communication device, the process of determining one of a plurality of communication protocols during the connection sequence is standardized by controlling the operation or stop of tone detection, various modulation / demodulation processes and related functions. This is a process of transmitting / receiving a signal to / from the other communication device at the same timing. At this time, there are various states in the connection process, and the sequence program controls this state transition, but the state transition process also includes reconnection, speed reset, power It is applied by various controls such as detection.
[0014]
One method for programming these state transitions is to use a state transition table.
[0015]
FIG. 1 is an example of a state transition model. In this way, entry processing, exit processing, normal processing, event processing, and action processing managed by module numbers are defined for each state.
[0016]
The state transition table lists the processing contents for each state. Here, the entrance process is a process performed when entering the next state, the exit process is a process performed when exiting from the current state, and the normal process is a normal process every time the state does not change. The process to be executed and the event process are processes to check whether the transition condition is satisfied, and the action process is a process to be processed when the state transitions. The sequence processing executes processing of each state listed in the state transition table at a predefined time interval such as a symbol frequency unit.
[0017]
Normally, all of this processing, including the table, is stored in ROM, but in the present invention, all modules called from the state transition table and the state transition table are stored in the external memory, and only the modules related to the state transition table and the initial state at startup DMA transfer to the internal RAM and the state transition processing program is executed on the RAM. Each time the state transitions to the next state due to the occurrence of an event, only the module accessed in the next state is DMA-transferred to the internal RAM, and the state transition processing program is executed on the RAM.
[0018]
As described above, since only the modules related to the state at a certain point in time are transferred to the internal RAM, a huge system can be realized only by mounting a small amount of memory inside.
Since the program size to be downloaded at one time can be reduced, if DMA transfer is used, the state transition process is processed at a sufficient time interval such as a symbol cycle, so the transfer to the internal RAM is completed before the next state process starts. Therefore, the CPU or DSP processing time required for the main signal processing can be saved.
[0019]
If such a method is used, a large-capacity communication processing program can be arranged in the external memory. As a result, it is possible to reduce the internal memory of the communication processing LSI, and it is possible to flexibly cope with program changes by using a memory that can be changed as an external memory.
Therefore, it is possible to realize a communication processing device that can be changed in program flexibly at a low cost.
[0020]
(Example)
FIG. 4 is a diagram showing a configuration example of a communication processing apparatus according to the present invention.
The communication processing apparatus includes terminal I / Fs 404 and 411, a public line I / F 412, a one-chip communication processing LSI 403, and a memory such as a flash ROM. An internal RAM 409, an internal ROM 410, and an external ROM 408 are connected to the system bus of the one-chip communication processing LSI 403. Note that 401 is a terminal, 402 is a communication processing device, 405 and 407 are I / Os, and 406 is a DSP.
[0021]
The internal RAM 409 stores work memory, and the internal ROM 410 stores program modules such as signal processing. The external ROM 408 stores a state transition table, a sequence processing program module, and the like.
The state transition table is configured as shown in FIG. 3 with respect to the state transition model modeled as shown in FIG.
[0022]
First, as an initialization process at the time of system startup, the state transition table is transferred from the external memory 408 to the internal RAM 409. If the initial state is state ID = 1, the entrance process 1 with the state ID = 1 is transferred to the internal RAM 409, and the entrance process 1 is executed after the transfer. Further, the module related to the sequence initial state (ID = 1) is transferred to the internal RAM 409.
[0023]
The modules to be transferred are the normal process 1 and the exit process 1 with the state ID = 1. Further, in the case of the state ID = 1 in the example, since there is one transition condition, event processing 1 and action processing 1 of the module related to the transition. Then, the entrance process 2 with the state ID = 2 as the transition destination is transferred to the internal RAM 409.
[0024]
Thereafter, the sequence processing is performed at a preset time interval. As the set time, a symbol time or several sample times for A / D acquisition may be set. For example, when the sampling frequency is 8 kHz, signal processing such as modulation / demodulation is performed at intervals of 125 μsec. However, since the sequence processing does not need to be performed so frequently, a unit of several msec is sufficient.
[0025]
FIG. 2 is a process diagram in the state transition according to the present invention.
After the initialization processing, at the first sequence processing timing, event processing 1 in state 1 is first processed as shown in FIG. Therefore, when the transition conditions do not match, the normal process 1 is processed, and the sequence process waits until the next sequence process timing. Thereafter, the above processing is repeated at each sequence processing timing.
[0026]
FIG. 3 is a state transition table according to the present invention.
Hereinafter, a description will be given with reference to FIG. Next, as shown in FIG. 3, when the transition conditions match in event processing 1, action processing 1 and exit processing 1 are performed as shown in FIG. 2, and finally entrance processing 2 is executed. Then, the related module used in the next transition state (ID = 2 in the example) is expanded in the internal RAM 409. In the case of the example, the normal process 2, the exit process 2, the event process 2-1, the event process 2-2, the action process 2-1, the action process 2-2, and the entrance process 3 with the state ID = 3 as the transition destination It becomes entrance processing 1 of state ID = 1.
[0027]
Thereafter, the above process is repeated.
[0028]
Thus, since the program size loaded into the internal RAM 409 is limited to only the modules related to each state among all the sequence modules, it can be realized with a small memory consumption, and the sequence related program is stored in the external memory. By arranging these, it is possible to realize a system that can flexibly cope with program changes.
[0029]
In addition, when a module is downloaded from an external memory to the internal memory, if program transfer is performed at once by a data read / write operation by the CPU (or DSP), it is necessary to wait for signal processing such as modulation / demodulation processing until the end of the transfer. DMA control is used for program transfer.
[0030]
By performing background transfer, modulation / demodulation signal processing can be performed at A / D sampling intervals throughout the memory transfer processing.
[0031]
At this time, since the modules to be transferred are not arranged in a continuous address space, it is necessary to process the DMA transfer for each module. Completing all DMA transfers in the background poses a problem, but this problem can be solved by providing a DMA transfer end interrupt function. If the DMA transfer is started for each module in the interrupt process, the CPU load for the modulation / demodulation process is not caused.
[0032]
Further, since the module is transferred from the external memory to the internal RAM 409, the execution module address cannot be determined at the time of program search.
[0033]
It is necessary to use the module storage address for transfer and the module execution address for execution separately, and furthermore, since the address of the module developed in the internal RAM 409 cannot be determined at the time of program link, there is a method for dynamically determining the module execution address. Necessary.
[0034]
FIG. 5 is an example of a memory transfer module address table for module numbers.
In order to solve this problem, at the time of linking, linking is performed with the module address arranged in the external memory. At the time of linking, a memory transfer module address table for the module number (Number) is created as shown in FIG. At the time of module transfer, the module address (Address) is obtained from the module number (Number) stored in the state transition table and the module address table for memory transfer, and DMA transfer is performed from the address (Address) by the module size in the table.
[0035]
FIG. 6 is an example of an execution module address table.
Then, after DMA transfer, an execution module address (Address) table in which the module number (Number) and the transferred module address (Address) as shown in FIG. 6 are stored in the internal RAM 409 is generated. Use the executed execution module address table. In this way, the module address (Address) for the module number (Number) can be determined by the static address (Address) at the time of transfer and the dynamic address (Address) at the time of execution.
[0036]
【The invention's effect】
As described above in detail, according to the present invention, the sequence program necessary for each protocol is stored in a memory provided outside the LSI that performs the communication device, and the processing part is commonly used in all communication protocols. Is stored in a ROM connected to a CPU bus in the LSI, and only a sequence program necessary when a certain communication protocol is in a certain state is transferred from the external memory to the RAM in the LSI. Since the program to be transferred is small, the transfer processing time is short and the transfer destination internal RAM memory size can be reduced.
[Brief description of the drawings]
FIG. 1 is a model diagram of a state transition according to the present invention.
FIG. 2 is a process diagram in a state transition according to the present invention.
FIG. 3 is a state transition table according to the present invention.
FIG. 4 is a configuration example diagram of a communication processing apparatus according to the present invention.
FIG. 5 is an example of a module address table for memory transfer with respect to a module number.
FIG. 6 is an example of an execution module address table.
[Explanation of symbols]
401 Terminal 402 Communication Processing Device 403 Communication Processing LSI
404, 411 Line I / F
412 Public line 405, 407 I / O
406 DSP
408, 410 ROM
409 RAM

Claims (4)

A terminal interface for sending and receiving data to and from the terminal;
A line interface for connecting to a public telephone line and performing data communication with a partner communication device via the telephone line;
A state transition table stored in the external memory at the time of startup and an internal RAM to which only modules related to the initial state are transferred ;
When the transfer to the internal RAM is performed, a microprocessor that executes a communication program and determines during a connection sequence with one partner communication device among a plurality of communication protocols;
The microprocessor coupled to a read only memory and random access memory connected to the system bus was integrated on a single chip, perform direct memory access control for data transfer from the external memory to the internal RAM An LSI having DMA control means;
A state transition type communication processing apparatus comprising: a ROM storing a communication processing program connected to the LSI. The microprocessor of the programs, the sequence processor to an external memory, the other processing unit in the LSI ROM, stores respectively,
At the start of the program, the microprocessor makes a state transition that lists the program module number of each process of the state entry process, steady process, exit process, and multiple transition processes for each state managed by the state transition number Transferring the table from the external memory to the internal RAM;
Using the state transition table , sequence processing is performed with a time interval such as a symbol timing of modulation / demodulation as a trigger,
When the transition condition matches , it operates to transition to the next transition destination,
To degrees every time a state transition, after the entry process of the next state, the normal processing of the next state, exit processing, download all relevant modules of the plurality of transition process from the external memory to the internal RAM, and program A state transition type communication processing method, characterized by: In the state transition type communication processing method according to claim 2,
The microprocessor to have a DMA transfer end interrupt function, when downloading the module to the internal RAM from the external memory, performs signal processing such as modulation and demodulation processing,
State-transition-type communication characterized in that by performing background processing using DMA transfer for each module, the transfer is completed by the next sequence processing timing without stopping the modulation / demodulation processing during the memory transfer processing Processing method. In the state transition type communication processing method according to claim 2,
The microprocessor, to the module number to be used in the state transition table, that module storage address and the module size is have a memory transfer module address table stored, after transferring the module to the internal RAM, and modules Generate an execution module address table in which the number and transfer destination module execution address are stored in the internal RAM,
At the time of memory transfer and the module executes, it switches the 該Te Buru, stateful communication processing method characterized by dynamically changing the module address.

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