JP3870575B2 - Delta-sigma modulation apparatus and method, and digital signal processing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a delta-sigma modulation apparatus and method for obtaining a 1-bit digital signal by performing delta-sigma (ΔΣ) modulation processing on a multi-bit digital signal, and a digital signal processing apparatus.
[0002]
[Prior art]
The ΔΣ modulated high-speed 1-bit audio signal has a very high sampling frequency and a short data word compared to the data format used in conventional digital audio (for example, sampling frequency 44.1 kHz, data word length 16 bits). It has a long length (for example, sampling frequency is 64 times 44.1 kHz and data word length is 1 bit), and features a wide transmittable frequency band. Also, even with a 1-bit signal by ΔΣ modulation, a high dynamic range can be ensured in an audio band that is low with respect to an oversampling frequency of 64 times. This feature can be applied to high-quality recorders and data transmission.
[0003]
The ΔΣ modulation circuit itself is not a particularly new technology, and its circuit configuration is suitable for IC integration, and AD conversion accuracy can be obtained relatively easily. It is.
[0004]
The ΔΣ-modulated signal can be converted back to an analog audio signal by passing it through a simple analog low-pass filter.
[0005]
By the way, if any signal processing is performed on a 1-bit signal that has been ΔΣ-modulated, the bit length of the signal is expanded in the process, so that the bit-extended signal is re-quantized to 1 bit again by the ΔΣ modulator. There is a need to.
[0006]
Here, as a ΔΣ modulator for performing requantization, a ΔΣ modulator having a local feedback loop is often used in order to obtain a characteristic in which the quantization noise level in the audible band is suppressed.
[0007]
[Problems to be solved by the invention]
However, when the local feedback loop is used, the word length of the data is expanded by the arithmetic processing in the loop, and the word length is expanded infinitely by the loop. For this reason, when this processing is performed by a finite word length accumulator, data truncation occurs due to digit loss.
[0008]
The present invention has been made in view of the above circumstances, and a delta-sigma modulation device that modulates a multi-mbit digital signal into a 1-bit digital signal while suppressing signal degradation caused by data truncation in a local feedback loop, and It is an object to provide a method and a digital signal processing apparatus.
[0009]
In order to solve the above-described problem, a delta-sigma modulation apparatus according to the present invention is a delta-sigma modulation apparatus that modulates a plurality of m-bit digital signals into a 1-bit digital signal. Attenuating means for attenuating the integrated output of a predetermined number of integrating means, and a noise shaper for requantizing the attenuated output from the attenuating means and feeding back to the integrating means before the predetermined number of integrating means And local feedback loop means.
[0010]
Here, the local feedback loop means feeds back the output of the second and subsequent integrating means among the plurality of n integrating means to the preceding integrating means. The local feedback loop means includes local attenuation means and noise shaping means.
[0011]
Further, the delta-sigma modulation apparatus according to the present invention includes an m-bit digital signal in each integration means in front of the plurality of n integration means and the local feedback loop means. A computing means for inputting a signal; (n-1) attenuating means connected to each of the first to (n-1) -th integrating means of the plurality of n integrating means; 1-bit quantization means connected to the n-th integration means of the integration means, and the bit length of the 1-bit digital signal from the 1-bit quantization means is converted to m bits, and the input of each integration means Bit length converting means for supplying to the calculating means.
[0012]
In order to solve the above problem, a delta sigma modulation method according to the present invention is a delta sigma modulation method executed by a delta sigma modulation apparatus that modulates a plurality of m-bit digital signals into one-bit digital signals. Attenuation step for attenuating the integral output of the predetermined integration means among the integration means, and noise returning to the integration means before the predetermined integration means by requantizing the attenuation output from the attenuation step And a local feedback loop process having a shaper process.
[0013]
Therefore, according to the above-described delta-sigma modulation apparatus and method, there is no data truncation process by requantizing the extension of the data length generated by one round of the local feedback loop using a noise shaper in the loop. Implements ΔΣ modulation processing.
[0014]
In order to solve the above-described problem, a digital signal processing apparatus according to the present invention performs a predetermined operation on a 1-bit digital signal obtained by delta-sigma modulation, and obtains an m-bit operation processing signal. Delta-sigma modulation means for obtaining a 1-bit digital signal by subjecting the arithmetic processing signal from the arithmetic processing means to re-delta sigma modulation processing. The delta-sigma modulation means includes a plurality of n integration means and a plurality of n pieces of integration means. An attenuating means for attenuating the integral output of a predetermined number of integrating means, and a noise shaper for requantizing the attenuated output from the attenuating means and feeding back to the integrating means prior to the predetermined number of integrating means; And local feedback loop means.
[0015]
For this reason, various high-quality digital signal processing can be performed on a 1-bit signal that is ΔΣ-modulated.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment is an example of a 1-bit signal processing apparatus for a high-speed 1-bit audio signal modulated by delta-sigma (ΔΣ).
[0017]
As shown in FIG. 1, the 1-bit signal processing device 1 includes an arithmetic processing device 3 and a ΔΣ modulation device 5. A multiplier 4 is provided inside the arithmetic processing unit 3 and performs some level change processing such as fade processing by multiplying the 1-bit signal by a predetermined coefficient from a coefficient generator (not shown). Can do. At this time, the 1-bit digital signal is bit-extended to m bits. The signal expanded to m bits is re-modulated again to the original 1-bit signal by the ΔΣ modulator 5. Therefore, the ΔΣ modulation device 5 used here greatly affects the sound quality of the output signal from the 1-bit signal processing device 1.
[0018]
The 1-bit signal supplied from the input terminal 2 to the 1-bit signal processing device 1 is generated by the ΔΣ modulator shown in FIG. In FIG. 2, the input audio signal from the input terminal 7 is supplied to the integrator 9 through the adder 8. The signal from the integrator 9 is supplied to the comparator 10 where it is compared with the midpoint potential of the input audio signal and quantized by 1 bit every sample period. The frequency of the sampling period (sampling frequency) is 64 times or 128 times that of the conventional 48 kHz and 44.1 kHz. The quantized data is supplied to the one-sample delay unit 12 and delayed by one sample period. This delay data is converted into an analog signal by a 1-bit D / A converter 13, for example, supplied to an adder 8, and added to an input audio signal from the input terminal 7. Then, the quantized data is taken out from the comparator 10 through the output terminal 11.
[0019]
FIG. 3 shows a first specific example of the ΔΣ modulator 5. A first specific example of the ΔΣ modulation device 5 is a third-order ΔΣ modulation device including three integrators 23, 28 and 33. Further, the ΔΣ modulation device 5 includes a local feedback loop unit 44 that attenuates the outputs of the three integrators 23, 28, and 33, re-quantizes them, and feeds them back to the input of the previous integrator. In particular, the local feedback loop unit 44 feeds back the output of the third integrator 33 among the three integrators 23, 28 and 33 to the input of the second integrator 28. The local feedback loop unit 44 includes a local feedback attenuator 38 and a noise shaper 39.
[0020]
Further, the delta sigma modulation device 5 includes an adder 22 serving as a calculation means for inputting an m-bit digital signal to each of the integrators 23, 28 and 33 before the three integrators 23, 28 and 33. , 27 and 32, two attenuators 26 and 31 connected respectively after the first and second integrators 28 and 33 of the three integrators, and of the three integrators, The 1-bit quantizer 36 connected to the third integrator, and the bit length of the 1-bit digital signal from the 1-bit quantizer 36 are converted to m bits, and the integrators 23, 28 and 33 A bit length converter 37 that is supplied to the adders 22, 27, and 32 so as to be input is provided.
[0021]
The first integrator 23 integrates the m-bit digital signal supplied via the input terminal 21 and the adder 22. For this reason, the addition output from the adder 24 is shifted by the shift calculator 25 and returned to the adder 24.
[0022]
Similarly, the second integrator 28 has a configuration in which the addition output from the adder 29 is shifted by the shift calculator 30 and returned to the adder 29. The third integrator 33 is also configured to shift the addition output from the adder 34 by the shift calculator 35 and return it to the adder 34.
[0023]
The integrated output from the third integrator 33 is supplied to the 1-bit quantizer 36 and the local feedback attenuator 38 of the local feedback loop unit 44. The 1-bit quantizer 36 performs 1-bit quantization on the integrated output, derives it from the output terminal 6, and supplies it to the bit length converter 37.
[0024]
The bit length converter 37 converts the 1-bit signal from the 1-bit quantizer 36 into an m-bit digital signal, adds a negative sign to each of the adders 22, 27 and 32, and feeds back. Accordingly, each adder 22, 27, and 32 is a conversion output of the bit length converter 37 from the m-bit digital signal supplied from the input terminal 21 or the integrators 23 and 28 in the previous stage through the attenuators 26 and 31. A certain m-bit signal is subtracted.
[0025]
The attenuators 26 and 31 attenuate the integrated outputs of the first integrator 23 and the second integrator 28 and supply them to the adder 27 and the adder 32.
[0026]
The local feedback attenuator 38 of the local feedback loop unit 44 attenuates the integrated output from the third integrator 33 and supplies it to the noise shaper 39.
[0027]
The noise shaper 39 includes an adder 40, a shift calculator 41, an adder 42, and a multi-bit quantizer 43, and the attenuation output from the local feedback attenuator 38 is generated without truncating the data word length. Requantize. Specifically, the requantization error is shifted out of the audible band.
[0028]
Since the ΔΣ modulator 5 includes the noise shaper 39 in the local feedback loop unit 44, a high-quality 1-bit audio signal can be output without generating a data word length truncation step. Also, the 1-bit signal processing apparatus 1 can realize various kinds of signal processing with high sound quality.
[0029]
Hereinafter, the detailed operation of the ΔΣ modulation device 5 will be described. Here, the description will proceed while clarifying the difference as compared with the conventional ΔΣ modulation device. As a conventional ΔΣ modulator, there can be mentioned a ΔΣ modulator 50 shown in FIG. 4 and a ΔΣ modulator 51 shown in FIG.
[0030]
The ΔΣ modulation device 50 in FIG. 4 has a configuration in which the local feedback loop unit 44 is removed from the ΔΣ modulation device 5 shown in FIG. That is, if the local feedback loop unit 44 is removed from the ΔΣ modulator 5, the ΔΣ modulator 50 is obtained.
[0031]
FIG. 5 shows the operation word lengths at points a, b, and c in FIG. 4 in the ΔΣ modulation apparatus 50 over time. The word length at point a is increased in the carry direction because the input signal (m-bit digital signal) is accumulated in the first integrator 23. Since the feedback signal has the same word length as the input signal, the extension of the word length by the accumulation of the feedback signal is an extension in the carry direction as in the input signal, and does not diverge in the carry direction due to negative feedback.
[0032]
As for the word length at the point b, since the signal obtained by multiplying the signal at the point a by the coefficient K1 (1>k> 0) by the attenuator 26 is accumulated, the word length increases in the direction of carry-down. Similarly, since the coefficient K2 is multiplied by the attenuator 31 at the point c, the word length is further expanded in the direction of carry-down. The data with the expanded operation word length is converted to 1 bit by the 1-bit quantizer 36. Since the quantization error component here is fed back and noise-shaped, the data word length No truncation occurs.
[0033]
Next, the delta-sigma modulation device 51 shown in FIG. 6 has a configuration in which the noise shaper 39 is removed from the local feedback loop unit 44 of the delta-sigma modulation device 5 shown in FIG.
[0034]
FIG. 7 shows the operation word lengths at points a, b, and c in the ΔΣ modulator 51 as time elapses. The word length at each point a, b (1), c (1) in FIG. 7 is the same as in FIG. Here, the numbers in parentheses indicate the time course at each point. When the word length at the point c (1) passes through the local feedback loop section, the word length further increases in the direction of carry-down because the coefficient Kf is multiplied by the local feedback attenuator 52. This signal is fed back to the b (2) point as it is, and is accumulated in the opposite phase, so that the word length at the point b (1) is expanded to the word length at the point b (2). At the point c (2), the word length is further expanded in the direction of the carry by the coefficient K2, and the word length is b (3), c (3), b (4) in order to continue the circulation by the local feedback loop thereafter. . . . And expand infinitely.
[0035]
In the delta-sigma modulation device 51 including the local feedback loop unit including the local feedback attenuator 52, the quantization error component within the audible band is not provided as shown in FIG. 8B. Since the quantization error component shown in FIG. 8 (a) can be suppressed to a lower level, a device having this configuration is generally used as a ΔΣ modulator. However, by having this local feedback loop, as described with reference to FIG. 7, the word length is extended in the direction of carry-down.
[0036]
Actually, since the registers in the integrator are limited, the data word length is always rounded down to make the data length constant somewhere. Due to the truncation of the data word length, the ΔΣ modulator 51 having a local feedback loop has been accompanied by deterioration in sound quality.
[0037]
On the other hand, in the delta-sigma modulation device 5 shown in FIG. 3, as described above, the noise shaper 39 is provided in the local feedback loop unit 44, and the word length expanded by one round of the loop is sequentially noise-shaped. This realizes ΔΣ modulation without the data truncation process.
[0038]
FIG. 9 shows the time lapse of the operation word length at points a, b, and c in FIG. The word lengths at points a, b (1), and c (1) are the same as those shown in FIG. Since the local feedback attenuator 38 multiplies the word length at the point d (1) in the local feedback loop unit 44 by the coefficient Kf, the word length is expanded in the direction of carry-down from c (1). Here, in the delta-sigma modulation device 51 shown in FIG. 6, this value is fed back as it is and accumulated in the second integrator 28, so that the word length at the point b has been expanded. Therefore, in the delta-sigma modulation device 5 in FIG. 3, the extension of the operation word length caused by the multiplication coefficients K2 and Kf of the second attenuator 31 and the local feedback attenuator 38 existing in the feedback loop section is regenerated by the noise shaper 39 beforehand. After the quantization process, the phase is fed back and accumulated in the second integrator 28. As a result, the word length at the point b (2) does not change from the word length at the point b (1), and the word length extension in the direction of carry-down does not occur at the subsequent points b and c. Keep the word length. Therefore, ΔΣ modulation that does not cause data truncation can be performed in the middle of calculation, and ΔΣ modulation that suppresses the influence on sound quality caused by data truncation is possible.
[0039]
As described above, by using the ΔΣ modulation device shown in FIG. 3 as the ΔΣ modulation device 5 inside the 1-bit arithmetic processing device 1 in FIG. 1, various signal processing can be performed on a high-quality high-speed 1-bit audio signal.
[0040]
Although an example in the case of a third-order ΔΣ modulator is shown here, a higher-order ΔΣ modulator and a ΔΣ modulator having a plurality of local feedback loops can also be realized with the same configuration.
[0041]
FIG. 10 shows a conventional fifth-order ΔΣ modulator 60. This ΔΣ modulation device 60 includes two local feedback loop units composed of local feedback attenuators 70 and 77, and the quantization error component in the audible band is represented by a local feedback loop unit as shown in FIG. Since it can be suppressed to be lower than the quantization error component shown in FIG. 11A when no is provided, it is generally often used as a fifth-order ΔΣ modulator. However, by having two local feedback loops, data word length truncation occurs in the process.
[0042]
An attenuator 64 connected after the first integrator 63, an attenuator 67 connected after the second integrator 66, and a local feedback attenuator 70 connected after the third integrator 69. The data tone continues to expand in the direction of the carry, and the word length is further reduced by the attenuator 74 connected after the fourth integrator and the local feedback attenuator 77 connected after the fifth integrator 76. It will expand further infinitely. Actually, since the registers in the integrator are limited, the data word length is always rounded down to make the data length constant somewhere. Due to the truncation of the data word length, even the ΔΣ modulator 60 having two local feedback loops is accompanied by deterioration of sound quality.
[0043]
Therefore, as shown in FIG. 12, a noise shaper 81 is provided in the local feedback loop unit in addition to the local feedback attenuator 70, and a noise shaper 82 is provided in the local feedback loop unit in addition to the local feedback attenuator 77. The modulation device 80 is configured and used.
[0044]
The two noise shapers 81 and 82 have the same configuration as the noise shaper 39 shown in FIG.
[0045]
Therefore, the ΔΣ modulation device 80 can perform ΔΣ modulation that does not cause data truncation in the middle of the calculation, and enables ΔΣ modulation that suppresses the influence on the sound quality caused by the data truncation.
[0046]
Further, by using the ΔΣ modulation device 80 as the ΔΣ modulation device 5 inside the 1-bit arithmetic processing device 1 in FIG. 1, various signal processing can be performed on a high-quality high-speed 1-bit audio signal.
[0047]
【The invention's effect】
According to the present invention, in a delta-sigma modulation device having a local feedback loop, it is possible to realize a configuration without a data truncation process, thereby realizing a high-quality delta-sigma modulator and high-speed 1-bit audio that is delta-sigma modulated. Various signal processing with high sound quality can be performed on the signal.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a 1-bit signal processing apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a ΔΣ modulator that generates a 1-bit signal input to the 1-bit signal processing apparatus.
FIG. 3 is a block diagram showing the configuration of a specific example of a ΔΣ modulation device that constitutes the 1-bit signal processing device.
FIG. 4 is a block diagram showing a configuration of a first specific example of a conventional ΔΣ modulator.
5 is a diagram for explaining accumulation of quantization error in the ΔΣ modulation apparatus shown in FIG. 4; FIG.
FIG. 6 is a block diagram showing a configuration of a second specific example of a conventional ΔΣ modulator.
7 is a diagram for explaining accumulation of quantization error in the ΔΣ modulation apparatus shown in FIG. 6; FIG.
FIG. 8 is a diagram illustrating characteristics of quantization error generated by the ΔΣ modulation apparatus shown in FIGS. 4 and 6;
9 is a diagram for explaining accumulation of quantization error in the ΔΣ modulation apparatus shown in FIG. 3; FIG.
FIG. 10 is a block diagram showing a configuration of a specific example of a conventional fifth-order ΔΣ modulator.
11 is a diagram showing characteristics of quantization error generated by the ΔΣ modulation apparatus shown in FIG.
FIG. 12 is a block diagram showing a configuration of a fifth-order ΔΣ modulation apparatus used in the present invention.
[Explanation of symbols]
1 1-bit signal processor, 3 arithmetic processor, 5 ΔΣ modulator, 23, 28 and 33 integrator, 26, 31 attenuator, 36 1-bit quantizer, 37-bit length converter, 38 local feedback attenuator, 39 Noise shaper, 44 Local feedback loop

Claims (5)

In a delta-sigma modulation device that modulates a plurality of m-bit digital signals into 1-bit digital signals,
A plurality of n integration means;
Attenuating means for attenuating the integrated output of a predetermined number of integrating means among the plurality of n integrating means ;
And a local feedback loop means having a noise shaper for requantizing the attenuation output from the attenuation means and feeding back to the integration means before the predetermined integration means .   2. The delta-sigma modulation apparatus according to claim 1, wherein the local feedback loop means feeds back an output of the second and subsequent integration means among a plurality of n integration means to a previous integration means. Arithmetic means for inputting an m-bit digital signal to each integrating means before each of the plurality of n integrating means;
(N-1) attenuating means respectively connected after the first to (n-1) -th integrating means of the plurality of n integrating means;
1-bit quantization means connected to the nth integration means among the n integration means;
Bit length conversion means for converting the bit length of the 1-bit digital signal from the 1-bit quantization means into m bits and supplying the same to the calculation means so as to be input to the integration means. The delta-sigma modulation device according to claim 1. In a delta-sigma modulation method for modulating a plurality of m-bit digital signals into 1-bit digital signals,
An attenuating step for attenuating the integrated output of a predetermined number of integrating means among a plurality of n integrating means;
A local feedback loop process comprising: a noise shaper process that re-quantizes the attenuated output from the attenuation process and feeds back to the integration means before the predetermined integration means . Arithmetic processing means for performing a predetermined arithmetic operation on a 1-bit digital signal obtained by delta-sigma modulation to obtain an m-bit arithmetic processing signal;
Delta-sigma modulation means for performing a re-delta sigma modulation process on the arithmetic processing signal from the arithmetic processing means to obtain a 1-bit digital signal,
The delta-sigma modulation means includes a plurality of n integrating means, an attenuating means for attenuating the integrated output of a predetermined number of integrating means among the n integrating means, and an attenuation output from the attenuating means being requantized And a local feedback loop means having a noise shaper that is fed back to the integration means before the predetermined integration means .

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