JP3871776B2 - Central processing unit for gaming machines - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a central processing unit (CPU) for controlling a gaming machine such as a pachinko machine.
[0002]
[Prior art]
Today, a central processing unit (CPU) for a gaming machine is provided inside the gaming machine to control various electric parts constituting the gaming machine such as a pachinko machine, and this CPU is a predetermined program. By performing the operation according to the above, a predetermined control operation can be executed. When the CPU performs an operation, it sends a real address and real data onto a bus inside the CPU.
[0003]
By the way, in order to develop a gaming machine using this CPU, it is preferable that a real address and real data be output from the CPU as the CPU performs an operation according to the program. According to such a configuration, there is a possibility that a person who analyzes a program built in based on an output address or data and alters the program to be advantageous to himself reflecting the analysis result may appear.
[0004]
Therefore, it is possible to encrypt the program in advance and provide a decryption circuit for decrypting the program when necessary, so that the CPU operates according to the program decrypted by the decryption circuit. It was proposed.
[0005]
[Problems to be solved by the invention]
However, the configuration provided with such a decoding circuit leads to an increase in cost and an increase in the size of a circuit system mounted on the board, and there is no outside of the CPU due to the operation of the CPU. Since no information is output, the ROM data normally obtained by the assembler is once encrypted through encryption means, and then this encrypted data is actually written to the ROM. There was a problem that.
[0006]
And since a pachinko machine is not approved as a product for sale unless it is inspected by an inspection organization, there is a demand that the inspection organization should be configured to be able to inspect the operation of the CPU.
[0007]
The present invention has been made to solve such a conventional problem, and its purpose is to make a gaming machine capable of grasping the operation only by an inspection organization while preventing the operation from being grasped by a third party. The point is to provide a CPU.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, in a central processing unit for a gaming machine for controlling a gaming machine, when a mode switching signal is given, a mode corresponding to this is set. A mode control unit, a switching setting register for storing a switching signal in accordance with the mode set in the mode control unit, and a chip selection unit for decoding the address signal supplied on the bus to generate a chip select signal , and possible interface unit outputs to the outside by switching the chip select signal the chip select portion and the address signal is generated in response to the switching signal, the central processing unit for a game machine, characterized in that it comprises the provision Is done.
According to a second aspect of the present invention, when the mode stored in the mode control unit is the inspection mode, the switching setting register outputs the address signal from the interface unit and stores it in the mode control unit. When the current mode is the normal mode, the switching signal can be stored so that the chip select signal is output from the interface unit.
[0009]
According to this, the interface unit, it is possible to output by switching the address signal and the chip select signal in response to the set mode, for example, during normal outputs a chip select signal, special cases during a test Since only the address signal is output, the analysis of the program by a third party can be made difficult.
[0010]
In order to achieve the above object , according to the invention according to claim 3 , in the central processing unit for gaming machines for controlling gaming machines, the address signals supplied on the bus are decoded and chip select is performed. A chip select unit that generates a signal, and an interface unit that can switch and output the address signal and the chip select signal generated by the chip select unit, and the interface unit can be mounted with an external chip select unit is configured, the external chip select unit, when the address signal is output from the interface unit, for gaming machines central processing unit is provided and outputs a chip select signal corresponding to the address signal .
[0011]
According to this, when attaching the external chip select unit to the interface unit, it is outputted chip select signals from the external chip select unit, from the interface unit address signal is outputted, by the inspection engine with the address signal The inspection can be performed, and the gaming machine can be normally operated using the chip select signal.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of a gaming machine CPU 100 according to an embodiment of the present invention.
[0013]
When the 2-bit digital signals MODEA and MODEB are supplied, the gaming machine CPU 100 sets a clock based on a mode control unit 10 for setting a mode corresponding to the signals and a signal (XTAL) supplied from a crystal oscillation circuit (not shown). A clock generator 20 that generates and supplies to each unit (only the synchronization clock E is shown), a general-purpose function unit 30 having a general-purpose function of a normal CPU, and a one-time program type that stores an encrypted program EPROM 50, which is a read-only memory (OTP / ROM), and EEPROM 60, which is an electrically rewritable read-only memory that stores various data necessary for controlling the gaming machine, such as a plurality of types of probability setting values of a CR pachinko machine. RAM 70 functioning as a work area for various processing, and 16 bits Chip select unit 80 (address decoder) that generates chip select signals (CS00 to CS15) from address signals (ADR00 to ADR15), and outputs data (D0 to D7), addresses (ADR00 to ADR16), and chip select signals A bus interface unit 90 having a terminal for performing the operation, and a CPU core 40 having a register, an ALU, and the like (not shown) and operating according to a program stored in the EPROM 50. Each component includes a data line, an address A line 85 and a bus 85 including a control line are connected so that information can be transmitted and received.
[0014]
When the 2-bit digital signals MODEA and MODEB are given, the mode control unit 10 performs mode setting according to the signals. For example, when a low level signal is “0” and a high level signal is “1”, the bus interface 90 outputs a chip select signal when “MODEA = 0, MODEB = 0” (normal mode). Then, an operation for applying a digital signal to the control line is performed, and when “MODEA = 0, MODEB = 1” (ROM writing mode), information can be written to the EPROM 50 and the EEPROM 60 via the bus interface 90. In the case of “MODEA = 1, MODEB = 0” (verify mode), the verify operation with the external master ROM (not shown) is similarly performed via the bus interface 90. And "MODEA = 1, MODEB = 1" (inspection mode), inspection Seki As inspection capable bus interface 90 outputs an address signal, performs an operation for providing a digital signal to the control line.
[0015]
The general-purpose function unit 30 includes an interrupt control unit 31 that is reset by a reset signal (RESET) and starts interrupt processing by an interrupt signal (IRQ), a watchdog unit 33 that includes a watchdog timer having a function of detecting runaway, etc. And a timer unit 32 for generating two types of timeout signals (TM0, TM1).
[0016]
The chip select unit 80 operates as an address decoder output that generates chip select signals (CS00 to CS15) for enabling 16 types of latch ICs (not shown) from a 16-bit address signal (ADR00 to ADR15).
[0017]
For example, if addresses of “7FF0 (H) to 7FFF (H)” are assigned to each of 16 types of latch ICs as an example, the address signal is “7FF0 (H) to 7FFF (H). ) ", Any one of the corresponding chip select signals becomes active (for example, low level).
[0018]
For example, the bus interface unit 90 can be configured to include an analog switch for selecting address data and a chip select signal by a control signal (a signal on a control line) for each bit from a lower bit to an upper bit.
[0019]
In the example shown in FIG. 2, analog switches 91a,..., 91b are provided corresponding to each bit from the least significant bit to the most significant bit, and the analog switch 91a can switch between CS00 and ADR00. The analog switch 91b is configured to be able to switch between CS15 and ADR15. Note that, for example, the contents of the switching setting register 92 connected to the CPU core 40 via a bus are sent to be a control signal.
[0020]
The control signal selects the chip select signal when a high level signal is written in the switching setting register 92, and selects the address signal when a low level signal is written in the switching setting register 92. The analog switch can be selected. In this way, the address signal (ADR00 to ADR15) and the chip select signal (CS00 to CS15) are switched.
[0021]
FIG. 2 shows an example of the bus interface unit 90, and other configurations may be used as long as the address signal and the chip select signal can be switched.
[0022]
First, when a high-level digital signal is supplied to MODEA and MODEB, the gaming machine CPU 100 enters a normal mode. In the normal mode, the mode control unit 10 stores a high level signal in the switching setting register 92.
[0023]
When the CPU core 30 operates in accordance with a program stored in the EPROM 40, addresses and data are transmitted and received within the CPU via the bus 85. The bus interface 90 outputs the chip select signal generated by the chip select unit 80. Any latch IC (not shown) that inputs this chip select signal latches data (D0 to D7). At this time, the address signal itself is not output.
[0024]
On the other hand, when a high-level digital signal is supplied to MODEA and MODEB, the operation of the gaming machine CPU 100 enters the inspection mode, and the operation will be described assuming that the inspection engine inspects the gaming machine CPU 100. First, in the inspection mode, the mode control unit 10 stores a low level signal in the switching setting register 92.
[0025]
When the CPU core 30 operates in accordance with a program stored in the EPROM 40, addresses and data are transmitted and received within the CPU via the bus 85. The bus interface 90 outputs an address signal. At this time, the chip select signal is generated but not output by the address decoding operation of the chip select unit 80.
[0026]
In this way, the signal output from the bus interface 90 can be switched between the address signal and the chip select signal. Therefore, according to this embodiment, since a chip select signal is normally output and an address is output only in a special case such as an inspection in an inspection organization, it is difficult for a third party to analyze a program. The effect that it can be obtained.
[0027]
Instead of changing the contents of the switching setting register 92 by the mode control unit 10, the storage contents of the switching setting register 92 may be forcibly set by a program to perform desired switching.
[0028]
When the address signal is output from the bus interface 90 for inspection, the chip select signal is not output. Therefore, the latch IC operated by the chip select signal cannot be driven in the normal state, and the control operation of the gaming machine can be performed. There will be no. Therefore, if the external chip select unit 200 that generates the chip select signal based on the address signal is output from the bus interface 90 so that it can be mounted on the gaming machine CPU 100, the inspection organization sends the address signal. It is possible to perform normal gaming machine control using a chip select signal while performing the inspection used.
[0029]
FIG. 3 shows a state in which the external chip select unit 200 is mounted on the gaming machine CPU 100. According to this, the external chip select unit 200 performs the same operation as the chip select unit 80, and generates the chip select signal (CS00 to CS15) using the address signal (ADR00 to ADR15).
[0030]
A specific configuration example for realizing the external chip select unit 200 will be described with reference to FIG.
FIG. 4 is a configuration diagram of only a part of the external chip select unit 200, specifically, the generation unit of the chip select signals CS00 and CS01.
[0031]
First, the generation unit of the chip select signal CS00 includes a NAND gate circuit 210 having four input terminals, and AND gate circuits 201, 202, 203, and 204 connected to the four input terminals. ing. The NAND gate circuit 210 can output a low-level signal only when the synchronization clock E generated by the clock generator 20 is input and the synchronization clock E is at a high level. The clock E is obtained when the CPU core is “68HC11” manufactured by Motorola (motorola is a registered trademark).
[0032]
The AND gate circuit 201 is configured to be capable of inputting signals obtained by inverting the signals of the address lines ADR00 to ADR03 by NOT gate circuits 220, 221, 222, and 223. The AND gate circuit 202 includes the address lines ADR04 to ADR07. The AND gate circuit 203 is configured to be able to input signals on the address lines ADR08 to ADR11, and the AND gate circuit 204 further includes signals on the address lines ADR12 to ADR14 and signals on the address line ADR15. Is inverted by a NOT gate circuit 224 so that it can be input.
[0033]
The AND gate circuit 201 outputs a high level signal when the signals on the address lines ADR00 to ADR03 are “0000”, and the AND gate circuit 202 outputs a high level signal when the signals on the address lines ADR04 to ADR07 are “1111”. The AND gate circuit 203 outputs a high level signal when the signals on the address lines ADR08 to ADR11 are “1111”, and the AND gate circuit 204 further outputs the signals on the address lines ADR12 to ADR15 to “0111”. A high level signal is output when.
[0034]
When the outputs from the four AND gate circuits 201 to 204 are “1”, the AND gate circuit 210 outputs a low level signal as the chip select signal CS00. Therefore, when the address signal is “7FF0 (H)”, a chip select signal CS00 for enabling a latch IC (not shown) to be in an enabled state (active low) is output.
[0035]
The chip select signal CS01 generation unit includes a NAND gate circuit 211 having four input terminals, and AND gate circuits 205, 206, 207, and 208 connected to the four input terminals. ing. Further, the synchronization signal E described above is input to the NAND gate circuit 211.
[0036]
The AND gate circuit 205 is configured to be able to input a signal of the address line ADR00 and the address lines ADR01 to ADR03 which are inverted by NOT gate circuits 225, 226 and 227, and the AND gate circuit 206 The ADR04 to ADR07 signals can be input, the AND gate circuit 207 can be configured to input the address lines ADR08 to ADR11, and the AND gate circuit 208 further includes the address lines ADR12 to ADR14 and the address lines. An ADR 15 signal inverted by a NOT gate circuit 228 can be input.
[0037]
The AND gate circuit 205 outputs a high level signal when the signals on the address lines ADR00 to ADR03 are “0001”, and the AND gate circuit 206 outputs a high level signal when the signals on the address lines ADR04 to ADR07 are “1111”. The AND gate circuit 207 outputs a high level signal when the signal on the address lines ADR08 to ADR11 is “1111”, and the AND gate circuit 208 further outputs the signal on the address lines ADR12 to ADR15 to “0111”. A high level signal is output when.
[0038]
When the outputs from the four AND gate circuits 205 to 208 are “1”, the AND gate circuit 211 outputs a low level signal as the chip select signal CS01. Therefore, when the address signal is “7FF1 (H)”, a chip select signal CS01 for enabling a latch IC (not shown) to be enabled (active low) is output.
[0039]
In this way, the chip select unit 80 that generates chip select signals CS00 to CS15 that are active when the address signal is “FFF0 (H)”, “FFF1 (H)”,..., “FFFF (H)”. It is possible to realize the external chip select unit 200 having the same function as the above.
[0040]
Therefore, as shown in FIG. 3, if the address signals ADR00 to ADR15 are input to the external chip select unit 200, a chip select signal can be generated in the same manner as the chip select unit 80.
[0041]
According to this, an address is output from the interface unit 90, the inspection by the inspection organization can be performed using this address, and the gaming machine is normally operated using the chip select signal output from the external chip select unit 200. It can also be operated. As a result, it is possible to prevent an increase in developer man-hours.
[0042]
Next, specific configuration examples of the gaming machine CPU 100 and the external chip selection unit 200 according to the embodiment of the present invention will be described with reference to FIG.
FIG. 5 is a schematic diagram showing a state where the gaming machine CPU and the external chip select unit according to the embodiment of the present invention are mounted on the board. FIG. 5A is a diagram for mounting the gaming machine CPU 100. FIG. 5B shows a configuration of a gaming machine control board 500 that includes a socket portion 510 realized by an IC socket or the like, and that can be mounted on the back side of the gaming machine, and FIG. 5B shows a test prepared separately. The structure of the sub board | substrate is shown. In the normal state, the gaming machine CPU 100 is directly attached to the socket 510, while the inspection sub-board 520 is attached in the inspection mode. The inspection sub-board 520 is provided with a connection pin 540 that protrudes so as to be attachable to the socket portion 510 of the gaming machine control board 500, and further, the gaming machine CPU 100 and the external chip selection section 200. (FIG. 5B shows a state where the gaming machine CPU 100 and the external chip select unit 200 are mounted), and information on the address bus, data bus, and control bus is displayed. A monitor terminal 530 for monitoring is provided.
[0043]
The connection pin 540 has a shape into which an IC socket can be inserted, and the pin arrangement of each terminal is exactly the same as that of the gaming machine CPU 100. The difference from the CPU 100 for gaming machines is that “CS ** / ADR **” (** is a number from 00 to 15, for example) is directly connected, instead of a chip select signal from the external chip select unit 200. “CS **” (** is a number from 00 to 15, for example) is connected. Other signals are connected and supplied directly to the connection pins 540 from the gaming machine CPU 100 mounted on the inspection sub-board 52.
[0044]
Further, the external chip select unit 200 is connected to generate a chip select signal “CS **” from the address from the gaming machine CPU 100. In addition, a signal necessary for inspection by the inspection organization is connected to be able to be taken out from the monitor terminal 530. The signals to be connected include the address bus “ADR **” from the gaming machine CPU 100, the data bus (D0 to D7), and the control signals (E, R / W). ) And the like. The monitor terminal 530 is connected to an inspection device such as an external logic analyzer so that the program can be inspected and analyzed.
[0045]
The gaming machine CPU 100 may be configured to automatically enter the inspection mode when connected to the inspection sub-board 520. For this purpose, a desired digital signal may be supplied to a desired pin position of an IC socket in which the CPU 100 for gaming machines is mounted so that a desired digital signal is supplied to MODEA and MODEB. . The inspection sub-board 520 having such a configuration is attached to the socket portion 510 by the connection pins 540.
[0046]
By this mounting, the signal from the gaming machine CPU 100 can be supplied to the gaming machine control board 500 side, so the gaming machine control board 500 is mounted with the gaming machine CPU 100 operating in the normal mode. Perform the same operation as
[0047]
Furthermore, if the performance of the external chip select section 200 is configured with the same function as the chip select section 80 built in the gaming machine CPU 100, it can operate under exactly the same conditions as when the CPU 100 is directly mounted. On the other hand, on the inspection sub-board 520 side to which the gaming machine CPU 100 is attached, an external inspection device such as a logic analyzer is connected to the monitor terminal 530, thereby enabling operation inspection and analysis. In the above description of the embodiment, a pachinko machine has been particularly assumed. However, the present invention provides a gaming machine CPU that can be suitably applied to other gaming machines such as a pachislot machine. Is.
[0048]
【The invention's effect】
As described above, according to the first and second aspects of the invention, the interface unit switches and outputs the address signal and the chip select signal according to the set mode. In addition to the output, an address signal is output at the time of inspection at the inspection organization, so that it is possible to make the analysis by the third party difficult while enabling inspection at the inspection organization.
[0049]
According to the invention of claim 3 , when the external chip select unit is attached to the interface unit, a chip select signal is output from the external chip select unit and an address signal is output from the interface unit. The inspection can be performed by the inspection organization using the signal , and the gaming machine can be normally operated using the chip select signal.
[Brief description of the drawings]
FIG. 1 is a block diagram of a gaming machine CPU according to an embodiment of the present invention.
FIG. 2 is a configuration diagram of a bus interface unit.
FIG. 3 is a block diagram of a gaming machine CPU to which an external chip select unit is connected.
FIG. 4 is a configuration diagram of an external chip select unit.
FIG. 5 is a schematic diagram showing a state in which a gaming machine CPU and an external chip select unit according to an embodiment of the present invention are mounted on a substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Mode control part 20 Clock generation part 30 General-purpose function part 31 Interrupt control part 32 Timer part 33 Watchdog part 34 PWM part 40 CPU core 50 EPROM
60 EEPROM
70 RAM
80 chip select section 90 bus interface section 91a analog switch 91b analog switch 92 switching setting register 100 CPU for gaming machine
200 External Chip Select Units 201-208 AND Gate Circuit 210 NAND Gate Circuit 211 NAND Gate Circuits 220-228 NOT Gate Circuit 500 Game Machine Control Board 510 Socket Unit 520 Inspection Sub-board 530 Monitor Terminal 540 Connection Pin

Claims (3)

In a central processing unit for gaming machines for controlling gaming machines,
A mode control unit for setting a mode corresponding to a signal for switching the mode;
A switching setting register for storing a switching signal according to the mode set in the mode control unit;
A chip select unit that decodes an address signal supplied on the bus and generates a chip select signal;
A central processing unit for gaming machines, comprising: an interface unit capable of switching the address signal and the chip select signal generated by the chip select unit in accordance with the switching signal and outputting the same to the outside . The switching setting register outputs the address signal from the interface unit when the mode stored in the mode control unit is a test mode, and when the mode stored in the mode control unit is a normal mode. The central processing unit for gaming machines according to claim 1, wherein the switching signal is stored so that the chip select signal is output from the interface unit . In a central processing unit for gaming machines for controlling gaming machines,
  A chip select unit that decodes an address signal supplied on the bus and generates a chip select signal;
  An interface unit capable of switching and outputting the address signal and the chip select signal generated by the chip select unit;
  The interface unit is configured so that an external chip select unit can be mounted. When the address signal is output from the interface unit, the external chip select unit outputs a chip select signal corresponding to the address signal. A central processing unit for gaming machines.

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