JP3890338B2 - Image signal processing device - Google Patents

Description

  The present invention relates to an image signal processing apparatus for performing processing such as encoding and decoding of image data.

  2. Description of the Related Art Conventionally, various apparatuses have been developed for encoding various kinds of data with a huge amount of data so that the amount of data can be reduced and transmitted at a relatively low transmission rate. For example, in a digital VTR that records image data on a storage medium such as magnetic tape, a standard has been established for compressing input image data of about 124 Mbps to about 1/5 of 25 Mbps, and recording and reproducing the data on magnetic tape. Has been.

  In a digital VTR based on such a standard, the input data is quantized after DCT conversion, and the quantized data is subjected to variable length coding by Huffman coding or the like, thereby compressing the data and further quantizing the data. The rate control is performed so that the quantization step at that time is variable based on various parameters, or the amount of data after the variable length encoding is constant.

  Further, the input image data is compressed using interframe or interfield motion compensation predictive coding, and the predictive coded data is further compressed using the above-described DCT, quantization, and variable length coding. The MPEG standard has been established, and various devices such as a CD-ROM corresponding to this standard have been developed.

JP-A-6-245189

  In a device such as a digital VTR or a CD-ROM as described above, it is necessary to perform various signal processing in real time. In order to realize this, it is considered to use a plurality of memories adapted to various signal processing, but there is a problem that the cost of the whole apparatus is increased and downsizing is hindered.

  The present invention has been made in view of the above circumstances, and provides an image signal processing apparatus capable of high-speed image processing and optimal memory use while reducing the cost and downsizing of the entire apparatus. With the goal.

  In the image signal processing apparatus according to the present invention, each has a luminance signal and two color difference signals, and the pixels of the two color difference signals are thinned out in the horizontal direction with respect to the pixels of the luminance signal, and are arranged in each horizontal line. The first image signal in which the two color difference signals are present, and the pixels of the two color difference signals are thinned out in the horizontal direction with respect to the pixels of the luminance signal, and the two color difference signals are alternately displayed for each horizontal line. An image signal processing apparatus that processes a second image signal in which one exists, and can perform burst writing and burst reading on the same row address in synchronization with a clock, and is input A memory for storing the first image signal and the second image signal, and a first image signal stored in the memory in units of pixel blocks each including a plurality of pixels in the vertical and horizontal directions. Or processing means for processing the second image signal, and a plurality of luminance line blocks having a burst length when accessing the memory for each horizontal line of the luminance signal in the first image signal and the second image signal. And the horizontal lines of the two color difference signals are respectively divided into a plurality of color difference line blocks, and the data of all the pixels in the same block for the luminance signal and the two color difference signals are the same in the memory. The luminance line block and the color difference line block of the two color difference signals are arranged so as to line up with the row address of the first image signal, and the control means includes the two of the same horizontal line for the first image signal. The horizontal lines of the two color difference signals are adjusted so that the color difference line blocks of the color difference signals are combined to obtain the burst length. The color difference line blocks of the two color difference signals having the burst length on the same horizontal line are arranged at the same row address, and the second image signal is divided into the two line blocks. The horizontal lines of the two color difference signals are divided into a plurality of line blocks so that the color difference line blocks of the color difference signals have the burst length, and the color difference line blocks of the two color difference signals are arranged at different row addresses.

  According to the present invention, data of the same block can be accessed at high speed, and a memory can be optimally used according to the type of image signal. Specifically, according to the present invention, two types of image signals having different sampling configurations for color difference signals can be efficiently arranged in a burst accessible memory.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the basic configuration of the present invention.
In the present embodiment, as shown in FIG. 1, various processing blocks are controlled by the system control block 8 while each accesses the memory at a desired timing, and the system control block 8 arbitrates those access requests. It is configured to guarantee the operation of each block.

Each of the above blocks operates as follows.
Terminal 1, terminal 2, and terminal 3 input DI component digital component signals in which the ratio of the luminance signal (hereinafter referred to as Y) and the color difference signals (hereinafter referred to as Cr and Cb) is 4: 2: 2. Output terminal.

  At the time of encoding, the image input / output block 4 thins out the color difference signal for the data input from the terminals 1 to 3 so that the ratio of the luminance signal and the color difference signal is converted into a digital signal of 4: 1: 1. A conversion process is performed, and a data string (hereinafter referred to as MUX-DATA) obtained by performing a multiplexing process on the Y, Cr, and Cb is output. At the same time, Y-RA, C-RA and enable signals Y-EN, C-EN, which are addresses for temporarily buffering Y, Cr / Cb in the MUX-DATA column in the buffer 5, are generated, and the main memory 6, Y-MA, C-MA and memory access request signals ReqY, ReqC are generated for the system control block 8. Further, at the time of decoding, MUX-DATA is read from the buffer 5 and converted into a 4: 2: 2 digital component signal while generating a signal similar to the above, and output to the terminals 1 to 3.

  The buffer 5 includes address signals (Y-RA, C-RA, YM-RA, CM-RA) from each peripheral block, and control signals (Y-En, C-En, YM-En, CM-En) and the luminance signal (hereinafter referred to as Y-MD) and the color difference signal (hereinafter referred to as C-MD) for writing / reading data to / from the main memory 6 by the predetermined data. Buffer long. The main memory 6 writes / reads data in synchronization with the system clock.

  The compression / decompression block 7 accesses the main memory 6 and performs variable length encoding / decoding using discrete cosine transform on the image data. The system control block 8 controls the entire system including the main memory 6 based on an address and a memory access request signal for the main memory 6 from each block. The main memory 6 according to the present embodiment uses an SDRAM (Synchronous DRAM) that enables high-speed read / write access by performing burst transfer of data in synchronization with the rising edge of the clock. Yes.

  The clock supplied to the SDRAM is, for example, a 27.5 MHz clock supplied from an external frequency oscillator 90 without jitter to the frequency multiplier 92 as shown in FIG. Supplied as a clock. Here, the reference clock 67.5 MHz (MCLK) is set to an integral multiple (5 times) of 13.5 MHz locked to the horizontal synchronizing signal generated by the frequency oscillator 94. Here, 13.5 MHz supplied from the frequency oscillator 94 is a sampling frequency of Y, and 3.375 MHz divided by 4 by the frequency divider 96 is converted to the above 4: 1: 1. It is the sampling frequency of Cr and Cb.

Next, a detailed operation in which Y, Cr, and Cb are multiplexed by the image input / output block 4 in FIG. 1 will be described with reference to FIG. In FIG. 3, the same parts as those in FIG.
Reference numeral 40 denotes a general filter. At the time of encoding, image data EX-Y of 4: 1: 1 is obtained by thinning out the image data Y, Cr, and Cb input at 4: 2: 2. , EX-Cr, EX-Cb. On the other hand, at the time of decoding, 4: 2: 1 image data Y, Cr is obtained by interpolating the 4: 1: 1 image data EX-Y, EX-Cr, EX-Cb on the color difference signal. , Cb is restored and output. Here, EX-Y is synchronized with the above 13.5 MHz, and EX-Cr and EX-Cb are synchronized with the above 3.375 MHz.

  Reference numerals 42, 44, and 46 are bidirectional flip-flops driven at 67.5 MHz. At the time of encoding, the image data EX-Y, EX-Cr, and EX-Cb are multiplexed and synchronized to 67.5 MHz. The generated MUX-DATA is generated, and at the time of decoding, demultiplex processing is performed from the MUX-DATA to generate image data EX-Y, EX-Cr, and EX-Cb. Each of the above processes is controlled by the Enebourg signals MUX-Y, MUX-Cr, and MUX-Cb synchronized with 67.5 MHz supplied from the timing generator 48, respectively. In addition to the above, the timing generator 48 is provided with each address (Y-RA, C-RA, Y-MA, C-MA) synchronized with 67.5 MHz, an Enebourg signal (Y-En, C-En), memory access Request signals (ReqY, ReqC) are generated and supplied to the peripheral blocks.

FIG. 4 shows the detailed timing of the multiplex and demultiplex processing in FIG. 4A to 4G show the multiplex timing.
(A) is 4: 1: 1 luminance data EX-Y synchronized with 13.5 MHz, (b) is 4: 1: 1 color difference data EX-Cr synchronized with 3.375 MHz, and similarly (c) is 3. Color difference data EX-Cb of 4: 1: 1 synchronized with 3.375 MHz. (D), (e), (f) are Inebourg signals synchronized with 67.5 MHz. EX-Y in (a) is latched at 67.5 MHz when MUX-Y in (d) is at LOW level. (B) EX-Cr is latched at 67.5 MHz when (e) MUX-Cr is at LOW level, (c) EX-Cb is (F) MUX-Cb is LOW By latch output at 67.5 MHz at the level, multiplex data MUX-DATA is generated as shown in (g).

  4 (g) and 4 (a) 'to (f)' show the demultiplex timing. (D) ′, (e) ′, and (f) ′ are enable signals MUX-Y, MUX-Cr, and MUX-Cb when performing demultiplex processing, respectively. When the enable signal is at the LOW level, MUX-DATA is latched and output at 67.5 MHz, so that demultiplexed EX-Y (a) ′, EX-Cr (b) ′, and EX-Cb (c) 'Is generated. As a matter of course, EX-Y (a) ′ is synchronized with 13.5 MHz, and EX-Cr (b) ′ and EX-Cb (c) ′ are data strings synchronized with 3.375 MHz.

FIG. 5 is a memory map of the buffer 5 in FIG.
The total capacity is 256 bytes. The color difference signals EX-Cr and EX-Cb are mapped to addresses 0 to 127, and the luminance signal EX-Y is mapped to addresses 128 to 255. Furthermore, each region of the luminance signal and the color difference signal has a bank configuration in units of 64 bytes in the present embodiment. Here, addresses 0 to 63 are bank 0 (hereinafter referred to as C-B0) for color difference signals, and addresses 64 to 127 are bank 1 (hereinafter referred to as C-B1) and addresses for color difference signals. 128 to 191 are configured as a bank 0 for luminance signals (hereinafter referred to as Y-B0), and addresses 192 to 255 are configured as a bank 1 for luminance signals (hereinafter referred to as Y-B1). The system input / output block 4 and the main memory 6 are controlled by the system control block 8 so as not to compete with each other.

FIG. 6 is a detailed timing chart of the writing / reading process at the time of encoding with respect to the buffer 5.
(A) is multiplexed data MUX-DATA supplied from the image input / output block 4. (B) and (d) are for extracting the luminance signals (XY0, XY1,...) And the color difference signals (XCr0, XCb0, XCr1, XCb1,...) From the MUX-DATA, respectively, and writing them to the respective areas of the buffer 5. This is an enable signal, and (c) and (e) are write addresses at that time.

  When the Y-En in (b) is at the LOW level, the Y-RA in (c) is selected as the write address, and the C-RA in (e) is selected when the C-En in (d) is at the LOW level. The At this time, Y-En and C-En cannot be at the LOW level at the same time. Therefore, the luminance signal is sequentially written from the address 128 of Y-B0 in FIG. 5, and the color difference signal is similarly written from the address 0 of C-B0. Here, 67.5 MHz is 20 packets and one packet is represented as a packet in (a). Therefore, one packet contains 4 bytes of luminance data and 1 byte of color difference data for each of the Cr component / Cb component.

  (F) and (g) are memory access request signals supplied from the image input / output block 4 to the system control block 8, and are output each time 64 bytes of luminance data and color difference data are accumulated in the buffer 5. Is done. Accordingly, the memory access request signal for luminance data is output when the packet number P15 shown in (a) ′ is accumulated in the buffer. On the other hand, the memory access request signal for color difference data is output when the packet number P31 shown in (a) ′ is accumulated in the buffer. The breakdown of the color difference data of 64 bytes at this time is that the Cr component is 32 bytes and the Cb component is 32 bytes. However, this is the case where the television system is in the NTSC mode, and this is not the case in other modes such as PAL.

  (I) and (k) are enable signals YM-En and CM-En generated as a result of arbitrating the memory access request signal supplied from each block in the system control block 8. (H) is luminance data Y-MD read from the buffer, and YM-En is read during the LOW level period. Similarly, (j) is the color difference data C-MD read from the buffer, and CM-En is read during the LOW level period. Here, although not shown, each read address is generated so that the image input / output block 4 is read from a bank opposite to the bank to which the image input / output block 4 is writing in real time. In addition, in reading the color difference data C-MD in the present embodiment, since it is desired to access the main memory 6 in units of 32 bytes each for the Cr component / Cb component, addresses are generated separately for even / odd.

FIG. 7 is a detailed timing chart of the writing / reading process at the time of decoding with respect to the buffer 5.
(A) ReqY and (b) ReqC are memory access request signals from the image input / output block 4 to the system control block 8, and are supplied from the timing generator 48 of FIG. ReqY is generated in a cycle of (1 / 13.5 MHz × 64 bytes) ns and accesses luminance data, and ReqC is generated in a cycle of (1 / 6.75 MHz × 64 bytes) ns and accesses color difference data.

  (C) Y-MD and (d) C-MD are the luminance data and color difference read by supplying the read address to the main memory 6 as a result of the arbitration processing of the memory access request signal in the system control block 8. It is data. The burst length at the time of memory access in this embodiment is 64 bytes as in the case of encoding. The means for calculating the burst length for access will be described in detail later.

  (D) YM-En and (f) CM-En are enable signals for writing data read out from the main memory 6 with the same burst length to the buffer 5, and each of the data in the LOW level period. Write processing is performed. Although not shown, a write address is supplied from the system control block 8 to the buffer 5, but as described above, bank control is performed so that it does not conflict with the processing of other blocks.

  (G) Y-En, (i) C-En, (h) Y-RA, and (i) C-RA are supplied from the image input / output block 4 to the buffer 5 as described in the encoding process. Enable signal and read address. (K) MUX-DATA is multiplexed with luminance data and color difference data latched and output by (g) Y-En, (i) C-En, and (h) Y-RA, (i) C-RA. And is supplied to the image input / output block 4.

Next, the mapping method of the main memory 6 will be described.
FIG. 8 shows a memory space of the main memory 6 of FIG. 1, and a video memory (VM) area (BS0 and BS1) having a capacity for two frames and a capacity for storing other data. The memory cells in each region can be set to the write mode and the read mode for each frame, and between the VM region or the Others region as necessary. It is also possible to exchange data with.

  That is, in FIG. 1, the image input / output block 4 exchanges data with the VM area exclusively through the buffer 5, and the compression / decompression block 7 exchanges data with the VM area. At the time of encoding, data is read from the VM area and encoded, and then output to the subsequent processing unit. At the time of decoding, the input encoded data is decoded and written to the VM area. The addresses at this time are generated by the system control block 8 in FIG. 1 as column (hereinafter referred to as row) addresses and row (hereinafter referred to as col) addresses.

Next, a method for calculating the burst length when accessing the main memory 6 will be described with reference to FIG.
In FIG. 9, (A) shows the structure of luminance data (hereinafter referred to as Y) in one frame of NTSC mode converted to 4: 1: 1, and is composed of horizontal 720 pixels × vertical 480 lines. . (B) shows the configuration of the color difference data (hereinafter referred to as Cr and Cb) in the NTSC mode 1 frame converted to 4: 1: 1. Each of Cr and Cb is composed of horizontal 180 pixels × vertical 480 lines. Is done.

  (C) shows the structure of luminance data (hereinafter referred to as Y) in one frame of the PAL mode converted to 4: 2: 0, and is composed of horizontal 720 pixels × vertical 576 lines. (D) shows the structure of color difference data (hereinafter referred to as Cr and Cb) in a PAL mode 1 frame converted to 4: 2: 0, and each of Cr and Cb is composed of 360 horizontal pixels × vertical 288 lines. Is done. (E) is a DCT block when the compression / decompression block 7 performs encoding / decoding processing. Usually, it is composed of n pixels × m pixels, but in this embodiment, n = m = 8.

In the present invention, the burst length for accessing the main memory 6 is determined by the following conditional expression.
Burst length = (m × N) × n ≦ COL (1)
N: Natural number of 1 or more COL: Capacity in the column direction of banks (BS0 and BS1).
Here, since COL = 512 in the present embodiment, the expression (1) is
8N × 8 ≦ 512 (2)
Therefore, N ≦ 8.

  Therefore, the burst length is a multiple of 8 from 8 bytes to 64 bytes. In order to access the SDRAM, which is the main memory 6, efficiently and at high speed, it is desirable to fix the row address and access with the longest burst length possible. Therefore, in this embodiment, the burst length is 64 bytes.

Next, a method for accessing the VM area of Y data in the NTSC mode will be described in detail with reference to FIG.
FIG. 10A shows a state in which the area A in FIG. 8 is enlarged and the actual screen image data is arranged beyond the memory. Here, CBL0 to CBL7 are column blocks divided every 64 columns, and RN is the number of divisions of one horizontal line. As described above, the image data of one line in FIG. 9A is divided into twelve for every 64 pixels, and the twelve blocks of the divided Line 0 are in the row direction as shown in the CBL0 area in FIG. The data are sequentially stored at (address 0 to address 11). Similarly, Line1 is sequentially stored in the CBL1 area. The same applies to the image data of the remaining lines.

  Accordingly, the data of the 8n + 0th line (n is a positive number greater than or equal to 0) in FIG. 9A is sequentially stored in the CBL0 area, the 8n + 1th line in the CBL1 area, the 8n + 2th in the CBL2 area, In the CBL3 area, data of the 8n + 3th, 8th + 4th in the CBL4 area, 8n + 5th in the CBL5 area, 8n + 6th in the CBL6 area, and 8n + 7th data in the CBL7 area are sequentially stored. Become.

  On the same row address stored in this way, there are eight DCT blocks of 8 pixels × 8 pixels shown in FIG. 9E in the horizontal direction of the one screen. Therefore, when the compression / decompression block 7 shown in FIG. 1 reads out and encodes this data, if 8 data are continuously read out from the head addresses of CBL0 to CBL7, the desired 8 pixels × 8 pixels can be obtained. Data of the DCT block can be obtained, and the DCT block is sequentially read and processed by sequentially reading out the 8 data while sequentially offsetting the col address by 8 with respect to CBL0 to CBL7.

  On the other hand, at the time of decoding, the 8 pixel × 8 pixel data decoded by the compression / decompression block 7 of FIG. By writing the data continuously, the data is stored as shown in FIG. The image input / output block 4 sequentially reads the data in 64 burst units while sequentially changing the row address. The same processing operation is performed in the PAL mode.

Next, a method for accessing the VM area of Cr and Cb data will be described in detail.
First, the memory access operation of the image input / output block 4 will be described. As shown in FIG. 9B, the color difference data in the NTSC mode is thinned out to 1/4 in the horizontal direction, and Cr and Cb data exist simultaneously on each line. Further, the DCT block configuration of the color difference data is 8 pixels × 8 pixels as in the luminance data, and the capacity in the COL direction per bank is 512 bytes. Therefore, the burst length in one access is 64 bytes, similarly to the luminance data. However, as described above, due to the nature of the color difference data in the NTSC mode, the breakdown of the burst length in one access is 64 bytes including 32 bytes of Cr and 32 bytes of Cb.

FIG. 11A shows bank 0 in the Cr / Cb region of FIG. 8 in the NTSC mode.
Cr and Cb are divided by a col address, and a col address from 0 to 255 is defined as a Cr area, and a col address from 256 to 511 is defined as a Cb area. CBL0 to CBL15 are column blocks divided every 32 columns of Cr / Cb. Here, in the writing / reading mode, access to 64 bytes of color difference data is performed for 32 bytes of Cr to CBL0 and 32 bytes of Cb to CBL8. Sequentially, each time the line changes, the access area changes such as CBL1 and CBL9 and CBL2 and CBL10.

FIG. 10B shows the above process in detail by enlarging the bank 0 in the Cr region of FIG.
Here, RN is the number of divisions of the horizontal line, and in the case of color difference data, RN = 5. As described above, the image data of one line in FIG. 9B is divided into six for every 32 pixels of Cr and Cb, and the six blocks of Line 0 thus divided are Cr. As shown in the CBL0 area, processing is sequentially performed in the row direction (address 0 to address 5). Similarly, processing is performed on the CBL8 area for the six blocks of Cb Line0.

  Further, the Cr and Cb of Line 1 are similarly processed for the CBL 1 and CBL 9 areas. The same applies to the image data of the remaining lines. Therefore, for the CBL0 and CBL8 areas, the Cr and Cb data of the 8n + 0th line (n is a positive number greater than or equal to 0) in FIG. 9B is processed, respectively. , 8n + 1, CBL2, CBL10 area, 8n + 2, CBL3, CBL11 area, 8n + 3, CBL4, CBL12 area, 8n + 4, CBL5, CBL13 area, 8n + 5, CBL6, CBL14 area , 8n + 6th, CBL7, CBL15 area, the data of the 8n + 7th line is processed.

Next, the memory access operation of the compression / decompression block 7 in FIG. 1 will be described.
For example, on the same row address in which Cr and Cb in NTSC mode are written as described above, the DCT block of 8 pixels × 8 pixels shown in FIG. 9E is Cr in the horizontal direction of the one pixel. , Cb exists for each 8 pieces. Therefore, when the compression / decompression block 7 reads out and encodes this data, it can read out the 8 data continuously from the head addresses of CBL0 to CBL7, and the Cr of the desired 8 pixel × 8 pixel DCT block can be obtained. Similarly, Cb data of a desired 8-pixel × 8-pixel DCT block can be obtained by continuously reading 8 data from the head addresses of CBL8 to CBL15. By sequentially reading 8 data while sequentially offsetting the col address by 8 with respect to CBL0 to CBL7 and CBL8 to CBL15 in the same manner, Cr and Cb each constitutes a desired DCT block and performs processing.

  On the other hand, at the time of decoding, the 8 pixel × 8 pixel data decoded by the compression / decompression block 7 is 8 data while offsetting the col address by 8 with respect to CBL0 to CBL7 and CBL8 to CBL15, contrary to the encoding. Are continuously written to store data as shown in FIG. The image input / output block 4 performs continuous reading in units of 64 bursts for every 32 bytes of Cr data and 32 bytes of Cb data while sequentially changing the row address.

Next, the processing operation in the PAL mode will be described.
As shown in FIG. 9D, the color difference data in the PAL mode is thinned by half in the horizontal direction for Cr and Cb, and either one of Cr or Cb data exists alternately for each line. Further, the DCT block configuration of the color difference data is 8 pixels × 8 pixels as in the luminance data, and the capacity in the COL direction per bank is 512 bytes. Therefore, the burst length in one access is 64 bytes, similarly to the luminance data for Cr and Cb.

FIG. 11B shows bank 0 in the Cr / Cb region of FIG. 8 in the PAL mode.
Cr and Cb are divided by a row address. In this embodiment, a row address from 864 to 1079 is a Cr region, and a row address from 1080 to 1294 is a Cb region. CBL0 to CBL7 are column blocks divided into 64 / each Cr / Cb.

  Here, the access of 64 bytes of color difference data in both the writing / reading mode of Cr data is performed in the case of the even line shown in FIG. 9D. For example, in the case of Line 0, 64 bytes of Cr are transferred to CBL 0. Done. Each time the line transitions sequentially, the access area transitions to CBL7. This detailed processing operation will be described with reference to FIG.

FIG. 12 shows a state in which the Cr area in FIG. 11 is enlarged and actual screen image data is arranged on the memory.
Here, CBL0 to CBL7 are column blocks divided every 64 columns, and RN is the number of divisions of one horizontal line. As described above, the image data of one line in FIG. 9D is divided into six parts every 64 pixels, and the six blocks of Line 0 divided into the row direction (address) as shown in the CBL0 area of FIG. 0 to address 5) are sequentially stored. Similarly, Line2 is sequentially stored in the CBL1 area. The same applies to the image data of the remaining lines.

  Accordingly, the data of the 8n + 0th line (n is a positive number greater than or equal to 0) in FIG. 9D is sequentially stored in the CBL0 area, the 8n + 2th line in the CBL1 area, the 8n + 4th in the CBL2 area, In the CBL3 area, the data of the 8n + 6th, the CBL4 area, the 8n + 8th, the CBL5 area, the 8n + 10th, the CBL6 area, the 8n + 12th data, and the CBL7 area, the 8n + 14th data are sequentially stored. Become.

  As for the Cb area, although not shown, the CBL0 area sequentially stores the data of the 8n + 1th line (n is a positive number of 0 or more) in FIG. 9D, and the CBL1 area has the 8n + 3rd line. , 8n + 5th in the CBL2 area, 8n + 7th in the CBL3 area, 8n + 9th in the CBL4 area, 8n + 11th in the CBL5 area, 8n + 13th in the CBL6 area, and 8n + 15th in the CBL7 area. Data will be stored sequentially. Memory access at the time of encoding / decoding of the compression / decompression block 7 is accessed in the same manner as in the other modes, and processing of each desired 8 × 8 pixel DCT block is performed in Cr and Cb.

  Note that the Cr and Cb area division method shown in FIG. 11 is an example, and for example, Cr and Cb in FIG. 11A may be alternately divided in the col address direction in units of 32 bytes. That is, it is only necessary that Cr and Cb are divided by the col address, and continuous data corresponding to the burst length derived from the conditional expression (6) can be arranged on the same row address. In FIG. 11B, it is only necessary that Cr and Cb are divided by the row address, and continuous data corresponding to the burst length derived from the conditional expression (1) can be stored on the same row address.

It is a block diagram which shows embodiment of this invention. It is a block diagram for demonstrating the clock used by this invention. It is a detailed block diagram of an image input / output block. It is a timing chart which shows a multiplex and a demultiplex operation | movement. It is a block diagram for demonstrating the mapping of the memory space inside a buffer. It is a detailed timing diagram when writing multiplex data in a buffer. It is a detailed timing diagram when reading multiplex data from a buffer. It is a block diagram for demonstrating the mapping of the main memory space. It is a block diagram of one screen of luminance data in NTSC, color difference data, and luminance data in PAL. It is a block diagram which shows the example of a part of address of a main memory. It is a block diagram explaining the mapping with respect to the main memory of Cr and Cb. It is a block diagram for demonstrating the access means to the C area | region at the time of the PAL mode in the main memory of this invention.

Explanation of symbols

1, 2, 3 Input / output terminal 4 Image input / output block 5 Buffer 6 Main memory 7 Compression / decompression block 8 System control block Y Luminance signal Cr, Cb Color difference signal MUX-DATA Data string Y-MD Buffered luminance signal C -MD buffered color difference signal

Claims (1)

A first pixel having a luminance signal and two color difference signals, wherein the pixels of the two color difference signals are thinned out in the horizontal direction with respect to the pixels of the luminance signal, and the two color difference signals are present in each horizontal line; And a second image signal in which the pixels of the two color difference signals are thinned out in the horizontal direction with respect to the pixels of the luminance signal and one of the two color difference signals exists alternately for each horizontal line An image signal processing device for processing
A memory capable of burst writing and burst reading with respect to the same row address in synchronization with a clock, and storing the input first image signal and the second image signal;
Processing means for processing the first image signal or the second image signal stored in the memory in units of pixel blocks each having a plurality of pixels in the vertical direction and the horizontal direction;
Each of the horizontal lines of the luminance signal in the first image signal and the second image signal is divided into a plurality of luminance line blocks having a burst length when accessing the memory, and the horizontal lines of the two color difference signals are divided. Each of the luminance line block and the two color difference signals is divided into a plurality of color difference line blocks, and the luminance line block and the two color difference signals are arranged in the same row address in the memory so that the data of all the pixels in the same block are aligned. Comprising a control means for arranging color difference line blocks of two color difference signals;
The control means sets the horizontal line of the two color difference signals to the plurality of line blocks so that the color difference line blocks of the two color difference signals of the same horizontal line for the first image signal are combined to become the burst length. The color difference line blocks of the two color difference signals having the burst length in the same horizontal line are arranged at the same row address, and the color difference line block of the two color difference signals is the second image signal. Image signal processing characterized in that a horizontal line of the two color difference signals is divided into a plurality of line blocks so as to have the burst length, and the color difference line blocks of the two color difference signals are arranged at different row addresses. apparatus.

Images