JP3890658B2 - Sample hold circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sample and hold circuit having an operational amplifier (operational amplifier) in an input stage.
[0002]
[Prior art]
  Conventionally, for exampleIn FIG.As shown, the operational amplifier OP10, the analog switch SW1 connected to the output terminal of the operational amplifier OP10, and one end connected to the output terminal of the operational amplifier OP10 via the analog switch SW1 and to the inverting input terminal (−) of the operational amplifier OP10. A sample-and-hold circuit comprising a hold capacitor C10 whose other end is grounded and a buffer circuit comprising an operational amplifier OP11 for outputting the voltage of the hold capacitor C10 to the outside is known.
[0003]
In this type of sample and hold circuit, when the analog switch SW1 is in the ON state, the hold capacitor C10 is the same as the input signal Vin input to the non-inverting input terminal (+) of the operational amplifier OP10 by the operation of the operational amplifier OP10. When charged to the voltage level and the analog switch SW1 is turned off, charging of the hold capacitor C10 by the operational amplifier OP10 is stopped, and the voltage of the hold capacitor C10 is held.
[0004]
Therefore, the output signal Vout from the operational amplifier OP11 constituting the buffer circuit has the same voltage as the input signal Vin if the analog switch SW1 is in an on state, and when the analog switch SW1 is turned off, Held at a voltage level.
[0005]
[Problems to be solved by the invention]
By the way, in the conventional sample and hold circuit, the sample and hold of the input signal Vin is switched using the analog switch SW1 connected to the output terminal of the operational amplifier OP10. In order to incorporate the IC into the IC of the chip, a BiCMOS process is required for manufacturing the IC, and there is a problem in that the cost of the IC is increased. In other words, in the conventional sample and hold circuit, the operational amplifiers OP10 and OP11 can be easily configured using bipolar transistors, but the analog switch SW1 is usually configured by a MOS type FET. In order to incorporate it into the IC, a BiCMOS process is required for its manufacture, which increases the cost of the IC.
[0006]
On the other hand, in order to solve such a problem, the inventor of the present application cuts off the NPN transistor and the PNP transistor for output in the push-pull output circuit constituting the output stage of the operational amplifier OP10 at the time of holding, thereby reducing the input signal Vin. We considered switching between sample and hold in the operational amplifier OP10 without using the analog switch SW1.
[0007]
As a method for cutting off the output transistors (NPN transistor and PNP transistor) of the push-pull output circuit and opening the output in this way, for example, as described in Japanese Patent Publication No. 7-52816, By connecting the base of each transistor to the collector side of the other transistor through a resistor and stopping the operation of the constant current circuit that supplies a bias current to each transistor, each transistor is turned off, There is known a method of maintaining the off state by setting the base of a transistor to a low potential side potential and a high potential side potential of a DC power source to which the other collector is connected.
[0008]
In this way, since the sample and hold circuit can be realized without using the analog switch SW1 as in the prior art, it is possible to easily implement the sample and hold circuit as an IC.
However, when the output transistor in the operational amplifier OP10 is cut off in this way, there is no problem if the change of the input signal Vin at the time of holding is slow, but if the input signal Vin changes sharply, The phase compensation capacitor causes AC coupling, the signal is transmitted to the push-pull output circuit, and the voltage of the hold capacitor C10 fluctuates.
[0009]
The present invention has been made in view of such problems. In a sample-and-hold circuit that includes an operational amplifier in an input stage and is configured to charge a hold capacitor by the operation of the operational amplifier, an analog switch is used to switch between sample and hold. An object of the present invention is to ensure that the output can be held without being affected by the change of the input signal at the time of holding.
[0010]
[Means for Solving the Problems]
  In order to achieve this object, the invention according to claim 1 is characterized in that a holding capacitor whose one end is grounded to a reference potential, an output terminal and an inverting input terminal are connected to the other end of the holding capacitor, The operational amplifier that charges the capacitor to the voltage corresponding to the input signal to the non-inverting input terminal, the buffer circuit that outputs the charging voltage of the holding capacitor, and the hold command from the outside, when the hold command is received, the output of the operational amplifier is opened, A sample and hold circuit having an output open circuit for fixing an output from a buffer circuit, wherein the output open circuit is an NPN transistor and a PNP for output in a push-pull output circuit constituting an output stage of an operational amplifier according to a hold command Cut-off means to cut off each transistor and the same hole By a command,The connection between the differential amplifier constituting the input stage of the operational amplifier and the phase compensation capacitor provided in the operational amplifierAnd a potential fixing means for fixing the potential.
[0011]
  In the sample hold circuit of the present invention configured as described above, when a hold command is input from the outside, the cutoff means cuts off each transistor for output in the push-pull output circuit constituting the output stage of the operational amplifier. Moreover, the potential fixing means is a phase compensation capacitor.Differential amplifier side ofFix the potential.
[0012]
For this reason, even when the input signal input to the non-inverting input terminal of the operational amplifier changes sharply during hold, the signal is transmitted to each output transistor by AC coupling of the phase compensation capacitor. No, the output of the operational amplifier is always kept open.
[0013]
Therefore, according to the present invention, there is no need to provide an analog switch for making the output of the operational amplifier open between the operational amplifier and the hold capacitor as in the prior art. It can be surely prevented from fluctuating. Therefore, according to the present invention, a sample-and-hold circuit capable of obtaining stable hold characteristics can be configured without using a MOS type FET, and an IC can be easily achieved.
[0014]
  Here, as the potential fixing means, as described in claim 2Operational amplifierDirectly fix the connection between the differential amplifier and the phase compensation capacitor that make up the input stage at a predetermined potential.What is necessary is just to comprise.
[0016]
  The cut-off means only needs to be able to cut off each transistor of the push-pull output circuit at the time of holding command input. As the method, various conventionally known methods such as the method disclosed in the above-mentioned publication can be used. Method can be adopted, especiallyClaim 3As described, it is preferable that the base and emitter of each transistor for output constituting the push-pull output circuit are connected by resistors.
[0017]
That is, if the base-emitter of each transistor for output is connected with a resistor in this way, when each transistor is in the off state, the base-emitter is set to the same potential, and each transistor is connected to the operational amplifier. It is possible to prevent breakdown due to the input voltage from the hold capacitor connected to the output terminal. Therefore, even when the voltage of the hold capacitor connected to the output terminal (that is, the hold voltage) becomes high, each transistor can be reliably held in the off state at the time of holding.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Examples of the present invention will be described below.
First, FIG. 1 is a configuration diagram showing the overall configuration of an air-fuel ratio detection apparatus according to an embodiment having a sample hold circuit to which the present invention is applied.
[0019]
The air-fuel ratio detection device of this embodiment is for detecting the air-fuel ratio (A / F) of the fuel mixture supplied to the internal combustion engine from the oxygen concentration in the exhaust gas of the internal combustion engine. An A / F sensor 2 provided in the A / F sensor 2, a constant voltage output circuit 4 for applying a constant voltage AFC (for example, 3 V) to one end of the A / F sensor 2, And a drive voltage output circuit 6 for applying a drive voltage AFV for detecting internal resistance.
[0020]
Here, the A / F sensor 2 forms a sensor main body by forming a solid electrolyte such as zirconia into a cylindrical shape whose one end is closed, and forming porous electrodes on the inner and outer surfaces thereof. It is a well-known one that is installed in a predetermined housing so that the main body is placed in a diffusion chamber where the inflow of exhaust is restricted, and the outer electrode is exposed to the exhaust in the diffusion chamber and the atmosphere is introduced into the inner electrode. is there.
[0021]
In this A / F sensor 2, if a voltage is applied between the electrodes so that the voltage of the inner electrode is higher than that of the outer electrode, oxygen in the diffusion chamber is pumped into the atmosphere, and the solid electrolyte As the oxygen moves, current flows from the inner electrode to the outer electrode. As shown in FIG. 2, this current has a region that does not change with respect to a change in applied voltage between the electrodes, and the current (limit current) flowing in this region is the oxygen concentration in the exhaust gas (by extension). A / F).
[0022]
Therefore, in this embodiment, the constant voltage AFC is applied from the constant voltage output circuit 4 to one end (inner electrode) of the A / F sensor 2, and the other end (outer electrode) of the A / F sensor 2 from the drive voltage output circuit 6. Is applied with a driving voltage AFV (for example, 2.7 V) lower than the constant voltage AFC, whereby the A / F detection voltage Vp (= AFC) that allows a limit current to flow through the voltage across the A / F sensor 2. -AFV; for example, +300 mV), and the A / F is detected by measuring the limit current Ip flowing through the A / F sensor 2 at that time (see FIG. 2).
[0023]
The A / F sensor 2 can be activated at a predetermined temperature or higher to detect A / F, and the detection result changes depending on the temperature. Therefore, the A / F sensor 2 heats the sensor body. A heater (not shown) for controlling the temperature to a constant temperature (for example, 700 ° C.) is separately provided. In order to keep the sensor temperature at a predetermined temperature, it is necessary to detect the sensor temperature and control the amount of current flowing to the heater.
[0024]
Therefore, in this embodiment, in a state where the constant voltage AFC is applied from the constant voltage output circuit 4 to one end (inner electrode) of the A / F sensor 2, the drive voltage AFV is temporarily set to a voltage (for example, higher than the constant voltage AFC). 3.3V), and the voltage across the A / F sensor 2 is controlled to the internal resistance detection voltage Vn (for example, −300 mV) in the opposite direction to that at the time of A / F detection. By measuring the flowing current In, the internal resistance Rn (= Vn / In) of the A / F sensor 2 corresponding to the sensor temperature is calculated from the current In and the internal resistance detection voltage Vn ( (See FIG. 2).
[0025]
In addition, when a voltage in the opposite direction to that at the time of A / F detection is applied between the electrodes of the A / F sensor 2 in order to detect the internal resistance Rn in this way, the current flow is temporarily reversed in the inner direction. Oxygen is adsorbed on the electrode. For this reason, even after the internal resistance Rn is detected, even if the voltage application direction is restored to detect the A / F, the A / F cannot be accurately detected until there is no oxygen adsorbed on the inner electrode.
[0026]
Therefore, in the present embodiment, after the internal resistance Rn is detected, the drive voltage AFV is temporarily switched to a voltage (for example, 2.4 V) lower than that at the time of A / F detection, and between the electrodes of the A / F sensor 2. Detecting the A / F by discharging the oxygen adsorbed to the inner electrode quickly by applying a return voltage (for example, +600 mV) that is the same polarity as the A / F detection and larger than the A / F detection. To be able to return quickly.
[0027]
In the air-fuel ratio detection apparatus of this embodiment, in order to realize such A / F detection operation, internal resistance detection operation, and return operation, as shown in FIG. 1, switching of the drive voltage AFV and heater control are performed. The voltage output circuits 4 and 6 are configured as follows.
[0028]
That is, first, the voltage command value DAFV for driving voltage command output from the microcomputer 10 is input to the driving voltage output circuit 6 as an analog voltage signal via the D / A converter 8. In the drive voltage output circuit 6, the voltage signal from the D / A converter 8 is smoothed by an integrating circuit composed of a resistor R4 and a capacitor C1, and this is used as a drive voltage AFV to form a buffer circuit composed of an operational amplifier OP2. To the other end (outer electrode) of the A / F sensor 2 (see FIG. 3).
[0029]
The microcomputer 10 normally outputs a command value DAFV for controlling the drive voltage AFV to a voltage value for A / F detection, and is once (for example, 4.5 msec.) At a predetermined period (for example, 128 msec.). As a result, the command value DAFV and the drive voltage AFV are sequentially switched to the internal resistance detection and return voltage values.
[0030]
Further, the constant voltage output circuit 4 divides the power supply voltage Vb (for example, 5 V) to generate a reference voltage, and the voltage dividing resistors R1 and R2 and the non-inverting input terminal (+) are the power supply voltage Vb by the resistors R1 and R2. The inverting input terminal (−) is directly connected to one end (inner electrode) of the A / F sensor 2 and the output terminal is connected to one end (inner electrode) of the A / F sensor 2 via a resistor R3. And an operational amplifier OP1 connected to each other.
[0031]
Therefore, a voltage for controlling one end (inner electrode) of the A / F sensor 2 to the same voltage as the reference voltage generated by the resistors R1 and R2 is output from the output terminal of the operational amplifier OP1. One end of 2 is controlled to the same constant voltage AFC as the reference voltage. At this time, since the same current as the current flowing through the A / F sensor 2 flows through the resistor R3, and the output terminal voltage of the operational amplifier OP1 corresponds to the current flowing through the A / F sensor 2, in this embodiment, This voltage is used as a detection voltage Vs for A / F or internal resistance (see FIG. 3).
[0032]
The microcomputer 10 takes in the detection voltage Vs obtained when the drive voltage AFV is controlled to the internal resistance detection voltage for heater control via the A / D converter 12 and detects the detection voltage Vs. The current In {= (AFC−Vs) / R3} flowing through the A / F sensor 2 is calculated from the voltage Vs, the resistance value of the resistor R3, and the constant voltage AFC applied to the A / F sensor 2, and this The internal resistance Rn (= Vn / In) of the A / F sensor 2 is calculated from the current In and the internal resistance detection voltage Vn so that the internal resistance Rn becomes a predetermined value (in other words, the sensor temperature is a predetermined temperature). The current applied to the heater is controlled.
[0033]
On the other hand, the detection voltage Vs obtained when the drive voltage AFV is controlled to the voltage for A / F detection corresponds to the limit current (and thus A / F) that has flowed to the A / F sensor 2. Therefore, it is necessary to output this detection voltage Vs to a control device that controls the amount of fuel supplied to the internal combustion engine. However, if this detection voltage Vs is directly output to the control device of the internal combustion engine, the detection voltage Vs does not correspond to A / F when the internal resistance of the A / F sensor 2 is detected or when it is subsequently recovered. A / F cannot be controlled accurately.
[0034]
Therefore, the air-fuel ratio detection device of this embodiment is provided with a sample hold circuit 14 as a circuit for outputting the detection voltage Vs to the control device of the internal combustion engine, and at the time of A / F detection, the detection voltage Vs is used as it is. The detection signal AFO is output to the control device, and when the internal resistance is detected or subsequently recovered, the voltage value obtained by holding the detection voltage Vs at the time of A / F detection is output to the control device as the detection signal AFO. Yes.
[0035]
In order to realize such a sample / hold operation, a sample / hold switching signal S / H is input to the sample / hold circuit 14 from the microcomputer 10, and the sample / hold circuit 14 has a low switching signal S / H. When it is at the level, the detection voltage Vs output until then is held (see FIG. 3).
[0036]
Next, as shown in FIG. 1, the sample and hold circuit 14 of the present embodiment includes two operational amplifiers OP3 and OP4 and a hold capacitor C2.
The operational amplifier OP3 incorporates the output open circuit of the present invention. The output terminal is connected to one end of the hold capacitor C2 and is connected to the inverting input terminal (−) and the non-inverting input terminal (+). Is connected to the output terminal of the operational amplifier OP1 and receives the detection voltage Vs. The other end of the hold capacitor C2 is grounded to the ground of the air-fuel ratio detection device.
[0037]
On the other hand, the operational amplifier OP4 is a buffer circuit for outputting the voltage across the holding capacitor C2 (charging voltage) as an A / F detection signal AFO to the control device of the internal combustion engine, and a non-inverting input terminal (+). Is connected to the output terminal of the operational amplifier OP3, and the inverting input terminal (−) is connected to the output terminal.
[0038]
The operational amplifier OP3 receives the sample / hold switching signal S / H output from the microcomputer 10, and operates as a general operational amplifier OP3 when sampling the detection voltage Vs at which the switching signal S / H is at a high level. Then, a signal Vo having the same voltage as the detection voltage Vs is output from the output terminal to the hold capacitor C2 and the operational amplifier OP4. When the detection voltage Vs at which the switching signal S / H is at the low level is held, the push constituting the output stage is performed. The output transistor of the pull output circuit is cut off, and the output is opened.
[0039]
  As a result, at the time of holding, the operational amplifier OP4 outputs the voltage charged in the holding capacitor C2 at the time of sampling, and the detection signal AFO output to the control device is held at the voltage value at the time of sampling.
  Hereinafter, the configuration and operation of the operational amplifier OP3 which is the main part of the present invention will be described.To do.
[0040]
  As shown in FIG.Of this exampleThe operational amplifier OP3 includes a power supply terminal to which the power supply voltage Vb on the high potential side of the DC power supply is applied, and a ground terminal grounded to the low potential side (ground; GND) of the DC power supply. Operates by receiving supply. The operational amplifier OP3 includes a differential amplifier 50 in the input stage, a common emitter amplifier 60 that amplifies the output from the differential amplifier 50 in the next stage, and a push-pull output circuit 70 in the output stage. The operational amplifier OP3 has an input terminal to which a switching signal S / H from the microcomputer 10 is input, and a low-level switching signal S / H to be a hold command is input to this input terminal, the push-pull output circuit And an output open circuit 80 for opening 70 outputs.
[0041]
First, the differential amplifier 50 has an emitter connected to a power supply line (power supply voltage Vb) via a resistor R50, and a base connected to a control terminal that receives a control signal Vc for current control from the outside. A PNP transistor Tr50 that outputs a constant current corresponding to the control signal Vc from two collectors is provided. The PNP transistor Tr50 serves as a constant current source for the differential amplifier 50.
[0042]
The differential amplifier 50 includes the following eight transistors.
A PNP transistor Tr51 whose base is connected to the inverting input terminal (-input) via the resistor R51, whose emitter is connected to the first collector of the PNP transistor Tr50, and whose collector is grounded.
[0043]
A PNP transistor Tr52 whose base is connected to the emitter of the PNP transistor Tr51 and whose emitter is connected to the second collector of the PNP transistor Tr50.
A PNP transistor Tr53 whose base is connected to the non-inverting input terminal (+ input) via the resistor R52, whose emitter is connected to the third collector of the PNP transistor Tr50, and whose collector is grounded.
[0044]
A PNP transistor Tr54 whose base is connected to the emitter of the PNP transistor Tr53 and whose emitter is connected to the second collector of the PNP transistor Tr50 together with the emitter of the PNP transistor Tr52.
A PNP transistor Tr55 having an emitter connected to the fourth collector of the PNP transistor Tr50, a base connected to the collector of the PNP transistor Tr52, and a collector grounded.
[0045]
A PNP transistor Tr56 whose emitter is connected to the fifth collector of the PNP transistor Tr50, whose base is connected to the collector of the PNP transistor Tr54, and whose collector is grounded.
An NPN transistor Tr57 whose collector is connected to the collector of the PNP transistor Tr52 (and hence the base of the PNP transistor Tr55), whose emitter is connected to the ground line, and whose base is connected to its own collector.
[0046]
The collector is connected to the collector of the PNP transistor Tr54 (and thus the base of the PNP transistor Tr56), the emitter is connected to the ground line, the base is connected to the base of the NPN transistor Tr57, and the current mirror together with the NPN transistor Tr57. NPN transistor Tr58 constituting the circuit.
[0047]
On the other hand, the common emitter amplifier 60 has a PNP transistor Tr61 for outputting a constant current from a collector with an emitter connected to the power supply line, a base connected to the base of the PNP transistor Tr50, and a base connected to the base of the PNP transistor Tr56. The NPN transistor Tr63 is connected to the emitter, the collector is connected to the collector of the PNP transistor Tr61, the emitter is connected to the ground line via the resistor R61, and the base is connected to the emitter of the NPN transistor Tr63. Is connected to the ground line, the collector is connected to the base of the PNP transistor Tr56 via the phase compensation capacitor C61, the collector of the NPN transistor Tr63 and the And a pair of diodes D61, D62 Prefecture connected in series as a cathode ground side between the-line.
[0048]
That is, the operational amplifier shown in FIG. 4 inputs signals from the inverting input terminal (−input) and the non-inverting input terminal (+ input) through the PNP transistors Tr51 and Tr52 and Tr53 and Tr54 connected in Darlington connection, respectively. In addition, the NPN transistor Tr64 serving as a signal output unit of the common emitter amplifier 60 has a collector input to the inverting input terminal and the non-inverting input terminal. A voltage corresponding to the signal potential difference is generated.
[0049]
Next, the push-pull output circuit 70 is a signal (Vo) output transistor, a first NPN transistor Tr71 having a collector connected to the power supply line and an emitter connected to the output terminal, and a collector connected to the ground line. And a PNP transistor Tr72 whose emitter is connected to the output terminal. Resistors R71 and R72 are connected between the base and emitter of the NPN transistor Tr71 and between the base and emitter of the PNP transistor Tr72, respectively.
[0050]
A pair of diodes D71 and D72 connected in series is provided between the base of the NPN transistor Tr71 and the base of the PNP transistor Tr72. These diodes D71 and D72 are used for holding the voltage between the bases of the transistors Tr71 and Tr72 at a forward voltage (about 1.4 V) corresponding to two diodes capable of operating the transistors Tr71 and Tr72 when a bias current is supplied. The anodes are connected to each other in the forward direction so that the anode is on the base side of the NPN transistor Tr71 and the cathode is on the base side of the PNP transistor Tr72.
[0051]
The base of the PNP transistor Tr72 is connected to the collector of an NPN transistor Tr64 that is an output transistor of the common emitter amplifier 40, and the output from the common emitter amplifier 40 is input to the base of the PNP transistor Tr72.
[0052]
Next, in order to supply a bias current for driving the NPN transistor Tr71 and the PNP transistor Tr72 between the base of the NPN transistor Tr71 and the power supply line, an emitter is connected to the power supply line, and a collector is connected to the NPN transistor Tr71. A PNP transistor Tr73 connected to the base is provided. The base of the PNP transistor Tr74 is connected to the base of the PNP transistor Tr73.
[0053]
The PNP transistor Tr74 forms a current mirror circuit together with the PNP transistor Tr73. The emitter of the PNP transistor Tr74 is connected to the power supply line, and the collector is connected to its own base. Further, the bases of the PNP transistors Tr73 and Tr74 are connected to the power supply line via the resistor R73.
[0054]
The collector of the PNP transistor Tr74 is connected to the collector of an NPN transistor Tr75 whose emitter is connected to the ground line, and the base of the NPN transistor Tr75 is connected to the base of the NPN transistor Tr76. The emitter of the NPN transistor Tr76 is connected to the ground line, the collector is connected to its own base, and the emitter is connected to the collector of the PNP transistor Tr78 connected to the power supply line. The base of the PNP transistor Tr78 is connected to a control terminal that receives a control signal Vc for current control from the outside, together with the bases of the PNP transistor Tr50 in the differential amplifier 50 and the PNP transistor Tr61 in the common emitter amplifier 60. .
[0055]
As a result, the PNP transistor Tr78 functions as a constant current source that supplies a constant current from the power supply line to the NPN transistor Tr76, and a constant current flows through the NPN transistor Tr76. In addition, since the NPN transistor Tr76 and the NPN transistor Tr75 constitute a current mirror circuit, the same constant current as that of the NPN transistor Tr76 flows through the NPN transistor Tr75. The same constant current flows.
[0056]
  Next, the output open circuit 80 is an inverter INV for inverting the high / low level of the switching signal S / H from the microcomputer 10.When,NPN transistor Tr1, Tr4And these transistors Tr1, Tr4Connect the base and the output of the inverter INVRuAnti-R81, 84And is composed of.
[0057]
  The collector of the NPN transistor Tr1 is connected to the collector of the NPN transistor Tr76 in the push-pull output circuit 70, and the emitter is connected to the emitter of the NPN transistor Tr76.The NPN transistor Tr4 has a collector connected to the base of the PNP transistor Tr56 in the differential amplifier 50, an emitter grounded to the ground line, and a base connected to the output of the inverter INV via the resistor R84.
[0058]
  In the operational amplifier OP3 of the present embodiment configured as described above, when the high level switching signal S / H is input from the microcomputer 10 (that is, during sampling), the NPN transistor Tr1 is turned off. The NPN transistors Tr75 and Tr76 and the PNP transistors Tr74 and Tr73 each function as a current mirror circuit and supply a base current to the output NPN transistor Tr71. Also,At the time of sample,NPN transistorTr4Can also be turned offOThe pair amplifier OP3 normally operates, and a signal Vo having the same potential as the detection voltage Vs is output from its output terminal.
[0059]
  On the other hand, when the switching signal S / H from the microcomputer 10 becomes a low level (that is, during holding), the NPN transistor Tr1 is turned on, and a constant current supplied from the PNP transistor Tr78 is supplied to the ground line side. The current flowing through the current mirror circuit composed of Tr75 and Tr76 and the current mirror circuit composed of PNP transistors Tr74 and Tr73, in other words, the base current of the PNP transistor Tr71 for output is cut off.At the time of holding, the NPN transistor Tr4 is turned on, and the differential amplifier 50 side of the phase compensation capacitor C61 is grounded to the ground line via the NPN transistor Tr4.
[0061]
  Thus, this exampleIn the operational amplifier OP3,In FIG.As shown in the figure, at the time of holding, not only the output transistors Tr71 and 72 are cut off to open the output, but also the NPN transistorBy Tr4Since the potential A on the differential amplifier 50 side of the phase compensation capacitor C61 is fixed, even if the detection voltage Vs changes sharply due to a change in the drive voltage AFV of the A / F sensor 2 during holding, the phase compensation capacitor C61. AC couplingAndThe change of the detection voltage Vs is not transmitted to the push-pull output circuit 70 side (see potential B) of the phase compensation capacitor C61, and the output signal Vo (in other words, the potential of the hold capacitor C2) does not change. The potential of the holding capacitor C2 can be reliably held.
[0062]
Therefore, according to the sample and hold circuit 14 of the present embodiment, there is no need to provide an analog switch for opening the output of the operational amplifier between the operational amplifier in the input stage and the hold capacitor C2 as in the prior art. In addition, it is possible to reliably prevent the output voltage (detection signal AFO) from changing during holding. Therefore, according to the present embodiment, a sample hold circuit capable of obtaining a stable hold characteristic can be configured without using a MOS type FET, and the entire air-fuel ratio detection apparatus excluding the sample hold circuit 14 and the A / F sensor 2 can be constructed. It is possible to easily achieve the IC.
[0063]
In this embodiment, since the resistors R71 and R72 are provided between the base and emitter of the output transistors Tr71 and Tr72 in the operational amplifier OP3, when the transistors Tr71 and Tr72 are in the off state, the base- Even when the potential between the emitters is set to the same level and the high voltage is held in the phase compensation capacitor C61 connected to the output terminal of the operational amplifier OP3, the transistors Tr71 and Tr72 can be prevented from breaking down.
[0064]
Furthermore, in this embodiment, the bases of the PNP transistors Tr74 and Tr73 constituting the current mirror circuit in the push-pull output circuit 70 are connected to the power supply line via the resistor R73. Even if a leak current flows, the PNP transistor Tr73 does not operate and a bias current does not flow to the NPN transistor Tr71 side. That is, in this embodiment, a more stable open state can be held at the time of holding by the resistor R73 provided in the current mirror circuit.
[0069]
  BookIn the embodiment, the NPN transistor Tr1 functions as a cutoff means, and the NPN transistor Tr4 functions as a potential fixing means.The
[0070]
As mentioned above, although the Example of this invention was described, this invention is not limited to the said Example, A various aspect can be taken.
For example, in the above embodiment, as the operational amplifier OP3 constituting the input stage of the sample and hold circuit, the signals from the inverting input terminal and the non-inverting input terminal are input via the PNP transistors Tr51, Tr52 and Tr53, Tr54 connected in Darlington, respectively. In the above description, the operational amplifier including the differential amplifier configured to perform the operation and the phase compensation capacitor C61 is taken as an example. However, the present invention can be applied to any type of operational amplifier. For example, the present invention can be applied to an operational amplifier to which a phase compensation capacitor is externally attached.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating the overall configuration of an air-fuel ratio detection apparatus according to an embodiment.
FIG. 2 is an explanatory diagram for explaining operations of A / F detection and internal resistance detection in the air-fuel ratio detection apparatus according to the embodiment.
FIG. 3 is a time chart for explaining signal waveforms of respective parts of the air-fuel ratio detection device according to the embodiment.
4 is an operational amplifier OP3 constituting the sample and hold circuit shown in FIG.StructureIt is an electric circuit diagram showing composition.
[Figure 5] It is explanatory drawing explaining the voltage A and B of the both ends of the capacitor | condenser for phase compensation of operational amplifier OP3, and the output signal Vo.
[Fig. 6] It is explanatory drawing showing the structure of the conventional sample hold circuit using an operational amplifier.
[Explanation of symbols]
  14 ... Sample and hold circuit,OP3 ... Operational amplifier,C2: Hold capacitor,OP4 ... Operational amplifier (buffer circuit),50 ... Differential amplifier,60 ... Common emitter amplifier,70. Push-pull output circuit,80 ... Output open circuit,C61: Phase compensation capacitor.

Claims (3)

A holding capacitor with one end grounded to a reference potential;
An operational amplifier that connects an output terminal and an inverting input terminal to the other end of the hold capacitor, and charges the hold capacitor to a voltage corresponding to an input signal to the non-inverting input terminal;
A buffer circuit for outputting a charging voltage of the holding capacitor;
When receiving a hold command from the outside, the output of the operational amplifier is opened, and an output open circuit that fixes the output from the buffer circuit;
A sample hold circuit comprising:
The output open circuit;
Cut-off means for cutting off each of the output NPN transistor and PNP transistor in the push-pull output circuit constituting the output stage of the operational amplifier according to the hold command;
In accordance with the hold command, a potential fixing means for fixing a potential of a connection portion between a differential amplifier constituting an input stage of the operational amplifier and a phase compensation capacitor provided in the operational amplifier;
A sample-and-hold circuit comprising:   2. The sample hold circuit according to claim 1, wherein the potential fixing means directly fixes a connection portion between the differential amplifier and the phase compensation capacitor at a predetermined potential.   3. The sample and hold circuit according to claim 1, wherein the push-pull output circuit includes resistors connected between bases and emitters of the NPN transistor and the PNP transistor.

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