JP3901681B2 - Semiconductor device and its mounting structure - Google Patents

Description

  The present invention relates to a semiconductor device having a bump electrode on a pad electrode of a semiconductor substrate and a mounting structure thereof, and particularly to a semiconductor device having a bump electrode suitable for mounting on an insulating substrate through an anisotropic conductive material, and the semiconductor device. It relates to the mounting structure.

  For example, as one method for mounting a semiconductor device on a liquid crystal display device, there is COG (Chip On Glass) mounting in which the semiconductor device is directly mounted on a liquid crystal glass panel. COG mounting is a mounting method in which a bump electrode formed of gold or the like is placed on a pad electrode of a semiconductor device and an electrode of a glass substrate so as to face each other, and an electrical force is applied while applying an external force such as heat or pressure. It is.

  As an electrical bonding method between a bump electrode of a semiconductor device and an electrode of a glass substrate in COG mounting, an anisotropic conductive film (ACF: 3 μm or 5 μm) in which conductive particles of several μm such as 3 μm or 5 μm are mixed in an adhesive binder. There is a system using Anisotropic Conductive Film). The COG mounting using the ACF is arranged such that the bump electrode of the semiconductor device and the electrode of the glass substrate face each other via the ACF, and the conductive particles in the adhesive binder are bumped by heating and pressing. The bump electrode and the glass substrate electrode are electrically joined by being crushed between the electrode and the glass substrate electrode.

7 and 8 show a COG mounting structure of a conventional semiconductor device using an ACF and a glass substrate.
That is, a gold bump (an example of a bump electrode) 5 is formed on the barrier metal 4 on the pad electrode 2 of the semiconductor substrate 1 through the opening 3 a of the passivation film 3. An electrode 7 of a glass substrate 6 (an example of an insulating substrate) is disposed so as to face the gold bump 5, and the gold bump 5 and the electrode 7 are bonded by being pressed and heated by the tool 10 and the stage 11. Electrically bonded by conductive particles 9 mixed in the agent binder 8.

  Here, if the size (diameter) of the conductive particles 9 used for COG mounting is about 4 μm, the conductive particles 9 must be at least assured of the electrical minimum connection between the gold bumps 5 and the electrodes 7. However, 3 to 4 conductive particles 9 are sandwiched between the gold bumps 5 and the electrodes 7 and are required to be crushed until they are deformed by about 20% of the diameter of the conductive particles 9. Further, assuming that the area of the top of the gold bump 5 facing the electrode 7 side is about 3000 μm ↑ 2, when an ACF 12 having a standard particle density is used, 20 to 30 conductive particles 9 are formed from the gold bump 5 and the electrode 7. It is sandwiched between.

  On the other hand, when COG mounting is performed, due to the flatness of the pressure tool 10 and the stage 11, the thickness variation of the semiconductor substrate 1, the height variation of the gold bump 5 itself, and the like, between the individual gold bumps 5. The contact state between the gold bump 5 and the electrode 7 of the glass substrate 6 varies. That is, according to the COG mounting under the conditions that we use experimentally, the top of the gold bump 5 is in complete contact with the electrode 7 as shown in FIG. As shown in FIG. 8A, a gap of about 2 μm is generated between the gold bump 5 and the electrode 7.

  Further, although the gold bump 5 is formed by electrolytic plating, when formed by electrolytic plating, a concave portion 5a is formed on the surface S of the top of the gold bump 5 facing the electrode 7 side. This is because the growth in the thickness direction of the electrolytic plating is performed uniformly, so that the concave / convex shape of the opening 3a of the passivation film 3 which is the base is reflected as it is, but the depth (step) of the concave portion 5a is 1. When the thickness is 2 μm or more, the gap between the electrode 7 shown in FIG. 8A and the bottom surface of the recess 5 a is 3.2 μm (= 2 + 1.2) or more, which corresponds to 80% of the diameter 4.0 μm of the conductive particles 9. 3.2 μm or more. That is, the amount of crushing of the conductive particles 9 is 20% or less, which is the minimum amount of crushing that allows electrical conduction, and thus there is a problem that the conductive particles 9 located in the recess 5a do not contribute to electrical connection. is there.

In order to solve such a problem, the planar area of the opening 3a of the passivation film 3 (that is, the area of the surface of the gold bump 5 facing the semiconductor substrate 1) (that is, the planar area of the gold bump 5) Patent Document 1 discloses a semiconductor device in which the planar area of the recess 5a (dimple) formed in the gold bump 5 is reduced by reducing the opening area.
Japanese Patent Laid-Open No. 11-31698 (pages 3-5, FIG. 5)

  According to Patent Document 1, by setting the planar area of the opening 3 a of the passivation film 3 to 1/9 or less with respect to the planar area of the gold bump 5, the conductive particles 9 that do not contribute to electrical bonding can be obtained. The ratio is decreasing. Further, the depth of the concave portion 5a of the gold bump 5 can be made shallower than that of the conventional structure by reducing the planar area of the opening 3a to some extent.

  For example, the thickness of the passivation film 3 in Patent Document 1 is 1 μm. On the other hand, even when the planar area of the opening 3 a is reduced, the thickness is 0.5 to 0.8 μm at the maximum (that is, the thickness of the passivation film 3 is A recess 5a having a depth of 50 to 80% is generated. However, with the recent miniaturization of the wiring of the semiconductor substrate 1, the number of layers and the material of the passivation film 3 are also reviewed, and as a result, the thickness of the passivation film 3 tends to increase. That is, the thickness of the passivation film 3 is about 1.2 to 1.8 μm, and even when the planar area of the opening 3a of the passivation film 3 is reduced as shown in Patent Document 1, 0.6 ( = 1.2 × 50%) to 1.4 (= 1.8 × 80%) It can be easily imagined that the concave portion 5a having a depth of about μm is generated on the surface of the gold bump 5. That is, a concave portion 5a having a depth of 1.2 μm or more is generated in the gold bump 5, and the conductive particles 9 corresponding to the concave portion 5a do not contribute to electrical bonding.

  Further, with the narrowing of the pitch of the gold bumps 5 and the reduction of the gold bumps 5, the use of conductive particles 9 having a smaller size than the conventional ones has been studied. The depth of 5a has become increasingly detrimental to COG implementation.

  In order to solve the above-described problem, it is considered effective to reduce the depth (step) of the recess 5a, for example. For this purpose, it is necessary to reduce the thickness of the opening 3a of the passivation film 3. There is. However, when the thickness of the opening 3a is reduced, the mechanical strength thereof is weakened. Therefore, the passivation film 3 is cracked from the opening 3a due to the stress of pressurization and heating applied during mounting, and the semiconductor device There is a problem that the reliability of A itself is adversely affected.

  The present invention reduces the depth (step) of the concave portion that can be formed in the bump electrode while preventing cracks in the passivation film, and also has a structure in which the depth of the concave portion itself can be ignored, so that the electrical conductivity of the conductive particles can be reduced. It is an object of the present invention to provide a semiconductor device capable of stably performing bonding and a mounting structure thereof.

To achieve the above object, the first invention provides a semiconductor substrate on which a plurality of pad electrodes are formed,
A passivation film provided on the semiconductor substrate;
A semiconductor device having a bump electrode formed on the pad electrode through a barrier metal,
An opening for opening at least a part of the pad electrode is formed in the passivation film,
The area of the opening of the passivation film on the semiconductor substrate side is larger than the area of the bump electrode, and the area of the bump electrode is formed larger than the area of the pad electrode,
The barrier metal covers a portion of the pad electrode exposed from the opening of the passivation film.

  According to this, the bump electrode can be arranged without overlapping the passivation film, the shape of the opening of the passivation film does not appear on the surface of the bump electrode opposite to the semiconductor substrate, and the bump electrode Since there is no opening of the passivation film between the semiconductor substrate and the semiconductor substrate, cracks in the passivation film due to stress during mounting do not occur. Here, a convex portion reflecting the shape of the pad electrode appears on the surface of the bump electrode opposite to the semiconductor substrate. Generally, the thickness of the pad electrode is 0.8 μm or less, which is smaller than that of the passivation film. Since it is sufficiently thin, the level difference of the convex portion appearing on the bump electrode is also suppressed to 0.8 μm or less, and this does not cause a particular problem in COG mounting. In addition, since the barrier metal having good adhesion to the semiconductor substrate and the pad electrode is formed so as to cover the pad electrode, the pad electrode is compared with the conventional structure even if the pad electrode is exposed from the passivation film. There is no deterioration in strength and chemicals.

In the second invention, the area of the pad electrode on the semiconductor substrate side is 1/9 or less of the area of the bump electrode.
According to this, the area of the convex portion reflecting the shape of the pad electrode appearing on the surface opposite to the semiconductor substrate of the bump electrode is reduced, and can be easily crushed by the pressure of normal COG mounting. The step height can be ignored during COG mounting. Therefore, it is possible to further reduce the influence of the convex portion appearing on the bump electrode.

In the third invention, the thickness of the pad electrode is 0.4 μm or less.
Further, the fourth invention provides a semiconductor substrate on which a plurality of pad electrodes are formed,
A passivation film provided on the semiconductor substrate;
A semiconductor device having a bump electrode formed on the pad electrode through a barrier metal,
An opening for opening at least a part of the pad electrode is formed in the passivation film,
The area of the bump electrode on the semiconductor substrate side is larger than the area of the opening of the passivation film, and the area of the opening of the passivation film is formed larger than the area of the pad electrode,
A portion of the pad electrode exposed from the opening of the passivation film is covered with a barrier metal ,
The distance from the periphery of the opening of the passivation film to the pad electrode is 2 μm or less .

  According to this, it is possible to form the pad electrode inside the region of the opening of the passivation film without overlapping the passivation film and the pad electrode. A concave portion reflecting the shape of the opening of the passivation film and a convex portion reflecting the shape of the pad electrode located inside the opening are formed on the surface of the bump electrode opposite to the semiconductor substrate. As a result, the step of the concave portion is filled (filled) with the step of the convex portion inside the concave portion, so that the depth of the concave portion becomes shallower, which is opposite to the semiconductor substrate of the bump electrode compared to the conventional structure. The influence of the recessed part which generate | occur | produces in the side surface can be made small.

Further, the depth of the concave portion of the bump electrode can be made smaller than the depth of the concave portion of the conventional bump electrode.

Further, the fifth invention provides a semiconductor substrate on which a plurality of pad electrodes are formed,
A passivation film provided on the semiconductor substrate;
A semiconductor device having a bump electrode formed on the pad electrode through a barrier metal,
An opening for opening at least a part of the pad electrode is formed in the passivation film,
The area of the bump electrode on the semiconductor substrate side is larger than the area of the opening of the passivation film, and the area of the opening of the passivation film is formed larger than the area of the pad electrode,
A portion of the pad electrode exposed from the opening of the passivation film is covered with a barrier metal,
The pad electrode is thinner than the passivation film, the difference between the thicknesses of the passivation film of the pad electrode is not more 0.4μm or less.
According to this, it is possible to form the pad electrode inside the region of the opening of the passivation film without overlapping the passivation film and the pad electrode. A concave portion reflecting the shape of the opening of the passivation film and a convex portion reflecting the shape of the pad electrode located inside the opening are formed on the surface of the bump electrode opposite to the semiconductor substrate. As a result, the step of the concave portion is filled (filled) with the step of the convex portion inside the concave portion, so that the depth of the concave portion becomes shallower, which is opposite to the semiconductor substrate of the bump electrode compared to the conventional structure. The influence of the recessed part which generate | occur | produces in the side surface can be made small.
Further, the step between the concave portion formed in the bump electrode and the convex portion inside the concave portion can be made 0.4 μm or less.

The sixth invention is a mounting structure in which a semiconductor device is mounted on an insulating substrate,
The semiconductor device has a semiconductor substrate on which a plurality of pad electrodes are formed, a passivation film provided on the semiconductor substrate, and a bump electrode formed on the pad electrode via a barrier metal,
An opening for opening at least a part of the pad electrode is formed in the passivation film,
The area of the opening of the passivation film on the semiconductor substrate side is larger than the area of the bump electrode, and the area of the bump electrode is formed larger than the area of the pad electrode,
The barrier metal covers a portion of the pad electrode exposed from the opening of the passivation film,
The insulating substrate has an electrode disposed at a position facing the bump electrode;
An anisotropic conductive material is interposed between and electrically connected at least between the bump electrode of the semiconductor device and the electrode of the insulating substrate.

  According to this, the bump electrode can be arranged without overlapping the passivation film, the shape of the opening of the passivation film does not appear on the surface of the bump electrode facing the electrode of the insulating substrate, and the bump electrode and Since there is no opening of the passivation film between the semiconductor substrate and the semiconductor substrate, cracks in the passivation film due to stress during mounting do not occur. Here, a bump reflecting the shape of the pad electrode appears on the surface of the bump electrode that faces the electrode of the insulating substrate. Generally, the thickness of the pad electrode is 0.8 μm or less, which is smaller than that of the passivation film. Since it is sufficiently thin, the level difference of the convex portion appearing on the bump electrode is also suppressed to 0.8 μm or less, and this does not cause a particular problem in COG mounting. In addition, since the barrier metal having good adhesion to the semiconductor substrate and the pad electrode is formed so as to cover the pad electrode, the pad electrode is compared with the conventional structure even if the pad electrode is exposed from the passivation film. There is no deterioration in strength and chemicals.

  According to the present invention, while preventing cracks in the passivation film, the steps of the bumps or recesses that can be formed into the bump electrodes are made shallow, and the steps can be ignored, thereby electrically connecting the conductive particles. It becomes possible to carry out stably.

(Embodiment 1)
1 and 2 are sectional views of a mounting structure in which the semiconductor device A according to the first embodiment is mounted on a glass substrate 6 (an example of an insulating substrate). In addition, about the same member as the conventional one demonstrated previously, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  A plurality of pad electrodes 2 (for example, aluminum pads) are formed on the main surface of the semiconductor substrate 1 of the semiconductor device A, and gold bumps 5 (an example of bump electrodes) so as to cover the pad electrodes 2. Is formed through a barrier metal 4 made of TiW, Ti, Cr or the like. A passivation film 3 made of silicon nitride, silicon oxide or the like is formed on the semiconductor substrate 1 so as not to overlap the gold bumps 5. The gold bump 5 is formed on the main surface of the semiconductor substrate 1 on which the pad electrode 2 and the passivation film 3 are formed in advance by a photolithography technique. That is, after a barrier metal such as TiW and an Au seed layer are formed by sputtering or the like, a plating resist is applied and thermally cured, and then exposed and developed to open positions where gold bumps 5 can be formed. Next, after the gold is grown by electrolytic gold plating, the plating resist that has become unnecessary is peeled off. Finally, it is obtained by removing unnecessary barrier metal and seed layer by etching. If necessary, heat treatment such as annealing is performed.

  The passivation film 3 is formed with an opening 3 a that opens at least a part of the pad electrode 2. The area of the opening 3 a is larger than the area of the surface of the gold bump 5 facing the semiconductor substrate 1, and the area of the surface of the gold bump 5 facing the semiconductor substrate 1 is larger than the area of the pad electrode 2. ing. The barrier metal 4 covers a portion of the pad electrode 2 exposed from the opening 3 a of the passivation film 3.

  The glass substrate 6 has an electrode 7 disposed at a position facing the gold bump 5. The electrode 7 and the gold bump 5 are formed by first arranging an ACF 12 (an example of an anisotropic conductive material) composed of conductive particles 9 and an adhesive binder 8 between the semiconductor substrate 1 and the glass substrate 6, After aligning 5 and the electrode 7 so as to face each other, the tool 10 and the stage 11 are joined by pressurization and heating. At this time, as shown in FIG. 2B, electrical joining is performed by crushing the conductive particles 9. In other words, the narrower and flatter the gap between the electrode 7 and the gold bump 5, the more reliable the bonding can be obtained. The tool 10 and the stage 11 are jigs used for COG mounting and are not particularly required after mounting.

Hereinafter, the operation of the above configuration will be described.
Conventionally, the passivation film 3 is formed so as to cover the pad electrode 2 (see FIG. 8), and the greatest purpose thereof is the adhesion strength between the pad electrode 2 and the underlying interlayer film (not shown). This prevents the pad electrode 2 from peeling off due to physical damage when performing wire bond bonding or the like. On the other hand, in the case of the first embodiment, as shown in FIG. 2, the barrier metal 4 covers the pad electrode 2 and has sufficient adhesion with the base, and COG mounting is performed. Since the physical damage at the time is buffered by the gold bump 5 and applied to the pad electrode 2, the damage is much weaker than the physical damage when the wire bond mounting is directly performed on the pad electrode 2, so that the adhesion strength is increased. Sufficient reliability can be obtained.

  Further, since the opening 3 a of the passivation film 3 is made larger than the gold bump 5 and the gold bump 5 is formed so as not to cover the passivation film 3, the gold bump 5 faces the electrode 7 of the glass substrate 6. The surface S (the surface opposite to the semiconductor substrate 1) is not formed reflecting the shape of the opening 3 a of the passivation film 3. Instead, the surface S of the gold bump 5 has a pad A convex portion 5b reflecting the shape of the electrode 2 appears. However, in general, the thickness of the pad electrode 2 is about 0.8 μm, which is sufficiently thinner than the passivation film 3 having a thickness of about 1 μm to 1.8 μm. As shown in FIG. 7A, the level difference is very shallow compared to the concave portion 5a that appears due to the influence of the opening 3a of the conventional passivation film 3. Therefore, reliable bonding can be obtained as compared with the conventional semiconductor device A.

  Further, the gold bumps 5 can be arranged without overlapping the passivation film 3, and the opening 3 a of the passivation film 3 does not exist between the gold bumps 5 and the semiconductor substrate 1. No cracks in the film 3 occur.

Further, since the barrier metal 4 having good adhesion to the semiconductor substrate 1 and the pad electrode 2 is formed so as to cover the pad electrode 2, even if the pad electrode 2 is exposed from the passivation film 3, the pad electrode 2. However, there is no deterioration in strength and chemical compared with the conventional structure.
(Embodiment 2)
In the second embodiment, the area of the pad electrode 2 viewed from the semiconductor substrate 1 side is set to be 1/9 or less of the area of the gold bump 5.

According to this, as shown in FIG. 2B, in COG mounting, the highest gold bump 5 is usually crushed by about 2 μm, but this crushed amount is a glass of the gold bump 5 up to a crushed amount of about 4-5 μm. It increases in proportion to the pressure per unit area of the surface S facing the electrode 7 of the substrate 6. This is because if the area of the convex portion 5b of the gold bump 5 is made smaller than the area of the entire surface facing the electrode 7, the pressure per unit area of the convex portion 5b increases and the convex portion 5b can be easily formed. It shows that it can be crushed. According to our rule of thumb, by making the area of the pad electrode 2 viewed from the semiconductor substrate 1 side to be 1/9 or less of the area of the surface S of the gold bump 5, the area of the convex portion 5b appearing on the gold bump 5 is also small. Thus, since the convex portion 5b is easily crushed during COG mounting, it is almost negligible. In addition, in the case of 1/9 or more, the amount of crushing from the bottom surface of the convex portion 5b tends to be slightly smaller than in the case without the convex portion 5b, which is not good. That is, when 3 μm conductive particles 9 are used for COG mounting, the conductive particles 9 are crushed to about 2 μm, which is about 30%, and more reliable electrical conduction can be secured.
(Embodiment 3)
In the third embodiment, the thickness of the pad electrode 2 is set to 0.4 μm or less.

According to this, when the diameter of the conductive particle 9 is changed from the conventional 4 μm to the fine 3 μm, the conductive particle 9 satisfies the condition that the gold bump 5 and the electrode 7 can be electrically connected. That is, the step h1 of the convex portion 5b appearing on the surface S of the gold bump 5 is 0.4 μm or less. Here, the minimum crushing amount by which the conductive particles 9 having a particle diameter of 3 μm can electrically connect the gold bumps 5 and the electrodes 7 is set to 20% or more as usual, and as shown in FIG. If the difference h2 (the flatness range of the gold bump 5) between the highest gold bump 5 and the lowest gold bump 5 is 4 μm and the highest gold bump 5 collapse amount h3 is 2 μm, the lowest The gap h4 from the bottom surface of the convex portion 5b of the gold bump 5 to the electrode 7 is 2.4 μm (= 4-2 + 0.4), which is 2.4 μm (= 3 μm × the diameter after the minimum collapse of the conductive particles 9 80%). That is, the thickness is such that the bonding is sufficiently performed, and by making the thickness of the pad electrode 2 0.4 μm or less, the shape of the surface S facing the electrode 7 of the gold bump 5 becomes appropriate.
(Embodiment 4)
4 to 6 are sectional views of a mounting structure in which the semiconductor device A according to the fourth embodiment is mounted on a glass substrate 6 (an example of an insulating substrate).

  In the passivation film 3, an opening 3 a that opens at least a part of the pad electrode 2 is formed. The area of the surface of the gold bump 5 facing the semiconductor substrate 1 is larger than the area of the opening 3 a and the area of the opening 3 a is larger than the area of the pad electrode 2. The gold bump 5 is disposed via the barrier metal 4 so as to completely close the opening 3 a and cover the pad electrode 2. The barrier metal 4 covers a portion of the pad electrode 2 exposed from the opening 3 a of the passivation film 3.

Hereinafter, the operation of the above configuration will be described.
It is possible to form the pad electrode 2 without overlapping the passivation film 3 and the pad electrode 2 and inside the region of the opening 3 a of the passivation film 3. Accordingly, the surface S (surface opposite to the semiconductor substrate 1) of the gold bump 5 facing the electrode 7 of the glass substrate 6 is provided with a recess 5 a reflecting the shape of the opening 3 a of the passivation film 3, and the opening A convex portion 5b reflecting the shape of the pad electrode 2 located inside 3a appears. As described above, generally, the pad electrode 2 has a thickness of about 0.8 μm, and the passivation film 3 has a thickness of about 1 μm to 1.8 μm. Accordingly, the step difference of the concave portion 5a is compensated (filled) by the step portion of the convex portion 5b on the inside thereof, so that the height difference B between the concave portion 5a and the convex portion 5b with respect to the surface S of the gold bump 5 is 0. It becomes about 2 μm to 1 μm (= 1-0.8 to 1.8-0.8), and can be made much shallower than the depth of the conventional concave portion 5 a shown in FIG. Thereby, the influence of the recessed part 5a which generate | occur | produces in the gold bump 5 can be made small.
(Embodiment 5)
In the fifth embodiment, the distance from the peripheral edge of the opening 3a of the passivation film 3 to the pad electrode 2 exposed in the opening 3a is 2 μm or less, that is, the opening 3a of the passivation film 3 and the pad electrode 2 The width of the groove 15 formed between is set to be 2 μm or less.

According to this, in general, when the gold bump 5 is formed by electrolytic plating, the shape of the base appears on the surface S after the gold bump 5 is formed, but the width of the recess or groove of the base is less than a certain width. The shape is gradually filled when the gold bump 5 grows and does not appear on the surface S after the gold bump 5 is formed. Under the formation condition of the gold bump 5 that we are using, this threshold is about 2 μm. If it is more than this, the shape of the underlying groove is reflected on the surface S of the gold bump 5 and formed. Therefore, as described above, by setting the distance from the peripheral edge of the opening 3a to the pad electrode 2 to 2 μm or less, the depth of the recess 5a appearing on the surface S facing the electrode 7 of the gold bump 5 is set as shown in FIG. The depth of the concave portion 5a of the conventional gold bump 5 shown in a) can be made shallower, or the concave portion 5a can be almost eliminated.
(Embodiment 6)
In the sixth embodiment, the pad electrode 2 is thinner than the passivation film 3 and the difference between the thickness of the pad electrode 2 and the thickness of the passivation film 3 is set to 0.4 μm or less.

  According to this, the height difference B (step) between the concave portion 5a and the convex portion 5b with respect to the surface S of the gold bump 5 can be set to 0.4 μm or less. Therefore, when the diameter of the conductive particle 9 is changed from the conventional 4 μm to the fine 3 μm, the conductive particle 9 satisfies the condition that the gold bump 5 and the electrode 7 can be electrically connected. That is, the minimum crushing amount by which the conductive particles 9 having a particle diameter of 3 μm can electrically connect the gold bump 5 and the electrode 7 is 20% or more as usual, and the top of the highest gold bump 5 before COG mounting. And the apex of the lowest gold bump 5 (the flatness range of the gold bump 5) is 4 μm, and the collapse amount of the highest gold bump 5 is 2 μm. The gap up to 7 is 2.4 μm (= 4-2 + 0.4), which is equal to 2.4 μm (= 3 μm × 80%), which is the minimum diameter after the conductive particles 9 are crushed. Thereby, the condition that the conductive particles 9 can electrically connect the gold bump 5 and the electrode 7 is satisfied, and by making the difference between the thickness of the pad electrode 2 and the thickness of the passivation film 3 0.4 μm or less, The shape of the surface S facing the electrode 7 of the gold bump 5 is appropriate.

  In each of the above-described embodiments, the gold bump 5 is used as an example of the bump electrode. However, the gold bump 5 is not limited to the gold bump 5, and a plating bump such as a solder bump or a copper bump may be used.

Moreover, in each said embodiment, although the electrically-conductive particle 9 is made into spherical shape, it does not specifically limit to spherical shape.
In each of the above embodiments, an aluminum pad is used as the pad electrode 2, but a copper pad or the like may be used. The structure in the semiconductor substrate 1 is not particularly limited. For example, an interlayer conductive structure such as a tungsten via or an aluminum contact may be formed under the pad electrode 2 together with an interlayer film (not shown). I do not care.

  In each of the above-described embodiments, the semiconductor device A bonded to the glass substrate 6 via the ACF 12 by COG mounting has been described. However, the semiconductor device A is not limited to COG mounting, and an insulating conductive material is interposed on the insulating substrate. It may be related to all the semiconductor devices A to be joined.

  The present invention can also be applied to the semiconductor device A mounted by a mounting format other than the COG mounting format using ACF and its mounting structure.

It is sectional drawing of the mounting structure which mounted the semiconductor device in the 1st Embodiment of this invention in the glass substrate. FIG. 2 is an enlarged cross-sectional view of the mounting structure, in which (a) shows an enlarged cross section of the X portion in the circle in FIG. 1, (b) shows an enlarged cross section of the Y portion in the circle in FIG. It is a ZZ arrow line view in a). It is sectional drawing which shows each dimension of a mounting structure equally. It is sectional drawing of the mounting structure which mounted the semiconductor device in the 2nd Embodiment of this invention in the glass substrate. FIG. 5 is an enlarged cross-sectional view of the mounting structure, in which (a) shows an enlarged cross section of the X portion in the circle in FIG. 4, (b) shows an enlarged cross section of the Y portion in the circle in FIG. It is a ZZ arrow line view in a). It is an expanded sectional view of the gold bump of the mounting structure. It is sectional drawing of the mounting structure which mounted the conventional semiconductor device in the glass substrate. FIG. 8 is an enlarged cross-sectional view of the mounting structure, in which FIG. 7A shows an enlarged cross section of the X portion in the circle in FIG. 7 and FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Pad electrode 3 Passivation film 3a Opening 4 Barrier metal 5 Gold bump (bump electrode)
6 Glass substrate (insulating substrate)
7 Electrode 12 ACF (Anisotropic Conductive Material)
A Semiconductor device

Claims (6)

A semiconductor substrate on which a plurality of pad electrodes are formed;
A passivation film provided on the semiconductor substrate;
A semiconductor device having a bump electrode formed on the pad electrode through a barrier metal,
An opening for opening at least a part of the pad electrode is formed in the passivation film,
The area of the opening of the passivation film on the semiconductor substrate side is larger than the area of the bump electrode, and the area of the bump electrode is formed larger than the area of the pad electrode,
A semiconductor device, wherein the barrier metal covers a portion of the pad electrode exposed from the opening of the passivation film. 2. The semiconductor device according to claim 1, wherein the area of the pad electrode on the semiconductor substrate side is 1/9 or less of the area of the bump electrode. 3. The semiconductor device according to claim 1, wherein the pad electrode has a thickness of 0.4 [mu] m or less. A semiconductor substrate on which a plurality of pad electrodes are formed;
A passivation film provided on the semiconductor substrate;
A semiconductor device having a bump electrode formed on the pad electrode through a barrier metal,
An opening for opening at least a part of the pad electrode is formed in the passivation film,
The area of the bump electrode on the semiconductor substrate side is larger than the area of the opening of the passivation film, and the area of the opening of the passivation film is formed larger than the area of the pad electrode,
A portion of the pad electrode exposed from the opening of the passivation film is covered with a barrier metal ,
2. A semiconductor device according to claim 1, wherein a distance from the periphery of the opening of the passivation film to the pad electrode is 2 [mu] m or less . A semiconductor substrate on which a plurality of pad electrodes are formed;
A passivation film provided on the semiconductor substrate;
A semiconductor device having a bump electrode formed on the pad electrode through a barrier metal,
An opening for opening at least a part of the pad electrode is formed in the passivation film,
The area of the bump electrode on the semiconductor substrate side is larger than the area of the opening of the passivation film, and the area of the opening of the passivation film is formed larger than the area of the pad electrode,
A portion of the pad electrode exposed from the opening of the passivation film is covered with a barrier metal,
The pad electrode is thinner than the passivation film, and the difference between the thickness of the pad electrode and the thickness of the passivation film is 0.4 μm or less . A mounting structure in which a semiconductor device is mounted on an insulating substrate,
The semiconductor device has a semiconductor substrate on which a plurality of pad electrodes are formed, a passivation film provided on the semiconductor substrate, and a bump electrode formed on the pad electrode via a barrier metal,
An opening for opening at least a part of the pad electrode is formed in the passivation film,
The area of the opening of the passivation film on the semiconductor substrate side is larger than the area of the bump electrode, and the area of the bump electrode is formed larger than the area of the pad electrode,
The barrier metal covers a portion of the pad electrode exposed from the opening of the passivation film,
The insulating substrate has an electrode disposed at a position facing the bump electrode;
A semiconductor device mounting structure, wherein an anisotropic conductive material is interposed between and electrically connected to at least a bump electrode of the semiconductor device and an electrode of an insulating substrate.

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