JP3904366B2 - Image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a moving image capturing image sensor having a low power consumption mode.
[0002]
[Prior art]
Image sensors used in portable devices are required to reduce power consumption.
[0003]
There are the following methods for reducing the power consumption of a semiconductor chip.
[0004]
(1) The operation clock is stopped during an operation unnecessary period.
[0005]
(2) The clock frequency is reduced to 1/2, 1/4, 1/8 or the like by a frequency divider.
[0006]
However, the image sensor chip includes an analog circuit and a digital circuit, and the ratio of the analog circuit to the power consumption of the digital circuit is large. Therefore, in such a method, the power consumption of the image sensor when a moving image is captured. Cannot be greatly reduced.
[0007]
When the power supply of the analog circuit is controlled to be turned on / off, the influence of the off effect appears one frame later, and thus the power supply cannot simply be turned off.
[0008]
[Problems to be solved by the invention]
On the other hand, in the case where the change of the sample body is gradual or in the trial shooting, it is not always necessary to capture all frames, so it is desired to reduce the frame rate and reduce the power consumption accordingly.
[0009]
An object of the present invention is to provide an image sensor capable of such focused to a point, to lower power consumption drop the frame rate by performing fine on / off control of the power.
[0010]
[Means for solving the problems and their effects]
In the image sensor of the first aspect of the present invention,
A pixel array in which pixels including light receiving elements are two-dimensionally arranged;
A readout circuit that scans the pixel array and reads out an optical integration signal from the pixel;
While the pixel array performs optical integration, a control circuit for stopping power supply to the readout circuit ;
It has.
[0011]
According to this image sensor, power supply to the readout circuit is stopped during the light integration period, so that the power consumption of the image sensor can be reduced. In other words, since the conventional integration of light integration and readout is controlled on / off in a time-sharing manner as described above, low power consumption with a reduced frame rate is effectively achieved. .
[0012]
In the image sensor according to the second aspect of the present invention , in the first aspect, the control circuit does not supply power to the pixel array and the readout circuit for a predetermined period.
[0013]
According to this image sensor, since power supply to the pixel array and the readout circuit is stopped for a predetermined period, it is possible to further reduce the power consumption of the image sensor.
[0014]
Other objects, configurations and effects of the present invention will become apparent from the following description.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
[First Embodiment]
FIG. 1 is a schematic block diagram of a two-dimensional image sensor according to the first embodiment of the present invention. The two-dimensional image sensor is, for example, a MOS type.
[0017]
The pixel array 10 includes pixels arranged in rows and columns (for example, a photodiode, a potential reset transistor switch connected to one end of the photodiode, a buffer amplifier connected in series between the one end of the photodiode and a vertical bus line, and Read transistor switch). The vertical scanning circuit 11 scans the pixel array 10 line (row) sequentially. As a result, a signal optically integrated with the light receiving elements in the selected row is read onto the vertical bus 12 (vertical reading). A signal on the vertical bus 12 is held in the sample and hold circuit 14 in response to a control signal from the sample and hold control circuit 13. The light receiving elements in the selected row are reset, and light integration in this row is started.
[0018]
The sample hold circuit 14 is, for example, a correlated double sampling circuit (CDS). In this case, details of reading and holding of the optical integration signal are as follows. The sample-and-hold circuit is reset, and the voltage of (optical integration signal Vx) + (component ΔV depending on variation in characteristics of the transistors coupled to the photodiode) is sampled in the sample-and-hold circuit 14 by the first sampling, and then selected. The light receiving elements in the row are reset, and then the optical integration signal voltage Vx, which is the difference between Vx + ΔV and ΔV, is held in the sample hold circuit 14 by the second sampling.
[0019]
The horizontal scanning circuit 15 scans the sample and hold circuit 14 dot-sequentially. As a result, the output signal of the selected sample and hold circuit is read onto the horizontal bus 16 (horizontal reading). The signal on the horizontal bus 16 is amplified by the amplification circuit 17 and then converted into a digital value by the A / D conversion circuit 18.
[0020]
The timing control circuit 19 generates a control signal for operating the vertical scanning circuit 11, the sample hold control circuit 13, and the horizontal scanning circuit 15 based on the clock CLK. The reference voltage generation circuit 20 supplies a reset voltage to the pixel array 10 and supplies a reference voltage to the sample hold circuit 14 and the amplifier circuit 17. This reference voltage generation circuit 20 is a part of the power supply circuit 21.
[0021]
A mode signal MODE is supplied to the power supply circuit 21. When the mode signal MODE indicates the normal mode, the power supply circuit 21 constantly supplies a power supply voltage to each circuit. When the mode signal MODE indicates the low power consumption mode, the power supply circuit 21 supplies the power supply voltage to the block BL1 while the enable signal EN1 from the power supply control circuit 22 is active, and the enable signal EN1 is inactive. The supply is stopped for a period, the power supply voltage is supplied to the block BL2 while the enable signal EN2 from the power supply control circuit 22 is active, and the supply is stopped while the enable signal EN2 is inactive.
[0022]
The block BL1 includes a pixel array 10 and a vertical scanning circuit 11. The block BL2 includes a sample hold control circuit 13, a sample hold circuit 14, a horizontal scanning circuit 15, an amplifier circuit 17, and an A / D conversion circuit 18.
[0023]
The power supply circuit 21 always supplies a power supply voltage to the timing control circuit 19 and the power supply control circuit 22 even in the low power consumption mode.
[0024]
Since the reference voltage generation circuit 20 is a part of the power supply circuit 21, when the power supply circuit 21 supplies a power supply voltage to the block BL1, the reference voltage generation circuit 20 supplies a reset voltage to the pixel array 10, and the power supply circuit 21 When the power supply voltage is supplied to the block BL2, the reference voltage generation circuit 20 supplies the reset voltage to the sample hold circuit 14 and supplies the reference voltage to the amplifier circuit 17.
[0025]
In the power supply control circuit 22, the vertical synchronization signal VSYNC is supplied from the timing control circuit 19 to the clock input terminal of the ternary counter 23, the lower bit Q0 of the output of the counter 23 is the enable signal EN2, and the upper bit of the output of the counter 23 An enable signal EN1 is obtained by inverting Q1 by the inverter 24. The counter 23 cyclically outputs counts 0, 1, and 2. When the count is 0 and 1, the enable signal EN1 is at a high level, and when the count is 1, the enable signal EN2 is at a high level.
[0026]
FIG. 2 is a time chart showing the operation of the power supply control circuit 22 in FIG.
[0027]
Next, the operation of the image sensor configured as described above will be described in the case of the low power consumption mode.
[0028]
Assume that the count of the counter 23 is 2 in the initial state. In this state, the power supply voltage is not supplied to the blocks BL1 and BL2.
[0029]
(Light integration period)
In response to the rise of the vertical synchronization signal VSYNC, the counter 23 counts to 0, the enable signal EN1 changes to high level, and the power supply voltage is supplied to the block BL1.
[0030]
The vertical scanning circuit 11 performs vertical scanning in response to a control signal from the timing control circuit 19. As a result, the above-described vertical reading and resetting are performed line-sequentially. Since no power supply voltage is supplied to the block BL2, no power consumption occurs.
[0031]
(Reading period)
In response to the rise of the vertical synchronization signal VSYNC, the counter 23 counts to 1, EN2 changes to high level, and the power supply voltage is also supplied to the block BL2.
[0032]
In the block BL1, vertical reading and reset are performed in line sequence, and in the block BL2, the horizontal reading is performed every time a signal for one row is held in the sample hold circuit.
[0033]
That is, the operation in this read period is the same as that in the normal mode.
[0034]
(Power-off period)
In response to the rising edge of the vertical synchronization signal VSYNC, the counter 23 counts to 2, both the enable signals EN1 and EN2 transition to a low level, and the supply of the power supply voltage to the blocks BL1 and BL2 is stopped.
[0035]
Hereinafter, such optical integration, readout, and power-off periods are cyclically repeated.
[0036]
For example, the current consumption is as follows.
[0037]
Pixel array 10: about 1 mA
Total current consumption of the vertical scanning circuit 11, sample hold control circuit 13, horizontal scanning circuit 15, timing control circuit 19 and power supply control circuit 22: about 3 mA
Sample hold circuit 14: about 2.5 mA
Amplification circuit 17: about 8 mA
A / D conversion circuit 18: about 12 mA
Reference voltage generation circuit 20: about 0.5 mA
The total current consumption of the sample hold circuit 14, the amplifier circuit 17 and the A / D conversion circuit 18 included in the block BL2 is relatively large at about 22.5 mA.
[0038]
According to the first embodiment, the power supply voltage supply to the block BL2 is stopped in the light integration period, and further, the power supply voltage supply to the blocks BL1 and BL2 is stopped in the power off period. The power consumption of the image sensor can be reduced to about 1/3 of that in the normal operation mode.
[0039]
[Second Embodiment]
FIG. 3 is a schematic block diagram of a two-dimensional image sensor according to the second embodiment of the present invention.
[0040]
The power supply circuit 21A always supplies a power supply voltage to the pixel array 10 even in the low power consumption mode.
[0041]
In the low power consumption mode, the power supply circuit 21A supplies the power supply voltage to the vertical scanning circuit 11 while the enable signal EN1A is active, and stops supplying the enable signal EN1A while the enable signal EN1A is inactive.
[0042]
In the power supply control circuit 22A, the signal obtained by inverting the output bit Q0 of the counter 23 by the inverter 24 is the enable signal EN1, and the output bit Q1 of the counter 23 is the enable signal EN2.
[0043]
The other points are the same as in FIG.
[0044]
FIG. 4 is a time chart showing the operation of the power supply control circuit 22A in FIG.
[0045]
Next, the operation of the image sensor configured as described above will be described in the case of the low power consumption mode.
[0046]
Assume that the count of the counter 23 is 2 in the initial state. In this state, the power supply voltage is supplied to the vertical scanning circuit 11 and the block BL2.
[0047]
(First light integration period)
In response to the rise of the vertical synchronization signal VSYNC, the count of the counter 23 becomes 0, the enable signal EN2 transitions to a low level, and the supply of the power supply voltage to the block BL2 is stopped.
[0048]
The vertical scanning circuit 11 performs vertical scanning in response to a control signal from the timing control circuit 19. As a result, the above-described vertical reading and resetting are performed line-sequentially.
[0049]
(Second light integration period)
In response to the rise of the vertical synchronization signal VSYNC, the count of the counter 23 becomes 1, the enable signal EN1A transitions to a low level, and the supply of power supply voltage to the vertical scanning circuit 11 is stopped.
[0050]
Thereby, only the light integration is performed in the pixel array 10.
[0051]
(Reading period)
In response to the rise of the vertical synchronization signal VSYNC, the counter 23 counts to 2, the enable signals EN1 and EN2 transition to a high level, and the power supply voltage is supplied to the blocks BL1 and BL2.
[0052]
Thereby, the same operation as the reading in the first embodiment is performed.
[0053]
Hereinafter, such a period of the first light integration, the second light integration, and the power off is cyclically repeated.
[0054]
According to the second embodiment, the supply of the power supply voltage to the block BL2 is off in the first and second light integration periods, and the power supply is close to power off. The power can be reduced to 50% or less of that in the normal operation mode. Further, the optical integration time is twice that of the first embodiment, and the sensitivity of the image sensor is improved.
[0055]
The ternary counter 23 of the power supply control circuit 22A is changed to a quaternary counter or more and the logical configuration is changed, so that the second optical integration period is set to a plurality of frame periods and the optical integration time is increased from that of the first embodiment. May be.
[0056]
[Third Embodiment]
FIG. 5 is a schematic block diagram of a two-dimensional image sensor according to the third embodiment of the present invention.
[0057]
The power supply circuit 21B always supplies a power supply voltage to the pixel array 10 and the vertical scanning circuit 11 even in the low power consumption mode. Therefore, the enable signal EN1 is not supplied to the power supply circuit 21B.
[0058]
In the power supply control circuit 22B, the output bits Q0 and Q1 of the counter 23 are supplied to the OR gate 25, and the output of the OR gate 25 is the enable signal EN2.
[0059]
The other points are the same as in FIG.
[0060]
FIG. 6 is a time chart showing the operation of the power supply control circuit 22B in FIG.
[0061]
Next, the operation of the image sensor configured as described above will be described in the case of the low power consumption mode.
[0062]
Assume that the count of the counter 23 is 2 in the initial state. In this state, the power supply voltage is supplied to the block BL2.
[0063]
(Light integration period)
In response to the rise of the vertical synchronization signal VSYNC, the count of the counter 23 becomes 0, the enable signal EN2 transitions to a low level, and the supply of the power supply voltage to the block BL2 is stopped.
[0064]
The vertical scanning circuit 11 performs vertical scanning in response to a control signal from the timing control circuit 19. As a result, the above-described vertical reading and resetting are performed line-sequentially.
[0065]
(First readout period)
In response to the rise of the vertical synchronization signal VSYNC, the counter 23 counts to 1, the enable signal EN2 transitions to a high level, and the supply of power supply voltage to the block BL2 is stopped.
[0066]
Thereby, the same operation as the reading in the first embodiment is performed.
[0067]
(Second readout period)
In response to the rise of the vertical synchronization signal VSYNC, the counter 23 counts to 2, and the enable signal EN2 maintains a high level.
[0068]
Thereby, the same operation as the above-described reading is performed.
[0069]
Hereinafter, such a period of optical integration, first readout, and second readout is cyclically repeated.
[0070]
According to the third embodiment, since the power supply voltage supply to the block BL2 is off during the light integration period, the state is close to power off, and the power consumption of the image sensor is reduced to about 2/3 in the normal operation mode. It is possible. Furthermore, since 2 frame periods are read out among 3 frame periods, the frame rate can be doubled as compared to the first embodiment.
[0071]
[Fourth Embodiment]
FIG. 7 is a schematic block diagram of a two-dimensional image sensor according to the fourth embodiment of the present invention.
[0072]
This image sensor is similar to that of FIG. 1, and differs from the first embodiment in that the enable signal EN2 in FIG. 1 is divided into enable signals EN21 to EN23.
[0073]
In the low power consumption mode, the power supply circuit 21C supplies the power supply voltage to the sample hold control circuit 13, the sample hold circuit 14, and the horizontal scanning circuit 15 while the enable signal EN21 is active, and the enable signal EN21 is inactive. During this period, the supply is stopped, while the enable signal EN22 is active, the power supply voltage is supplied to the amplifier circuit 17, and when the enable signal EN22 is inactive, the supply is stopped and the enable signal EN23 is active. During the period, the power supply voltage is supplied to the A / D conversion circuit 18, and the supply is stopped while the enable signal EN23 is inactive.
[0074]
In the power supply control circuit 22C, the logic circuit 26, based on the output bit Q0 of the counter 23 and the timing correction signal from the timing control circuit 19, as shown in FIG. EN23 is generated.
[0075]
The other points are the same as in FIG.
[0076]
Since the operation of the above configuration is apparent from the description of the first embodiment and FIG. 8, the description thereof is omitted.
[0077]
According to the fourth embodiment, since a sudden change in current is reduced due to the deviation, the fluctuation of the power supply voltage is less than that in the first embodiment.
[0078]
Note that the present invention includes various other modifications.
[0079]
For example, in the first embodiment, if there is no problem even if the frame rate is further reduced, the power-off period may be set to two vertical scanning periods or more.
[0080]
The image sensor may not have the A / D conversion circuit 18. The image sensor is not limited to the MOS type, and may be a CCD type or the like.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a two-dimensional image sensor according to a first embodiment of the present invention.
FIG. 2 is a time chart showing the operation of the power supply control circuit in FIG. 1;
FIG. 3 is a schematic block diagram of a two-dimensional image sensor according to a second embodiment of the present invention.
4 is a time chart showing the operation of the power supply control circuit in FIG. 3;
FIG. 5 is a schematic block diagram of a two-dimensional image sensor according to a third embodiment of the present invention.
6 is a time chart showing the operation of the power supply control circuit in FIG. 5. FIG.
FIG. 7 is a schematic block diagram of a two-dimensional image sensor according to a fourth embodiment of the present invention.
8 is a time chart showing the operation of the power supply control circuit in FIG. 6;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Pixel array 11 Vertical scanning circuit 12 Vertical bus 13 Sample hold control circuit 14 Sample hold circuit 15 Horizontal scanning circuit 16 Horizontal bus 17 Amplifying circuit 18 A / D conversion circuit 19 Timing control circuit 20 Reference voltage generation circuit 21, 21A-21C Power supply Circuit 22, 22A-22C Power supply control circuit 23 Counter 24 Inverter 25 OR gate 26 Logic circuit BL1, BL2 block

Claims (2)

A pixel array in which pixels including light receiving elements are two-dimensionally arranged;
A vertical scanning circuit for vertically scanning the pixel array;
A sample-and-hold circuit that samples and holds an optical integration signal of a pixel row selected by the vertical scanning;
A horizontal scanning circuit for horizontally scanning the sample and hold circuit;
An amplifying circuit for amplifying a signal read from the sample and hold circuit by the horizontal scanning;
While the pixel array performs light integration, the sample and hold circuit and a control circuit for stopping power supply to the horizontal scanning circuit are provided,
A first timing for starting power supply to the horizontal scanning circuit and the sample hold circuit is different from a second timing for supplying power to the amplifier circuit;
An image sensor characterized by that. An A / D conversion circuit for A / D converting the amplified signal;
The control circuit makes the third timing for supplying power to the A / D conversion circuit different from the first timing and the second timing.
The image sensor according to claim 1 .

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