JP3904656B2 - Clock controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock control device used in a system using a CPU, and more particularly to a clock control device that contributes to lower power consumption of a portable terminal using a battery or a rechargeable battery.
[0002]
[Prior art]
In order to reduce the power consumption of a portable terminal using a conventional battery or a rechargeable battery, for example, as disclosed in JP-A-4-160415, when an external interrupt signal such as a key input is input, the CPU The clock generation circuit for supplying the clock to the CPU is operated only when the CPU operates.
[0003]
[Problems to be solved by the invention]
However, in the above conventional technique, the time from when the external interrupt signal is generated to the time when the clock is stably supplied to the CPU and the CPU starts to operate is expected in consideration of the response characteristics and operation margin of the components used in the circuit. Therefore, it is set longer than the actual value of the actual circuit, and usually takes several hundred ms or more, and it is not possible to frequently generate a state in which the generation of the clock supplied to the CPU is substantially stopped. There was a problem.
[0004]
An object of the present invention is to provide a clock control device capable of realizing lower power consumption by frequently stopping a clock supplied to a CPU.
[0005]
[Means for Solving the Problems]
The clock control device according to claim 1 controls the start and stop of the generation of the CPU clock having a predetermined frequency from the CPU clock generation means, and detects the external interrupt when the generation of the CPU clock is stopped. A clock control device for starting generation of a CPU clock, wherein clock generating means for generating a reference clock having a frequency lower than that of the CPU clock , and the frequency of the CPU clock is stably operated based on the reference clock. CPU clock control means for immediately supplying the CPU clock to the CPU when it is determined that the CPU clock is present.
[0006]
According to a second aspect of the present invention, in the clock control device according to the first aspect, the CPU clock control means divides the CPU clock and determines the level of the divided signal as the reference clock. The rising edge timing and the falling edge timing of the CPU are checked, and if the high level and the low level, respectively, it is determined that the frequency of the CPU clock is stable, and the CPU clock is immediately supplied to the CPU. To do.
[0007]
According to a third aspect of the present invention, there is provided the clock control device according to the first or second aspect, wherein the CPU clock control means has a period Td of the reference clock and a period of the divided signal is T. , T <Td <2T, so that the CPU clock is frequency-divided.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows the configuration of the clock control apparatus of the present invention. This apparatus comprises a CPU clock generation circuit 1, a CPU clock control circuit 2, a clock clock generation circuit 3, and a CPU 4.
[0009]
The CPU clock generation circuit 1 stops the generation of the clock signal c when the clock stop signal b is input from the CPU 4 in a state where the external interrupt signal a such as key input is not input. When the external interrupt signal a is input in this stopped state, it detects that it is an external interrupt and starts outputting the clock signal c.
[0010]
The CPU clock control circuit 2 checks the clock signal c from the CPU clock generation circuit 1 on the basis of the clock signal d output from the clock clock generation circuit 3 and immediately determines that it is operating stably. The signal c is supplied to the CPU 4 as the clock signal e. A control signal f is inputted to the CPU clock control circuit 2 in synchronization with the clock stop signal b so that the clock signal c can be checked.
[0011]
The clock signal d from the clock clock generation circuit 3 is set to a frequency sufficiently lower than the clock signal c from the CPU clock generation circuit 1. Normally, the clock signal d for a clock is also supplied to the CPU 4, but is not directly related to the present invention.
[0012]
FIG. 2 shows a detailed configuration of the CPU clock generation circuit 1 of FIG. The CPU clock generation circuit 1 includes a selector circuit 101 and an oscillation circuit 102 including an oscillator, a capacitor, a resistor, and a NOR gate. In this circuit operation, when an external interrupt occurs, that is, when the external interrupt signal a becomes high level, the output of the selector circuit 101 becomes low level, and the oscillation circuit 102 enters an oscillation state. On the other hand, when the external interrupt signal a is at a low level and the output of the selector circuit 101 is at a low level, when a signal for stopping the generation of the CPU clock is input, that is, when the clock stop signal b is at a high level, the selector circuit The output of 101 becomes high level, and the oscillation of the oscillation circuit 102 is stopped.
[0013]
FIG. 3 shows a detailed configuration of the CPU clock control circuit 2 of FIG. The CPU clock control circuit 2 includes a counter 201, a D flip-flop 202, an AND gate 203, a D flip flop 204, a D flip flop 205, an inverter 206, and a two-input AND / OR gate 207.
[0014]
The clock signal c from the CPU clock generation circuit 1 is divided by 512 by the counter 201, and the divided signal is input to the inputs D of the D flip-flop 202 and the D flip-flop 204. The clock signal d from the clock generation circuit 3 is inverted by the CK of the D flip-flop 202 and the CK of the D flip-flops 205 and 206 after being inverted by the inverter 206. Here, assuming that the period Td of the clock signal d for a clock is T and the period of the signal divided by the counter 201 is T, the relationship of T <Td <2T may be satisfied.
[0015]
The D flip-flop 202 takes in the signal divided by the counter 201 at the rising edge of the clock signal d for clock and outputs it from the output Q. The output signal is input to the input D of the D flip-flop 205.
[0016]
The D flip-flop 204 takes in the signal divided by the counter 201 at the fall of the clock signal d for clock and outputs it from the output Q bar, and the output signal is inputted to the 2-input AND / OR gate 207.
[0017]
The D flip-flop 205 matches the output phases of the D flip-flop 202 and the D flip-flop 204, takes the output Q of the D flip-flop 202, and outputs it to the 2-input AND / OR gate 207.
[0018]
The CPU clock control circuit 2 operates only when the control signal f from the CPU 4 is at a low level. That is, when the control signal f input to the 2-input AND / OR gate 207 is at a low level, the output Q bar of the D flip-flop 204 and the output Q of the D flip-flop 205 are enabled. On the other hand, when the input control signal f is at a high level, the clock signal c from the CPU clock generation circuit 1 is output as the clock signal e.
[0019]
Next, the operation of the clock control device of the present invention will be described with reference to FIGS. First, at time t1 in FIG. 4, the clock stop signal b is set to the high level and the control signal f is set to the low level to stop the generation of the clock signal c from the CPU clock generation circuit 1, and the clock signal e Stop supplying.
[0020]
When an external interrupt occurs at time t2 in FIG. 4, that is, when the external interrupt signal a becomes high level, generation of the clock signal c from the CPU clock generation circuit 1 is started.
[0021]
At time t3 in FIG. 4, it is assumed that the D flip-flop 202 checks the level of the output signal of the counter 201 at the rising timing of the clock signal d for clock, and operates stably if the level is high. In this case, since the level is high, the high level side of the output signal of the counter 201 operates stably.
[0022]
At time t4 in FIG. 4, it is assumed that the D flip-flop 204 checks the level of the output signal of the counter 201 at the falling timing of the clock signal d for clock, and operates stably if the level is low. In this case, since the level is high, the low level side of the output signal of the counter 201 is not stably operated.
[0023]
At time t5 in FIG. 4, the D flip-flop 202 checks the level of the output signal of the counter 201 at the rising timing of the clock signal d for the clock. In this case, the level is high. Yes.
[0024]
At time t6 in FIG. 4, the D flip-flop 204 checks the level of the output signal of the counter 201 at the falling timing of the clock signal d for clock, and in this case, it is low level. The low level side operates stably. As a result, the output of the 2-input AND / OR gate 207 becomes high level, and it is determined that both the high level and low level of the output signal of the counter 201 are stably output, and the clock signal e is output. .
[0025]
At time t7 in FIG. 4, the CPU stop program sets the clock stop signal b to low level and the control signal f to high level.
[0026]
In the above embodiment, when the output waveform of the clock signal d is 32 KHz, the frequency of the output waveform of the counter 201 is 32 MHz, and the clock signal d for the clock is used as a reference, the frequency of the output waveform of the clock signal c is about 16 Stable operation can be checked in the range of 4 MHz to 32.7 MHz.
[0027]
As described above, since it is supplied to the CPU as soon as it is determined that the clock signal to the CPU is operating stably, the CPU starts operating with a quick response from the state where the supply of the clock signal to the CPU is stopped. As a result, it is possible to frequently generate a state in which the clock supplied to the CPU is stopped.
[0028]
【The invention's effect】
According to the present invention, it is possible to frequently generate a state in which the clock supplied to the CPU is stopped, to realize low power consumption, and in particular, to contribute to low power consumption of the portable terminal.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a clock control device of the present invention.
FIG. 2 is a diagram illustrating an example of a CPU clock generation circuit in FIG. 1;
FIG. 3 is a diagram illustrating an example of a CPU clock control circuit in FIG. 1;
FIG. 4 is a time chart for explaining the operation of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 CPU clock generation circuit 2 CPU clock control circuit 3 Clock generation circuit 4 for clocks CPU

Claims (3)

A clock control device that controls the start and stop of generation of a CPU clock having a predetermined frequency from the CPU clock generation means, and starts generation of the CPU clock when an external interrupt is detected in a state where generation of the CPU clock is stopped Because
Clock generating means for generating a reference clock having a lower frequency than the CPU clock;
And a CPU clock control means for immediately supplying the CPU clock to the CPU when it is determined that the frequency of the CPU clock is operating stably based on the reference clock. The CPU clock control means includes
The CPU clock is divided, and the level of the divided signal is checked at the rising timing and falling timing of the reference clock. If the level is high and low, the frequency of the CPU clock is stabilized. and it is judged that the clock control apparatus according to claim 1, characterized in that immediately supplies the clock for the CPU to CPU.   The CPU clock control means includes
  3. The CPU clock according to claim 1, wherein the CPU clock is divided so as to satisfy a relationship of T <Td <2T, where T is the reference clock period Td and T is the frequency of the divided signal. The clock control device described.

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