JP3907181B2 - System on chip and method for transferring data to a display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a system on chip and a method for transferring data from a memory to a liquid crystal display (LCD) in which a plurality of modules are connected by a local bus.
[0002]
[Prior art]
In recent years, the system-on-chip 40 shown in FIG. The system-on-chip 40 is a chip on which a plurality of modules are mounted with an MPU Core (Micro Processor Unit Core) 12 as a center. The modules include a power management 27, a clock controller 28, a DRAM (Dynamic Random Access Memory) controller 42, a DMA (Direct Memory Access) controller (not shown), an LCD controller 44, various peripheral controllers 26, and the like. Each module is connected to the MPU Core 12 and each module through a local bus 24.
[0003]
A system area 19 and a video area 20 are provided in a DRAM 18 which is a main memory. Thus, in the system on chip 40, the main memory and the video memory do not use their own memories, but share a single memory. This is a UMA (Unified Memory Architecture) adopted by some personal computers, and a simple system configuration including peripheral devices can be adopted.
[0004]
Data transfer from the DRAM 18 to the LCD 22 is performed via the DRAM controller 42, the local bus 24, and the LCD controller 44 as shown in FIG. When the LCD 22 is an LCD with a small number of colors such as an STN (Super Twisted Nematic) LCD, the LCD controller 44 performs dither processing and FRC (Frame Rate Control) processing.
[0005]
The dither process is a kind of filter process using a physical space, and the FRC process is a filter process using time change. In the dither process, when there is no change in the image, that is, in the case of a still image, it is not necessary to perform the process after the process is performed once. The FRC process needs to be performed for each frame.
[0006]
In order to perform the above processing, the LCD controller 44 includes a dither circuit 46 and an FRC circuit 48 as shown in FIGS. For example, when data to the LCD 22 is sent from the DRAM 18 to the LCD controller 44 at 16 bpp (bit par pixel), the data is reduced to (1) 9 bpp by the dither circuit 46 and (2) 3 bpp by the FRC circuit 48. Thus, after reducing the data, the data is sent to the LCD 22 and an image is displayed. When displayed, the actual number of colors is reduced because the data is reduced. However, since the dithering process and the FRC process are performed, the human eye feels that more colors are developed than the actual number of colors.
[0007]
However, if the main memory and the video memory are shared by the DRAM 18 and various modules are connected by the same bus 24, the bus 24 may be occupied by a specific module. In that case, data transfer to the LCD 22 is interrupted, and the screen of the LCD 22 is disturbed. Further, when the bus 24 is occupied by data, data to each module is interrupted.
[0008]
[Problems to be solved by the invention]
An object of the present invention is to provide a system-on- chip and a method for transferring data to an LCD so that the display on the LCD is not disturbed.
[0009]
[Means for Solving the Problems]
Memory controller, including a dither circuit for Genchijimi the amount of data to be input in the memory.
[0010]
The gist of the system on chip for transferring data to the liquid crystal display according to the present invention is that data from an external memory having a system area and a video area to the liquid crystal display is connected to the MPU and a plurality of modules on a local bus. a system-on-chip for performing the transfer, which is connected to an external memory, a memory controller including a Disa circuitry for Genchijimi amount of data into and out force to the memory, the local bus And a display controller connected to the liquid crystal display, receiving data reduced by the dither circuit via the local bus, and including an FRC circuit for further reducing the amount of data .
[0011]
Further, the gist of the data transfer method to the liquid crystal display is that the MPU and a plurality of modules are connected to the local bus, and the system is turned on to transfer data from the external memory having the system area and the video area to the liquid crystal display. · in the chip, the data memory controller into and out of force in memory of the external, a data transfer method for transferring via the local bus and a display controller to display, the memory controller (a), A step of reducing the amount of data to be input / output in the memory by dither processing ; and ( b) the display controller receives and receives the reduced amount of data in the memory controller via the local bus. The amount of data is FR Further reducing by the C process.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
A system on chip and method including a memory controller for transferring data to a display of the invention will be described with reference to the drawings. In this description, the memory controller is a DRAM controller.
[0013]
As shown in FIG. 1, the chip 10 of the present invention is a system-on-chip in which a plurality of modules are mounted around an MPU Core 12. The modules include a power management 27, a clock controller 28, a DRAM controller 14, a DMA controller (not shown), an LCD controller 16, and various peripheral controllers 26. Each module is connected to the MPU Core 12 and each module through a local bus 24.
[0014]
The main memory uses, for example, a DRAM 18 and is controlled by the DRAM controller 14. A system area 19 and a video area 20 are provided in the DRAM 18, and a part of the DRAM 18 is used as a video memory.
[0015]
An LCD is used as a display for displaying data. As the LCD 22, for example, an STN LCD is used. Although the actual number of colors is small, the number of colors can be increased in a pseudo manner by dither processing and FRC processing described later.
[0016]
The DRAM controller 14 includes a dither circuit 15 that reduces the amount of data to be input / output in the DRAM 18.
[0017]
The dither process performed by the dither circuit 15 is a process for reducing the amount of data using a filter. The filter is determined by the position of the data on the LCD 22 and the value of the lower bits. For example, a case will be described in which 8-bit data in FIG. 2A is reduced at a position in the region 30 in FIG. It is preferable to display the data B (7: 0) from B7 to B0 as they are, but when the number of colors on the LCD 22 is small, a dither process is performed. When the lower bits are 2 bits, first to fourth filters 32a, 32b, 32c, and 32d are provided as shown in FIG. When the lower 2 bits (B1, B2) of the data are (0, 0), the lower 2 bits are first deleted. Further, as shown in FIG. 2A, the first filter 32a is used to reflect the lower bits in the upper bits from B7 to B2. If there is data at the position (m, n), 1 is subtracted from the data B (7: 2) from B7 to B2. For example, if B (7: 2) is “100000”, “011111” is obtained.
[0018]
When the lower 2 bits (B1, B2) are (0, 0) and the data position is (m, n + 1), the lower 2 bits are deleted and nothing is performed on the data from B7 to B2.
[0019]
To delete the lower 3 bits, prepare 9 filters and do the same as above.
[0020]
The timing for performing the dither processing is when data is stored in the DRAM 18 or when data is read out. When the stored data is used for other processes, the data must be reversible, and a dither process is performed when reading the data. Further, when the data is only displayed on the LCD 22, the reversibility of the data is unnecessary, and the dither process is performed when the data is stored.
[0021]
There are two timings for performing the dither processing as described above, but the MPU Core 12 serves as a means for controlling the timing. Two timings are selected by the MPU Core 12 sending a signal to the dither circuit 15 and controlling the dither circuit 15. As described above, when the MPU Core 12 selects the timing, the data corresponding to the data can be stored, and the operation of the chip 10 becomes faster.
[0022]
The LCD controller 16 includes an FRC circuit 17 that further reduces the data reduced by the dither circuit 15.
[0023]
The FRC process performed by the FRC circuit 17 is a process for reducing the amount of data using a time change. For example, FIG. 3 shows a process for developing four colors in three frames using white and black. Black and white colors are black or white in all three frames. In the case of developing an intermediate color (66%, 33% gray), as shown in the drawing, it is possible to artificially generate an intermediate color by generating black or white for each frame. This is because the response speed of the liquid crystal used in the STN LCD is slow, so even if the voltage applied to the liquid crystal is changed for each frame, the pretilt angle of the liquid crystal becomes an average of all frames. As the number of frames increases, the number of colors can be increased in a pseudo manner.
[0024]
When the video data is input from the outside, the chip 10 described above is stored in the DRAM 18 via the DRAM controller 14. The data is 16 bpp (bit par pixel) data as shown in FIG. In the case of 16 bpp, red (R) and blue (B) are generally 5 bits, and green (G) is 6 bits.
[0025]
When the MPU Core 12 controls the dither circuit 15, the timing for performing the dither processing is selected as follows.
[0026]
When data reversibility is required, the data is stored in the DRAM 18 as it is. When reading the stored data, the dither circuit 15 performs dither processing. The data subjected to the dither processing is 9 bits per bit of 3 bits for each color. Therefore, the occupancy rate of the local bus is reduced to 9/16 compared to the conventional case, and data transfer can be performed smoothly.
[0027]
If data reversibility is not required, a dither process is performed when data is stored in the DRAM 18. Similarly to the above, the data amount is set to 9 bpp. The occupancy rate of the local bus 24 decreases. Data transfer time between the DRAM controller 15 and the DRAM 18 is shortened. Furthermore, the storage area in the DRAM 18 can be reduced.
[0028]
From the above, as shown in FIG. 5, the amount of data on the local bus 24 is reduced to 9 bpp. This is a reduction of 7 bpp compared to the conventional case shown in FIG.
[0029]
When the LCD controller 16 receives the data reduced to 9 bpp, the data amount is further reduced by the FRC process. The data amount is 3 bpp in total for 1 bit of each color.
[0030]
The LCD 22 receives the data reduced to 3 bpp and performs the same color development as the original data in a pseudo manner. In the case of the above-described example, since the basic data is 16 bpp, 65536 colors can be displayed. The amount of data is reduced to 3 bpp by the dither processing and the FRC processing, and the actual color development is 8 colors, but pseudo 65536 colors are displayed.
[0031]
As described above, the present invention can reduce the amount of data on the local bus 24. Specifically, in the case of displaying 16 bpp data on an LCD of 640 × 480 pixels and a refresh rate of 72 Hz, conventionally, the data transfer on the local bus 24 is 16 × 640 × 480 × 72 = 44236800 bytes. A data transfer rate of / sec was required. In the present invention, since it is 9 bpp, the data transfer rate is 24883200 bytes / sec. The difference between the prior art and the present invention is 19.4 Mbyte / sec. This difference reduces the possibility that data cannot be sent to the LCD controller 16.
[0032]
As mentioned above, although this invention was demonstrated, this invention is not limited to said embodiment. In addition, the present invention can be carried out in a mode in which various improvements, modifications, and changes are added based on the knowledge of those skilled in the art without departing from the spirit of the present invention.
[0033]
【The invention's effect】
According to the present invention, since the amount of data transferred to the LCD controller is reduced by the dither circuit provided in the DRAM controller, it is easy to avoid data collision on the local bus. Accordingly, since data can be reliably transferred to the LCD controller, image disturbance on the LCD does not occur.
[0034]
By dithering the data before storing it in the memory, the data storage capacity can be reduced. Therefore, the open area of the memory can be used for other data, and the memory can be effectively used. In addition, the data transfer speed between the memory controller and the memory is increased.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a chip of the present invention.
FIGS. 2A and 2B are diagrams illustrating dither processing, where FIG. 2A is an example of data, FIG. 2B is a diagram illustrating a region, and FIG. 2C is a diagram of a filter;
FIG. 3 is a diagram illustrating a pseudo color generation process by an FRC process.
FIG. 4 is a diagram illustrating how data is reduced by dither processing and FRC processing;
FIG. 5 is a diagram illustrating a flow of data by a chip.
FIG. 6 is a diagram showing a configuration of a conventional chip.
FIG. 7 is a diagram showing a data flow in a conventional chip.
[Explanation of symbols]
10, 40: Chip 12: MPU Core (MPU)
14, 42: DRAM controller (memory controller)
15, 46: Dither circuit 16, 44: LCD controller (display controller)
17, 48: FRC circuit 18: DRAM (memory)
19: System area 20: Video area 22: LCD
24: Local bus 26: Various peripherals 27: Power management 28: Clock controller 30: Areas 32a, 32b, 32c, 32d: Filter

Claims (6)

A system-on-chip, in which an MPU and a plurality of modules are connected to a local bus, and data is transferred from an external memory having a system area and a video area to a liquid crystal display,
A memory controller including a Disa circuitry for connected to said external memory, to Genchijimi amount of data into and out force to the memory,
A display controller connected to the local bus and the liquid crystal display, including a FRC circuit for receiving data reduced by the dither circuit via the local bus and further reducing the amount of data of the received data ; ,
Including system on chip. The MPU controls the timing of the dither circuit is Genchijimi the data amount of the data, the system-on-chip according to claim 1. 3. The system on chip according to claim 2, wherein the timing is when data is stored in or read from the memory. 4. The system-on- chip according to claim 1, wherein the data amount reduced by the dither circuit is 9 bits / pixel, and the data amount reduced by the FRC circuit is 3 bits / pixel. It is connected to the local bus to the MPU and a plurality of modules in a system-on-chip for transferring from the external memory data to the liquid crystal display having a system area and a video area, and out force in memory of the external A data transfer method for transferring data to a display via a memory controller, a local bus and a display controller,
(A) the memory controller reducing the amount of data to be input / output in the memory by dithering ;
( B) The display controller receives data with the data amount reduced by the memory controller via the local bus, and further reduces the data amount of the received data by FRC processing;
Data transfer method including : The stearyl-up (a) involves Genchijimi the amount of data when the read data from the memory or when the memory of the data to memory, the data transfer method of claim 5.

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