JP3907448B2 - Shot layout creation method - Google Patents

Description

【００３０】
次に、ウエハステージの移動時間の算出方法について説明する。
図８は、ステージの駆動方法を示しており、図中Ｖはステージ速度、ｔはステージ移動時間、Ｖmax はステージ最大速度、αはステージ加速度、Ｓ1 は加速区間、Ｓ2 は定速区間、Ｓ3 は減速区間、Ｓ4 は静定（位置決め）区間、ｔ1 は加速駆動時間、ｔ2 は定速駆動時間、ｔ3 は減速駆動時間、ｔ4 はステージの静定（位置決め）時間を表している。
【００３１】
一般に、ウエハステージの駆動は、縦軸を速度Ｖ、横軸を時間ｔとした場合、図８に示すように加速区間Ｓ1 の部分の加速駆動と、定速区間Ｓ2 の部分の一定速駆動と、減速区間Ｓ3 の部分の減速駆動からなる台形駆動制御と、静定区間Ｓ4 の部分の静定駆動により行われており、加速駆動時間ｔ1 からステージ静定時間ｔ4 までのトータルの時間がステージの移動時間となる。尚、駆動制御に使用されるステージ加速度αとステージ最高速度Ｖmax は、ステージの移動距離により最適の値が露光装置内で設定され、ステージ静定時間ｔ4 は、固定の時間が設定される。ここで、実際のステージの移動は、前記加速区間Ｓ1 から減速区間Ｓ3 までの区間で行われており、静定区間Ｓ4 では位置サーボにより、目標位置への最終位置決めを行っている。よって、ステージ移動距離Ｓは、図中斜線で示されている台形の面積を示すことになり、ステージ加速度α、ステージ最高速Ｖmax 、加速駆動時間ｔ1 、定速駆動時間ｔ2 、及び減速駆動時間ｔ3 より、以下の式（４）で求めることが出来る。
Ｓ＝(1/2) ×α×ｔ1²＋Ｖmax ×ｔ2 ＋(1/2) ×α×ｔ3² …（４）
【００３２】
ここで、図８から分かるように、加速駆動時間ｔ1 はステージ最高速Ｖmax に至るまでの時間であり、減速駆動時間ｔ3 はステージ最高速Vmaxから速度０になるまでの時間であるため、
ｔ1 ＝ｔ3 ＝Ｖmax ／αとなる。
よって、上記式（４）は、
Ｓ＝Ｖmax²／α＋Ｖmax ×ｔ2 となり、
定速駆動時間ｔ2 は、
ｔ2 ＝Ｓ／Ｖmax −Ｖmax ／α となる。
【００３３】
以上より、ステージ移動時間Ｔstepは、以下の式（５）により求めることが出来る。
Ｔstep＝ｔ1 ＋ｔ2 ＋ｔ3 ＋ｔ4
＝Ｖmax ／α＋（Ｓ／Ｖmax −Ｖmax ／α）＋Ｖmax ／α＋ｔ4
＝Ｖmax ／α＋Ｓ／Ｖmax ＋ｔ4 …（５）
ここで、ステージ移動距離Ｓは、実際にはショットサイズを示すことになる。
【００３４】
次に、ステッパ、及びスキャナでの１ショット当たりの露光時間の算出方法について説明する。
ステッパの場合、ショットの露光はステージが停止した状態で行われるため、１ショットの露光時間Ｔexpoは、ウエハ面での露光光の照度I とレジスト感度（露光量）Ｅにより、以下の式（６）で求めることが出来る。
Ｔexpo＝Ｅ÷Ｉ …（６）
【００３５】
スキャナの場合は、ショット内Ｙ方向に一定速度で走査（スキャン）しながら露光を行うため、露光ショットのＹ方向の距離（長さ）と走査速度（スキャンスピード）により、露光時間を求めることが出来る。
【００３６】
ここで、スキャン露光では、実際の露光は走査方向に直交する長方形の露光スリットにより行うため、スキャンスピードＶscan、露光スリットの幅ｄ、ウエハ面での露光光の照度Ｉ、露光量Ｅとすると、露光量Ｅは以下の式で表すことが出来る。
Ｅ＝Ｉ×（ｄ÷Ｖscan）
よって、上記式から、スキャンスピードＶscanは、
Ｖscan＝Ｉ÷Ｅ×ｄ
となる。
【００３７】
以上より、スキャナの場合の露光時間Ｔexpoは、スキャン距離をＳscanとすると、以下の式（７）で求められる。
Ｔexpo＝Ｓscan÷Ｖscan
＝Ｓscan÷（Ｉ÷Ｅ×ｄ）
＝（Ｓscan×Ｅ）÷（Ｉ×ｄ）… （７）
ここで、ＸＹステージの加速度α、最高速Ｖmax 、ウエハ面の露光光照度Ｉ、及び露光スリット幅ｄは、ショットサイズや露光条件、または露光装置により、露光装置内で所定の値が決定される。
【００３８】
以下、例を基に各ショットレイアウトの単位時間当たりのチップ生産性を求める。
図９は、ウエハサイズ＝２００．０ｍｍ、ショットサイズＸ＝１８．０ｍｍ、Ｙ＝２０．０ｍｍ チップサイズＸ方向lx＝６．０ｍｍ、Ｙ方向ly＝１０．０ｍｍ、露光有効領域＝半径９７．０ｍｍ、３×２の６チップ構成からなる露光ショットの場合の本ショットレイアウト作成方法で作成されたショットレイアウトを示す図である。
【００３９】
作成された４つのショットレイアウトのショット数、チップ数とレイアウトの横列（Row)数は、
(a) の場合
ショット数＝８５、チップ数＝４４１、Row 数＝１０
(b) の場合
ショット数＝８７、チップ数＝４４８、Row 数＝１０
(c) の場合
ショット数＝８３、チップ数＝４４２、Row 数＝９
(d) の場合
ショット数＝８５、チップ数＝４４４、Row 数＝９
となり、従来であれば、(b) のショットレイアウトが最適ショットレイアウトとして決定されていた。
【００４０】
次に、図９の４つのショットレイアウトについて、前記スループット算出式を用い、ステッパでのスループットを求める。今回、設定露光量を５００．０Ｊ／ｍ² とし、装置の設定値を各々、ステージ加速度＝５０００ｍｍ／sec²、ステージ最高速＝２５０ｍｍ／sec 、ステージ静定時間＝０．０５sec 、ウエハ面露光光照度＝５０００Ｗ／ｍ² 、ウエハ供給時間＝５．０sec 、ウエハ回収時間＝５．０sec 、アライメント時間＝１０．０sec とする。
【００４１】
先ず、Ｘステージ移動時間Ｔx は、移動距離１８．０ｍｍから、前記式（５）より、
Ｔx ＝２５０／５０００＋１８．０／２５０＋０．０５
＝０．１７２ sec
Ｙステージ移動時間Ｔy は、移動距離２０．０ｍｍから、同じく前記式（５）より、
Ｔy ＝２５０／５０００＋２０．０／２５０＋０．０５
＝０．１８０ sec
となる。
【００４２】
次に、露光時間Ｔexpoは、照度５０００Ｗ／ｍ² 、露光量５００．０Ｊ／ｍ² から、前記式（６）より、
Ｔexpo＝５００÷５０００＝０．１０ sec
となる。
【００４３】
次に、露光処理時間を算出する。上記計算より、ステージ移動時間は、Ｘステージ移動時間Ｔx ＜Ｙステージ移動時間Ｔy となるため、露光処理時間の算出式は、前記式（３−２）が適用され、各々のショットレイアウトでの露光処理時間は以下のようになる。
【００４４】
(a)の場合
０．１７２×７５＋０．１８×９＋０．１×８５
＝２３．０２ sec
(b)の場合
０．１７２×７７＋０．１８×９＋０．１×８７
＝２３．５６４ sec
(c)の場合
０．１７２×７４＋０．１８×８＋０．１×８３
＝２２．４６８ sec
(d)の場合
０．１７２×７６＋０．１８×８＋０．１×８５
＝２３．０１２ sec
【００４５】
以上より、図９の(a) から(d) までの各々のショットレイアウトのスループットは以下のように求まる。
【００４６】
(a)の場合
３６００÷（５．０＋１０．０＋２３．０２＋５．０）
＝８３．６８ｗｐｈ
(b)の場合
３６００÷（５．０＋１０．０＋２３．５６４＋５．０）
＝８２．６３ｗｐｈ
(c)の場合
３６００÷（５．０＋１０．０＋２２．４６８＋５．０）
＝８４．７６ｗｐｈ
(d)の場合
３６００÷（５．０＋１０．０＋２３．０１２＋５．０）
＝８３．６９ｗｐｈ
【００４７】
最後に、各ショットレイアウトでの１時間当たりのチップ生産量を求める。１時間当たりのチップ生産量は、（スループット）×（各ショットレイアウトでの総チップ数）で求められ、上記条件の場合の各ショットレイアウトでのチップ生産性は、
(a) の場合
８３．６８×４４１＝３６９０２チップ
(b) の場合
８２．６３×４４８＝３７０１８チップ
(c) の場合
８４．７６×４４２＝３７４６３チップ
(d) の場合
８３．６９×４４４＝３７１５８チップ
となり、(c) のショットレイアウトが、１時間当たりの生産量が最も多い、つまり生産性の高いショットレイアウトとなることが分かる。これにより、半導体製造メーカは、短期間での生産性が要求される半導体製品の場合は、(c) のショットレイアウトを使用すれば良いことになる。
【００４８】
尚、上記では、本発明の動作を順に述べてきたが、予め、生産性優先、ウエハ内のチップ数優先などの条件を設定しておき、その条件を満たす最適なショットレイアウトを自動作成するようにしても良い。
【００４９】
なお、本発明は、上記ショットレイアウト作成方法を用いるためのプログラムを記録した磁気ディスクやＭＯ等の記録媒体、並びに上記ショットレイアウト作成方法を用いる半導体露光装置などにも適用可能である。
【００５０】
（半導体生産システムの実施形態）
次に、本発明に係る装置を用いた半導体デバイス（ＩＣやＬＳＩ等の半導体チップ、液晶パネル、ＣＣＤ、薄膜磁気ヘッド、マイクロマシン等）の生産システムの例を説明する。これは半導体製造工場に設置された製造装置のトラブル対応や定期メンテナンス、あるいはソフトウェア提供などの保守サービスを、製造工場外のコンピュータネットワークを利用して行うものである。
【００５１】
図１０は全体システムをある角度から切り出して表現したものである。図中、１０１は半導体デバイスの製造装置を提供するベンダ（装置供給メーカ）の事業所である。製造装置の実例としては、半導体製造工場で使用する各種プロセス用の半導体製造装置、例えば、前工程用機器（露光装置、レジスト処理装置、エッチング装置等のリソグラフィ装置、熱処理装置、成膜装置、平坦化装置等）や後工程用機器（組立て装置、検査装置等）を想定している。事業所１０１内には、製造装置の保守データベースを提供するホスト管理システム１０８、複数の操作端末コンピュータ１１０、これらを結んでイントラネット等を構築するローカルエリアネットワーク（ＬＡＮ）１０９を備える。ホスト管理システム１０８は、ＬＡＮ１０９を事業所の外部ネットワークであるインターネット１０５に接続するためのゲートウェイと、外部からのアクセスを制限するセキュリティ機能を備える。
【００５２】
一方、１０２〜１０４は、製造装置のユーザとしての半導体製造メーカの製造工場である。製造工場１０２〜１０４は、互いに異なるメーカに属する工場であっても良いし、同一のメーカに属する工場（例えば、前工程用の工場、後工程用の工場等）であっても良い。各工場１０２〜１０４内には、夫々、複数の製造装置１０６と、それらを結んでイントラネット等を構築するローカルエリアネットワーク（ＬＡＮ）１１１と、各製造装置１０６の稼動状況を監視する監視装置としてホスト管理システム１０７とが設けられている。各工場１０２〜１０４に設けられたホスト管理システム１０７は、各工場内のＬＡＮ１１１を工場の外部ネットワークであるインターネット１０５に接続するためのゲートウェイを備える。これにより各工場のＬＡＮ１１１からインターネット１０５を介してベンダの事業所１０１側のホスト管理システム１０８にアクセスが可能となり、ホスト管理システム１０８のセキュリティ機能によって限られたユーザだけにアクセスが許可となっている。具体的には、インターネット１０５を介して、各製造装置１０６の稼動状況を示すステータス情報（例えば、トラブルが発生した製造装置の症状）を工場側からベンダ側に通知する他、その通知に対応する応答情報（例えば、トラブルに対する対処方法を指示する情報、対処用のソフトウェアやデータ）や、最新のソフトウェア、ヘルプ情報などの保守情報をベンダ側から受け取ることができる。各工場１０２〜１０４とベンダの事業所１０１との間のデータ通信および各工場内のＬＡＮ１１１でのデータ通信には、インターネットで一般的に使用されている通信プロトコル（ＴＣＰ／ＩＰ）が使用される。なお、工場外の外部ネットワークとしてインターネットを利用する代わりに、第三者からのアクセスができずにセキュリティの高い専用線ネットワーク（ＩＳＤＮなど）を利用することもできる。また、ホスト管理システムはベンダが提供するものに限らずユーザがデータベースを構築して外部ネットワーク上に置き、ユーザの複数の工場から該データベースへのアクセスを許可するようにしてもよい。
【００５３】
さて、図１１は本実施形態の全体システムを図１０とは別の角度から切り出して表現した概念図である。先の例ではそれぞれが製造装置を備えた複数のユーザ工場と、該製造装置のベンダの管理システムとを外部ネットワークで接続して、該外部ネットワークを介して各工場の生産管理や少なくとも１台の製造装置の情報をデータ通信するものであった。これに対し本例は、複数のベンダの製造装置を備えた工場と、該複数の製造装置のそれぞれのベンダの管理システムとを工場外の外部ネットワークで接続して、各製造装置の保守情報をデータ通信するものである。図中、２０１は製造装置ユーザ（半導体デバイス製造メーカ）の製造工場であり、工場の製造ラインには各種プロセスを行う製造装置、ここでは例として露光装置２０２、レジスト処理装置２０３、成膜処理装置２０４が導入されている。なお図１１では製造工場２０１は１つだけ描いているが、実際は複数の工場が同様にネットワーク化されている。工場内の各装置はＬＡＮ２０６で接続されてイントラネットを構成し、ホスト管理システム２０５で製造ラインの稼動管理がされている。
【００５４】
一方、露光装置メーカ２１０、レジスト処理装置メーカ２２０、成膜装置メーカ２３０などベンダ（装置供給メーカ）の各事業所には、それぞれ供給した機器の遠隔保守を行うためのホスト管理システム２１１，２２１，２３１を備え、これらは上述したように保守データベースと外部ネットワークのゲートウェイを備える。ユーザの製造工場内の各装置を管理するホスト管理システム２０５と、各装置のベンダの管理システム２１１，２２１，２３１とは、外部ネットワーク２００であるインターネットもしくは専用線ネットワークによって接続されている。このシステムにおいて、製造ラインの一連の製造機器の中のどれかにトラブルが起きると、製造ラインの稼動が休止してしまうが、トラブルが起きた機器のベンダからインターネット２００を介した遠隔保守を受けることで迅速な対応が可能であり、製造ラインの休止を最小限に抑えることができる。
【００５５】
半導体製造工場に設置された各製造装置はそれぞれ、ディスプレイと、ネットワークインタフェースと、記憶装置にストアされたネットワークアクセス用ソフトウェアならびに装置動作用のソフトウェアを実行するコンピュータを備える。記憶装置としては内蔵メモリやハードディスク、あるいはネットワークファイルサーバーなどである。上記ネットワークアクセス用ソフトウェアは、専用又は汎用のウェブブラウザを含み、例えば図１２に一例を示す様な画面のユーザインタフェースをディスプレイ上に提供する。各工場で製造装置を管理するオペレータは、画面を参照しながら、製造装置の機種４０１、シリアルナンバー４０２、トラブルの件名４０３、発生日４０４、緊急度４０５、症状４０６、対処法４０７、経過４０８等の情報を画面上の入力項目に入力する。入力された情報はインターネットを介して保守データベースに送信され、その結果の適切な保守情報が保守データベースから返信されディスプレイ上に提示される。またウェブブラウザが提供するユーザインタフェースはさらに図示のごとくハイパーリンク機能４１０〜４１２を実現し、オペレータは各項目の更に詳細な情報にアクセスしたり、ベンダが提供するソフトウェアライブラリから製造装置に使用する最新バージョンのソフトウェアを引出したり、工場のオペレータの参考に供する操作ガイド（ヘルプ情報）を引出したりすることができる。ここで、保守データベースが提供する保守情報には、上記説明した本発明に関する情報も含まれ、また前記ソフトウェアライブラリは本発明を実現するための最新のソフトウェアも提供する。
【００５６】
次に上記説明した生産システムを利用した半導体デバイスの製造プロセスを説明する。図１３は半導体デバイスの全体的な製造プロセスのフローを示す。ステップ１（回路設計）では半導体デバイスの回路設計を行う。ステップ２（マスク製作）では設計した回路パターンを形成したマスクを製作する。一方、ステップ３（ウエハ製造）ではシリコン等の材料を用いてウエハを製造する。ステップ４（ウエハプロセス）は前工程と呼ばれ、上記用意したマスクとウエハを用いて、リソグラフィ技術によってウエハ上に実際の回路を形成する。次のステップ５（組み立て）は後工程と呼ばれ、ステップ４によって作製されたウエハを用いて半導体チップ化する工程であり、アッセンブリ工程（ダイシング、ボンディング）、パッケージング工程（チップ封入）等の組立て工程を含む。ステップ６（検査）ではステップ５で作製された半導体デバイスの動作確認テスト、耐久性テスト等の検査を行う。こうした工程を経て半導体デバイスが完成し、これを出荷（ステップ７）する。前工程と後工程はそれぞれ専用の別の工場で行い、これらの工場毎に上記説明した遠隔保守システムによって保守がなされる。また前工程工場と後工程工場との間でも、インターネットまたは専用線ネットワークを介して生産管理や装置保守のための情報がデータ通信される。
【００５７】
図１４は上記ウエハプロセスの詳細なフローを示す。ステップ１１（酸化）ではウエハの表面を酸化させる。ステップ１２（ＣＶＤ）ではウエハ表面に絶縁膜を成膜する。ステップ１３（電極形成）ではウエハ上に電極を蒸着によって形成する。ステップ１４（イオン打込み）ではウエハにイオンを打ち込む。ステップ１５（レジスト処理）ではウエハに感光剤を塗布する。ステップ１６（露光）では上記説明した露光装置によってマスクの回路パターンをウエハに焼付露光する。ステップ１７（現像）では露光したウエハを現像する。ステップ１８（エッチング）では現像したレジスト像以外の部分を削り取る。ステップ１９（レジスト剥離）ではエッチングが済んで不要となったレジストを取り除く。これらのステップを繰り返し行うことによって、ウエハ上に多重に回路パターンを形成する。各工程で使用する製造機器は上記説明した遠隔保守システムによって保守がなされているので、トラブルを未然に防ぐと共に、もしトラブルが発生しても迅速な復旧が可能であり、従来に比べて半導体デバイスの生産性を向上させることができる。
【００５８】
【発明の効果】
以上述べたように、本発明によれば、作成されたショットレイアウトに対し、スループットを求め、更に単位時間当たりのチップ生産性を求めることが可能になる。これにより、半導体製造メーカの製造要求に合った、最適なショットレイアウトを求めることが出来る。
【図面の簡単な説明】
【図１】 本発明が適用される半導体製造用投影露光装置の一例を示す構成図である。
【図２】 本発明の実施形態に係るショットレイアウト作成方法において、チップレイアウト作成時のチップ配置を示す図である。
【図３】 本発明の実施形態に係るショットレイアウト作成方法で作成した、チップレイアウトの例を示す図である。
【図４】 本発明の実施形態に係るショットレイアウト作成方法において、ショットレイアウトの作成方法を示す図である。
【図５】 本発明の実施形態に係るショットレイアウト作成方法で作成した、ショットレイアウトの例を示す図である。
【図６】 本発明の実施形態に係るスループット算出方法において、１枚のウエハの露光処理工程を示すフローチャートである。
【図７】 本発明の実施形態に係るスループット算出方法において、ショットの露光順序を示す図である。
【図８】 本発明の実施形態に係るスループット算出方法において、ウエハステージの移動時間を示す図である。
【図９】 本発明の実施形態に係る単位時間当たりのチップ生産性を求めるための例となるショットレイアウトの図である。
【図１０】 本発明に係る装置を用いた半導体デバイスの生産システムをある角度から見た概念図である。
【図１１】 本発明に係る装置を用いた半導体デバイスの生産システムを別の角度から見た概念図である。
【図１２】 ユーザインタフェースの具体例である。
【図１３】 デバイスの製造プロセスのフローを説明する図である。
【図１４】 ウエハプロセスを説明する図である。
【符号の説明】
５０：照明光学系、５１：レチクル（原版）、５２：レチクルステージ、５３：縮小投影レンズ、５４：オートフォーカス検出器、５５：ウエハ（基板）、５６：ウエハチャック、５７：ウエハステージ、５８：ミラー、５９：レーザ干渉計式測長器、６０：コンソールユニット、６１：アライメント検出器。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a shot layout creation method for determining an arrangement of exposure shots on a substrate such as a wafer in a semiconductor exposure apparatus.
[0002]
[Prior art]
Usually, when a circuit pattern on the surface of an original plate such as a reticle is projected and exposed onto a wafer, which is a substrate, using a semiconductor exposure apparatus (stepper or scanner), the shot arrangement can take the maximum number of chips from the wafer. It has been decided.
[0003]
[Problems to be solved by the invention]
In recent years, semiconductor device-equipped devices have shifted from personal computers (PCs) to the Internet, such as mobile phones, and digital consumer devices. As for semiconductor products, the market window has been shortened, the life has been shortened, and the number of products has been reduced. Is progressing. Further, even in mass-produced products such as memories such as DRAMs and microprocessors, the period of high prices after product introduction has become much shorter than before. For this reason, in the future, at the start of mass production of products for the Internet, digital consumer products, and mass-produced products such as memory and microprocessors, production in a shorter period of time, that is, product production per unit time An increase is required. Along with this, semiconductor manufacturers are now trying to improve productivity by manufacturing on a small-scale line called a mini-fab and changing wafer processing methods such as single wafer processing. Under such circumstances, in a semiconductor exposure apparatus such as a stepper and a scanner, productivity depends on a shot arrangement on a wafer, and the shot arrangement is determined from a chip arrangement on the wafer. Therefore, when viewed from the viewpoint of the amount of product (device chip) produced per unit time, a shot layout in which the maximum number of chips can be taken from a wafer is not always high in chip productivity, that is, an optimal shot layout. May not be able to meet the requirements of the semiconductor manufacturer as a user.
[0004]
SUMMARY OF THE INVENTION An object of the present invention is to make it possible to create an optimal exposure shot layout that meets user production requirements.
[0005]
[Means for Solving the Problems]
  To achieve the above object, the present inventionLayout creation methodThe original pattern on the substrateCreate chip layout and shot layout for exposureIn the layout creation method,
  A layout creating step of creating a plurality of chip layouts and shot layouts corresponding to each of the plurality of chip layouts;
  A calculation step of calculating a production amount of chips per unit time in each shot layout based on the plurality of chip layouts and a shot layout corresponding to each of the plurality of chip layoutsAnd
  A step of obtaining a chip layout having the largest chip production amount per unit time and a corresponding shot layout based on the chip production amount per unit time in each of the shot layouts calculated in the calculation step.It is characterized by that.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment of shot layout creation method etc.)
Hereinafter, a shot layout creation method according to an embodiment of the present invention will be described with reference to the drawings. Before that, a step-and-repeat (or scan) type projection exposure apparatus to which the present invention is applied, a configuration of a so-called stepper is illustrated. 1 will be used for explanation. In this figure, reference numeral 50 denotes an illumination optical system, which projects and exposes a pattern (having a plurality of chip patterns) provided on a reticle 51 as an original onto a photosensitive resist layer on a wafer 55 as a substrate. Exposure light is generated. A reticle stage 52 holds the reticle 51. When the reticle 51 held on the reticle stage 52 is irradiated with exposure light from the illumination optical system 50, the pattern on the reticle 51 is reduced and projected onto the wafer 55 on the wafer chuck 56 via the reduction projection lens 53. Is done.
[0013]
54 is a known autofocus detector. The autofocus detector irradiates the surface of the wafer 55 with a light beam and photoelectrically detects the reflected light, whereby the position of the surface of the wafer 55 in the optical axis (Z-axis) direction with respect to the focal plane of the projection lens 53 is detected. Is detected. Based on this detection result, the wafer chuck 56 is moved in the optical axis direction of the projection lens 53 by a drive mechanism (not shown), and the surface of the wafer 55 is positioned on the focal plane of the projection lens 53. Reference numeral 57 denotes a wafer stage for moving the wafer 55 held on the wafer chuck 56 along a plane (XY plane) perpendicular to the optical axis of the projection lens 53, and sequentially exposes each area on the wafer 55. In this case, the step and repeat movement is performed.
[0014]
58 is a mirror that moves along the XY plane integrally with the wafer stage 57, 59 is a known laser interferometer type length measuring device that measures the position of the wafer stage 57 on the XY plane via the mirror 58, and 60 is this A console unit 61 for controlling the entire projection exposure apparatus 61 detects an alignment mark formed on the wafer 55 through the projection lens 53 and measures the position of the wafer 55 on the XY plane. It is a detector.
[0015]
Next, a method of creating a shot layout that is a candidate for the optimum shot layout in the present invention will be described. In this shot layout creation method, first, a chip layout in the wafer 55 is created. FIG. 2 shows an arrangement method of chips in the wafer, and the chip layout is obtained by arranging the chips in one of the four patterns (a) to (d) in the figure with respect to the center of the wafer. . Each chip arrangement method from FIG. 2 (a) to FIG. 2 (d) is as follows. In the figure, A represents the center of the wafer and B represents the center of the chip.
[0016]
(a) The center of the chip is the center of the wafer.
(b) The center of the left side of the chip is the center of the wafer.
(c) The center of the lower side of the chip is the center of the wafer.
(d) The lower left corner of the chip is the center of the wafer.
[0017]
Next, in order to determine whether or not the arranged chip exists within the effective exposure area of the wafer, chip coordinates to be used are obtained. Here, assuming that the length in the X direction of the chip is lx and the length in the Y direction is ly, when valid / invalid determination is performed in the first quadrant of the wafer, the coordinates in the upper right corner of the chip, in the second quadrant, The coordinates of the lower right corner of the chip, the coordinates of the lower left corner in the third quadrant, and the coordinates of the upper left corner in the fourth quadrant may be obtained. For example, the chip coordinates (X, Y) when the presence / absence determination is performed in the first quadrant can be obtained by the following expression.
[0018]
(a) Chip layout
(X, Y) = ((m−0.5) × lx), (n−0.5) × ly))
(b) Chip layout
(X, Y) = ((m × lx), (n−0.5) × ly))
(c) Chip layout
(X, Y) = ((m−0.5) × lx), (n × ly))
(d) Chip layout
(X, Y) = ((m × lx), (n × ly))
m represents the number of chips in the X direction (m = 1, 2, 3,...), and n represents the number of chips in the Y direction (n = 1, 2, 3,...).
[0019]
Here, in the effective exposure area of the wafer, if the distance from the center of the wafer is D and each determination chip coordinate is (X, Y), a chip having a chip coordinate satisfying the following expression (1) is the wafer. It is defined that the chip is in the effective exposure area. Therefore, in the four chip arrangement patterns, the chip layout in each wafer can be obtained by determining the effective chip according to the equation (1).
D² ≧ X² + Y² (1)
[0020]
FIG. 3 is a diagram showing a chip layout in the wafer obtained by the above chip arrangement. (A), (b), (c) and (d) in FIG. 3 correspond to (a), (b), (c) and (d) in FIG. 2, respectively.
[0021]
If the chip layout in the wafer 55 is obtained, then a shot layout for performing actual exposure is obtained. Usually, the exposure shot is composed of one to a plurality of chips, and the shot sizes X and Y are always an integral multiple of the chip size (x, y). FIG. 4 shows a shot layout creation method. In this figure, a represents an exposure shot having a 2 × 1 two-chip configuration. “c” represents a shot layout creation reference. In this embodiment, a frame of 1 shot 2 × 1 chip as indicated by a dotted line in FIG. 4 with reference to the intersection of the left end and the lower end of the chip layout of the wafer 55. Then, the chip layout is cut out, and the shot layout is created by making the effective shot when the chip is in the cut shot. In FIG. 4, the hatched portion indicated by the dotted line indicated by b is the created shot layout.
[0022]
FIG. 5 is a diagram showing a shot layout created based on the chip layout of FIG.
[0023]
Next, a method for obtaining the number of processed wafers (throughput) per unit time from the shot layout created by the shot layout creating method will be described. The throughput generally represents the number of wafers processed per hour, and the unit is represented by wph (Wafer per Hour). The throughput is obtained from the processing time per wafer.
[0024]
FIG. 6 is a flowchart of a general exposure processing sequence for one wafer in the alignment step. As shown in this figure, the processing of a single wafer is made up of four processes: a wafer supply process in step S1, an alignment process in step S2, an exposure process in step S3, and a wafer recovery process in step S4. Become. Therefore, when the unit of each processing time is second, the throughput can be obtained by the following formula (2) by obtaining the sum of these four processing times.
[0025]
Throughput (wph) = 3600 / (wafer supply time + alignment time + exposure processing time + wafer recovery time) (2)
Here, the wafer supply time and wafer recovery time are determined by the wafer size, and the alignment time is simply determined by the number of measurement shots used for alignment, so these should be treated as fixed values that are almost independent of the shot layout. I can do it. Therefore, in order to obtain the throughput, it is only necessary to obtain the exposure processing time depending on the shot layout.
[0026]
FIG. 7 is a diagram showing an exposure order in the shot exposure process. In the figure, (a) represents the stepper and (b) represents the exposure sequence of the scanner. The numbers described in the shot are numbers indicating the exposure order of the shots.
[0027]
First, the stepper exposure sequence will be described. As shown in FIG. 7 (a), the stepper steps in the −X direction from the first exposure start shot, steps in the −Y direction when the exposure for one column is completed, and steps in the X direction again to perform exposure. This process is repeated until the 28th shot when the exposure ends. In the shot layout of FIG. 7A, stage movement is performed in a total of 27 steps, that is, 23 steps in the X direction and 4 steps in the X and Y directions, that is, the number of shots minus 1 step. Next, the exposure order of the scanner will be described. The arrow in the layout of the shot layout in FIG. 7B represents the scan direction of the scan exposure, and as shown in the figure, the scan direction is always exposed so that the adjacent shots are alternately reversed. . The dotted line of the semicircle in the figure represents the stage movement (step) from the end of the scan exposure of the shot to the start of the scan exposure of the next shot, and the arrow indicates the direction of movement of the stage. As can be seen from the dotted line of the semicircle, the stage movement order and the number of movements are the same as those of the stepper.
[0028]
In addition, the movement pattern of the XY stage in the exposure process includes three movement patterns of only the X direction, only the Y direction, and the XY simultaneous direction. In the case of the XY simultaneous movement, the X direction movement time and the Y direction movement time. By comparing the time of the two, it is possible to distribute the movement to either X or Y. Therefore, the stage movement time in one wafer can be obtained by obtaining the movement time in the X direction and the Y direction and the number of movements in the shot layout. Here, the number of movements of each of X and Y can be simply determined as follows based on the movement time in the X and Y directions, the number of shots, and the number of rows in the horizontal direction of the shot layout.
When (X direction movement time) ≥ (Y direction movement time)
Number of movements in X direction = number of shots−1
Number of movements in the Y direction = 0
When (X direction movement time) <(Y direction movement time)
Number of movements in X direction = number of shots-number of rows
Number of movements in Y direction = Number of Rows -1
[0029]
From the above, the exposure processing time depends on the number of shots, the number of rows in the horizontal direction of the shot layout, the movement time of the wafer stages X and Y depending on the shot size, and the exposure time per shot. 1) and (3-2).

[0030]
Next, a method for calculating the movement time of the wafer stage will be described.
FIG. 8 shows a stage driving method, where V is the stage speed, t is the stage moving time, Vmax is the stage maximum speed, α is the stage acceleration, S1 is the acceleration section, S2 is the constant speed section, and S3 is the stage speed. The deceleration zone, S4 is the static (positioning) zone, t1 is the acceleration driving time, t2 is the constant speed driving time, t3 is the deceleration driving time, and t4 is the stage stationary (positioning) time.
[0031]
In general, the wafer stage is driven when the vertical axis is speed V and the horizontal axis is time t, as shown in FIG. 8, acceleration driving in the acceleration zone S1 portion and constant speed driving in the constant velocity zone S2 portion. The trapezoidal drive control consisting of the deceleration drive in the deceleration zone S3 and the static drive in the static zone S4 are performed, and the total time from the acceleration drive time t1 to the stage stabilization time t4 is Travel time. The stage acceleration α and the stage maximum speed Vmax used for drive control are set to optimum values in the exposure apparatus depending on the stage moving distance, and the stage settling time t4 is set to a fixed time. Here, the actual stage movement is performed in the section from the acceleration section S1 to the deceleration section S3. In the stationary section S4, the final positioning to the target position is performed by the position servo. Accordingly, the stage moving distance S indicates the area of the trapezoid indicated by diagonal lines in the drawing, and the stage acceleration α, the stage maximum speed Vmax, the acceleration driving time t1, the constant speed driving time t2, and the deceleration driving time t3. Thus, it can be obtained by the following equation (4).
S = (1/2) × α × t1²+ Vmax * t2 + (1/2) * α * t3²  (4)
[0032]
Here, as can be seen from FIG. 8, the acceleration drive time t1 is the time to reach the stage maximum speed Vmax, and the deceleration drive time t3 is the time from the stage maximum speed Vmax to the speed 0.
t1 = t3 = Vmax / α.
Therefore, the above equation (4) is
S = Vmax²/ Α + Vmax × t2
The constant speed drive time t2 is
t2 = S / Vmax-Vmax / [alpha].
[0033]
From the above, the stage moving time Tstep can be obtained by the following equation (5).
Tstep = t1 + t2 + t3 + t4
= Vmax / α + (S / Vmax−Vmax / α) + Vmax / α + t4
= Vmax / α + S / Vmax + t4 (5)
Here, the stage moving distance S actually indicates the shot size.
[0034]
Next, a method for calculating the exposure time per shot in the stepper and scanner will be described.
In the case of a stepper, since shot exposure is performed with the stage stopped, the exposure time Texpo for one shot depends on the illuminance I of the exposure light on the wafer surface and the resist sensitivity (exposure amount) E as follows: ).
Texpo = E ÷ I (6)
[0035]
In the case of a scanner, since exposure is performed while scanning (scanning) at a constant speed in the Y direction within a shot, the exposure time can be obtained from the distance (length) in the Y direction of the exposure shot and the scanning speed (scanning speed). I can do it.
[0036]
Here, in the scan exposure, actual exposure is performed by a rectangular exposure slit orthogonal to the scanning direction. Therefore, when the scan speed Vscan, the width d of the exposure slit, the illuminance I of the exposure light on the wafer surface, and the exposure amount E, The exposure amount E can be expressed by the following formula.
E = I × (d ÷ Vscan)
Therefore, from the above equation, the scan speed Vscan is
Vscan = I ÷ E × d
It becomes.
[0037]
From the above, the exposure time Texpo in the case of the scanner can be obtained by the following equation (7) when the scan distance is Sscan.
Texpo = Sscan ÷ Vscan
= Sscan ÷ (I ÷ E × d)
= (Sscan × E) ÷ (I × d) (7)
Here, predetermined values are determined in the exposure apparatus for the acceleration α of the XY stage, the maximum speed Vmax, the exposure light illuminance I on the wafer surface, and the exposure slit width d depending on the shot size, the exposure conditions, or the exposure apparatus.
[0038]
Hereinafter, chip productivity per unit time of each shot layout is obtained based on an example.
FIG. 9 shows wafer size = 200.0 mm, shot size X = 18.0 mm, Y = 20.0 mm chip size X direction lx = 6.0 mm, Y direction ly = 10.0 mm, effective exposure area = radius 97.0 mm. It is a figure which shows the shot layout created with this shot layout creation method in the case of the exposure shot which consists of 3x2 6-chip structure.
[0039]
The number of shots of the four shot layouts created, the number of chips and the number of rows in the layout are:
For (a)
Number of shots = 85, number of chips = 441, number of rows = 10
For (b)
Number of shots = 87, number of chips = 448, number of rows = 10
For (c)
Number of shots = 83, number of chips = 442, number of rows = 9
For (d)
Number of shots = 85, number of chips = 444, number of rows = 9
Thus, conventionally, the shot layout (b) has been determined as the optimum shot layout.
[0040]
Next, for the four shot layouts in FIG. 9, the throughput in the stepper is obtained using the throughput calculation formula. This time, set exposure amount is 500.0J / m² And the set value of each device is stage acceleration = 5000 mm / sec.², Stage maximum speed = 250 mm / sec, stage settling time = 0.05 sec, wafer surface exposure light illuminance = 5000 W / m² Wafer supply time = 5.0 sec, wafer recovery time = 5.0 sec, alignment time = 10.0 sec.
[0041]
First, the X stage movement time Tx is calculated from the above equation (5) from the movement distance 18.0 mm.
Tx = 250/5000 + 18.0 / 250 + 0.05
= 0.172 sec
The Y stage moving time Ty is from the moving distance of 20.0 mm, from the above equation (5),
Ty = 250/5000 + 20.0 / 250 + 0.05
= 0.180 sec
It becomes.
[0042]
Next, the exposure time Texpo has an illuminance of 5000 W / m.² , Exposure 500.0J / m² From the above equation (6),
Texpo = 500 ÷ 5000 = 0.10 sec
It becomes.
[0043]
Next, the exposure processing time is calculated. From the above calculation, the stage moving time is X stage moving time Tx <Y stage moving time Ty. Therefore, the expression (3-2) is applied as the formula for calculating the exposure processing time, and exposure in each shot layout is performed. The processing time is as follows.
[0044]
In case of (a)
0.172 × 75 + 0.18 × 9 + 0.1 × 85
= 23.02 sec
For (b)
0.172 × 77 + 0.18 × 9 + 0.1 × 87
= 23.564 sec
For (c)
0.172 × 74 + 0.18 × 8 + 0.1 × 83
= 22.468 sec
For (d)
0.172 × 76 + 0.18 × 8 + 0.1 × 85
= 23.012 sec
[0045]
From the above, the throughput of each shot layout from (a) to (d) in FIG. 9 is obtained as follows.
[0046]
In case of (a)
3600 / (5.0 + 10.0 + 23.2 + 5.0)
= 83.68 wph
For (b)
3600 ÷ (5.0 + 10.0 + 23.564 + 5.0)
= 82.63 wph
For (c)
3600 / (5.0 + 10.0 + 22.468 + 5.0)
= 84.76 wph
For (d)
3600 / (5.0 + 10.0 + 23.012 + 5.0)
= 83.69 wph
[0047]
Finally, the amount of chip production per hour in each shot layout is obtained. The amount of chip production per hour is obtained by (throughput) × (total number of chips in each shot layout), and chip productivity in each shot layout under the above conditions is
For (a)
83.68 × 441 = 36902 chips
For (b)
82.63 × 448 = 37018 chips
For (c)
84.76 × 442 = 37463 chips
For (d)
83.69 × 444 = 37158 chips
Thus, it can be seen that the shot layout of (c) has the highest production amount per hour, that is, a shot layout with high productivity. As a result, the semiconductor manufacturer may use the shot layout (c) in the case of a semiconductor product that requires productivity in a short period of time.
[0048]
In the above, the operation of the present invention has been described in order. However, conditions such as productivity priority and priority on the number of chips in the wafer are set in advance, and an optimal shot layout that satisfies the conditions is automatically created. Anyway.
[0049]
The present invention can also be applied to a recording medium such as a magnetic disk or MO on which a program for using the shot layout creation method is recorded, and a semiconductor exposure apparatus using the shot layout creation method.
[0050]
(Embodiment of semiconductor production system)
Next, an example of a production system of a semiconductor device (a semiconductor chip such as an IC or LSI, a liquid crystal panel, a CCD, a thin film magnetic head, a micromachine, etc.) using the apparatus according to the present invention will be described. In this method, maintenance services such as troubleshooting, periodic maintenance, and software provision for manufacturing apparatuses installed in a semiconductor manufacturing factory are performed using a computer network outside the manufacturing factory.
[0051]
FIG. 10 shows the whole system cut out from a certain angle. In the figure, reference numeral 101 denotes a business office of a vendor (apparatus supply manufacturer) that provides a semiconductor device manufacturing apparatus. Examples of manufacturing apparatuses include semiconductor manufacturing apparatuses for various processes used in semiconductor manufacturing plants, such as pre-process equipment (lithographic apparatuses such as exposure apparatuses, resist processing apparatuses, etching apparatuses, heat treatment apparatuses, film forming apparatuses, and flattening apparatuses. As well as post-processing equipment (assembly equipment, inspection equipment, etc.). The office 101 includes a host management system 108 that provides a maintenance database for manufacturing apparatuses, a plurality of operation terminal computers 110, and a local area network (LAN) 109 that connects these to construct an intranet or the like. The host management system 108 includes a gateway for connecting the LAN 109 to the Internet 105, which is an external network of the office, and a security function for restricting access from the outside.
[0052]
On the other hand, 102 to 104 are manufacturing factories of semiconductor manufacturers as users of manufacturing apparatuses. The manufacturing factories 102 to 104 may be factories belonging to different manufacturers, or factories belonging to the same manufacturer (for example, a factory for a pre-process, a factory for a post-process, etc.). In each of the factories 102 to 104, a plurality of manufacturing apparatuses 106, a local area network (LAN) 111 that connects them together to construct an intranet, etc., and a host as a monitoring apparatus that monitors the operating status of each manufacturing apparatus 106 A management system 107 is provided. The host management system 107 provided in each factory 102 to 104 includes a gateway for connecting the LAN 111 in each factory to the Internet 105 which is an external network of the factory. As a result, the host management system 108 on the vendor's office 101 side can be accessed from the LAN 111 of each factory via the Internet 105, and access is permitted only to limited users due to the security function of the host management system 108. . Specifically, status information (for example, a symptom of a manufacturing apparatus in which a trouble has occurred) indicating the operating status of each manufacturing apparatus 106 is notified from the factory side to the vendor side via the Internet 105, and the notification is also handled. It is possible to receive response information (for example, information for instructing a coping method for trouble, coping software or data), maintenance information such as the latest software and help information from the vendor side. A communication protocol (TCP / IP) generally used on the Internet is used for data communication between each factory 102 to 104 and the vendor office 101 and data communication on the LAN 111 in each factory. . Instead of using the Internet as an external network outside the factory, it is also possible to use a high-security dedicated line network (such as ISDN) without being accessible from a third party. Further, the host management system is not limited to the one provided by the vendor, and the user may construct a database and place it on the external network, and allow access to the database from a plurality of factories of the user.
[0053]
FIG. 11 is a conceptual diagram showing the overall system of the present embodiment cut out from an angle different from that in FIG. In the previous example, a plurality of user factories each equipped with a manufacturing apparatus and a management system of a vendor of the manufacturing apparatus are connected via an external network, and production management of each factory or at least one unit is performed via the external network. Data communication of manufacturing equipment was performed. On the other hand, in this example, a factory equipped with a plurality of vendors' manufacturing devices and a management system of each vendor of the plurality of manufacturing devices are connected by an external network outside the factory, and maintenance information of each manufacturing device is obtained. Data communication. In the figure, reference numeral 201 denotes a manufacturing factory of a manufacturing apparatus user (semiconductor device manufacturer), and a manufacturing apparatus that performs various processes on the manufacturing line of the factory, in this case, an exposure apparatus 202, a resist processing apparatus 203, and a film forming processing apparatus. 204 has been introduced. In FIG. 11, only one manufacturing factory 201 is depicted, but actually, a plurality of factories are similarly networked. Each device in the factory is connected by a LAN 206 to form an intranet, and the host management system 205 manages the operation of the production line.
[0054]
On the other hand, each business office of a vendor (apparatus supply manufacturer) such as the exposure apparatus manufacturer 210, the resist processing apparatus manufacturer 220, and the film formation apparatus manufacturer 230 has host management systems 211, 221 for performing remote maintenance of the supplied devices. 231 and these comprise a maintenance database and an external network gateway as described above. The host management system 205 that manages each device in the user's manufacturing factory and the vendor management systems 211, 221, and 231 of each device are connected by the external network 200, which is the Internet or a dedicated line network. In this system, if a trouble occurs in any one of a series of production equipment on the production line, the operation of the production line is suspended, but remote maintenance via the Internet 200 is received from the vendor of the troubled equipment. Therefore, it is possible to respond quickly and to minimize downtime of the production line.
[0055]
Each manufacturing apparatus installed in the semiconductor manufacturing factory includes a display, a network interface, and a computer that executes network access software stored in a storage device and software for operating the apparatus. The storage device is a built-in memory, a hard disk, or a network file server. The network access software includes a dedicated or general-purpose web browser, and provides, for example, a user interface having a screen as shown in FIG. 12 on the display. The operator who manages the manufacturing apparatus in each factory refers to the screen, and the manufacturing apparatus model 401, serial number 402, trouble subject 403, date of occurrence 404, urgency 405, symptom 406, countermeasure 407, progress 408, etc. Enter the information in the input field on the screen. The input information is transmitted to the maintenance database via the Internet, and appropriate maintenance information as a result is returned from the maintenance database and presented on the display. Further, the user interface provided by the web browser further realizes hyperlink functions 410 to 412 as shown in the figure, and the operator can access more detailed information on each item, or the latest software used for the manufacturing apparatus from the software library provided by the vendor. Version software can be pulled out, and operation guides (help information) for use by factory operators can be pulled out. Here, the maintenance information provided by the maintenance database includes the information related to the present invention described above, and the software library also provides the latest software for realizing the present invention.
[0056]
Next, a semiconductor device manufacturing process using the production system described above will be described. FIG. 13 shows the flow of the entire manufacturing process of the semiconductor device. In step 1 (circuit design), a semiconductor device circuit is designed. In step 2 (mask production), a mask on which the designed circuit pattern is formed is produced. On the other hand, in step 3 (wafer manufacture), a wafer is manufactured using a material such as silicon. Step 4 (wafer process) is called a pre-process, and an actual circuit is formed on the wafer by lithography using the prepared mask and wafer. The next step 5 (assembly) is called a post-process, and is a process for forming a semiconductor chip using the wafer produced in step 4, and is an assembly process (dicing, bonding), packaging process (chip encapsulation), etc. Process. In step 6 (inspection), the semiconductor device manufactured in step 5 undergoes inspections such as an operation confirmation test and a durability test. Through these steps, the semiconductor device is completed and shipped (step 7). The pre-process and post-process are performed in separate dedicated factories, and maintenance is performed for each of these factories by the remote maintenance system described above. In addition, information for production management and apparatus maintenance is communicated between the pre-process factory and the post-process factory via the Internet or a dedicated network.
[0057]
FIG. 14 shows a detailed flow of the wafer process. In step 11 (oxidation), the wafer surface is oxidized. In step 12 (CVD), an insulating film is formed on the wafer surface. In step 13 (electrode formation), an electrode is formed on the wafer by vapor deposition. In step 14 (ion implantation), ions are implanted into the wafer. In step 15 (resist process), a photosensitive agent is applied to the wafer. In step 16 (exposure), the circuit pattern of the mask is printed onto the wafer by exposure using the exposure apparatus described above. In step 17 (development), the exposed wafer is developed. In step 18 (etching), portions other than the developed resist image are removed. In step 19 (resist stripping), unnecessary resist after etching is removed. By repeating these steps, multiple circuit patterns are formed on the wafer. Since the manufacturing equipment used in each process is maintained by the remote maintenance system described above, it is possible to prevent troubles in advance and to recover quickly even if troubles occur. Compared to conventional semiconductor devices Productivity can be improved.
[0058]
【The invention's effect】
As described above, according to the present invention, it is possible to obtain the throughput for the created shot layout and further obtain the chip productivity per unit time. This makes it possible to obtain an optimal shot layout that meets the manufacturing requirements of the semiconductor manufacturer.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a projection exposure apparatus for semiconductor manufacturing to which the present invention is applied.
FIG. 2 is a diagram showing a chip arrangement at the time of chip layout creation in the shot layout creation method according to the embodiment of the present invention.
FIG. 3 is a diagram showing an example of a chip layout created by a shot layout creation method according to an embodiment of the present invention.
FIG. 4 is a diagram showing a shot layout creation method in the shot layout creation method according to the embodiment of the present invention.
FIG. 5 is a diagram showing an example of a shot layout created by the shot layout creation method according to the embodiment of the present invention.
FIG. 6 is a flowchart showing exposure processing steps for one wafer in the throughput calculation method according to the embodiment of the present invention.
FIG. 7 is a diagram showing an exposure order of shots in the throughput calculation method according to the embodiment of the present invention.
FIG. 8 is a diagram showing the movement time of the wafer stage in the throughput calculation method according to the embodiment of the present invention.
FIG. 9 is a shot layout example as an example for obtaining chip productivity per unit time according to the embodiment of the present invention;
FIG. 10 is a conceptual diagram of a semiconductor device production system using the apparatus according to the present invention as seen from a certain angle.
FIG. 11 is a conceptual view of a semiconductor device production system using the apparatus according to the present invention as seen from another angle.
FIG. 12 is a specific example of a user interface.
FIG. 13 is a diagram illustrating a flow of a device manufacturing process.
FIG. 14 is a diagram illustrating a wafer process.
[Explanation of symbols]
50: illumination optical system, 51: reticle (original), 52: reticle stage, 53: reduction projection lens, 54: autofocus detector, 55: wafer (substrate), 56: wafer chuck, 57: wafer stage, 58: Mirror, 59: Laser interferometer type length measuring device, 60: Console unit, 61: Alignment detector.

Claims (4)

In a layout creation method for creating a chip layout and a shot layout when exposing an original pattern on a substrate,
A layout creating step of creating a plurality of chip layouts and shot layouts corresponding to each of the plurality of chip layouts;
A calculation step of calculating a production amount of a chip per unit time in each shot layout based on the plurality of chip layouts and a shot layout corresponding to each of the plurality of chip layouts ;
And obtaining a chip layout having the largest chip production amount per unit time and a corresponding shot layout based on the chip production amount per unit time in each of the shot layouts calculated in the calculation step. A layout creation method characterized by that. The calculation step according to claim 1, wherein each shot is calculated from the number of chips in each chip layout, the number of shots in the shot layout corresponding to each chip layout, the moving time of the stage for moving the substrate, and the exposure time in each shot. The layout creation method according to claim 1, wherein a production amount of chips per unit time is calculated in the layout. Recording medium characterized by recording a program for using the layout creation method according to claim 1 or 2. Using the chip layout obtained by the layout creation method according to claim 1 and a shot layout corresponding to the chip layout, exposing a pattern of an original to a photosensitive agent applied to a substrate;
And a step of developing the photosensitive agent .

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