JP3914110B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device related to electrical characteristic testing and wire bonding.
[0002]
[Prior art]
In order to manufacture an IC, the electrical characteristics of a semiconductor chip formed on a wafer are subjected to an electrical characteristic test (test) to identify and select non-defective / defective products, and then divided and separated into semiconductor chips. Then, each of the non-defective semiconductor chips is mounted to complete a desired IC.
[0003]
Normally, in the above-described mounting process of a semiconductor chip, after mounting the semiconductor chip on a substrate, electrode pads provided on the semiconductor chip and external terminals such as leads are connected by wire bonding. However, in the test process before this mounting process, the surface of the electrode pad formed of aluminum metal or the like becomes rough because the probe is brought into contact with the electrode pad. This surface roughness causes the above-mentioned wire bonding failure. Such a problem becomes more apparent in a custom product of a semiconductor device. This is because custom products have a wide variety of test items in the electrical characteristic test, and the number of times the probe is brought into contact with the electrode pad varies depending on the product.
[0004]
In order to solve such a problem, many conventional techniques have proposed to provide a probing pad on a semiconductor chip in addition to the electrode pad. An example of this will be described with reference to FIG. This conventional technique is disclosed in JP-A-5-160216. Here, a plurality of probing pads or bonding pads are provided for one wiring.
[0005]
FIG. 5 is a plan view showing a semiconductor chip. As shown in FIG. 5, a circuit portion 102 is formed on a semiconductor chip 101, and a wiring 103 for extracting a signal from the circuit portion 102 is branched from the middle to provide two probing pads 104 and 104a, respectively. .
[0006]
If comprised in this way, the electrical characteristic test and wire bonding of the probing pad 104,104a installed in parallel can be performed a plurality of times using separate probing pads. Therefore, the probe is not brought into contact with the same portion of the probing pad for another test, and the result of the test is stabilized. Further, wire bonding is not performed on the probe trace, and the reliability of wire bonding is improved.
[0007]
[Problems to be solved by the invention]
In the conventional technique, when the electrical characteristic test of a semiconductor chip is performed a plurality of times, another test must be performed by bringing the probe into contact again with the electrode pad on which the probe mark has been generated in the previous test. The resulting test results are unstable. Further, as described above, there is a problem that bonding reliability is lowered when a wire is bonded to a probe mark.
[0008]
As described above, when a plurality of probing pads are provided on a semiconductor chip to solve the above problems, the area occupied by the pads on the semiconductor chip is increased, and the circuit integration degree of the semiconductor chip is reduced. become. This becomes a big obstacle for high integration of semiconductor devices.
[0009]
An object of the present invention is to solve the above-mentioned problems, and it is possible to perform a plurality of electrical characteristic tests and improve the reliability of wire bonding by a simple method. is there.
[0010]
[Means for Solving the Problems]
To this end, the method of manufacturing a semiconductor device according to the present invention performs a test of electrical characteristics of the circuit portion of the semiconductor chip by contacting the probe with the electrode pad of the semiconductor chip and stores the number of times the probe is brought into contact with the electrode pad. And a step of wire bonding to the electrode pad by changing bonding conditions according to the number of times the probe is brought into contact with the connection between the electrode pad for mounting the semiconductor chip and an external terminal. Here, the number of times the probe is brought into contact is memorized by irradiating the surface of the semiconductor chip with laser light. Alternatively, the number of times the probe is brought into contact is stored in units of the semiconductor chip in a storage medium attached to the apparatus for performing the electrical characteristic test.
[0011]
In the present invention, the bonding weight in the wire bonding is increased as the number of times of contacting the probe is increased. Alternatively, the ultrasonic power in the wire bonding is increased with an increase in the number of times the probe is brought into contact. Here, the electrode pad surface is formed of an aluminum metal film.
[0012]
In the present invention, wire bonding can be performed with high reliability even if a wire is bonded to the probe trace of the electrode pad generated in the test process of the semiconductor chip. In addition, it is not necessary to provide a plurality of probing pads on the semiconductor chip, and the problem that the area occupied by the electrode pads on the semiconductor chip, which has occurred in the prior art, is increased and the degree of circuit integration of the semiconductor chip is reduced. The
[0013]
In this manner, the reliability of the mounted semiconductor device is improved, and the semiconductor device can be easily increased in density or functionality.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a schematic diagram of a measuring apparatus used in a semiconductor chip test process. FIG. 1B is a plan view of the semiconductor chip. FIG. 2 is a schematic diagram for explaining a mounting process such as bonding. And FIG. 3 is sectional drawing of the order of a manufacturing process for demonstrating the effect of this invention.
[0015]
As shown in FIG. 1A, in the prober 1 constituting the measuring apparatus, the wafer 3 is fixed to the surface of the stage 2 with a vacuum chuck. Then, the probe card 4 is attached to the upper part of the wafer 3 so as to face the probe 5 and the probe 5 is brought into contact with the electrode pad on the wafer 3 to measure the electrical characteristics of a predetermined semiconductor chip. Here, in the present invention, a dot mark 12 described later is formed by the laser marker 6 provided on the probe card 4.
[0016]
The prober 1 sends the coordinate position of the semiconductor chip 9 to be described later in the wafer 3 and the information of its lot No. and wafer No. to the identification device 7. Thereby, the number of times of contact (contact) of the probe with the electrode pad 11 of the semiconductor chip 9 is obtained, and each dot mark is formed for each contact. Next, the prober 1 transmits a test start signal to the tester 8 to measure the electrical characteristics. After the test is completed, an end signal is transmitted from the tester 8 to the prober 1, and the stage 2 moves to another semiconductor chip. By repeating this, the wafer 3 is tested.
[0017]
The dot mark will be described with reference to FIG. Many semiconductor chips 9 as shown in FIG. 1B are formed on the wafer 3. In this semiconductor chip 9, a circuit portion 10 is formed, and a large number of electrode pads 11 are formed in the peripheral portion of the semiconductor chip 9. The dot mark 12 described above is formed in a predetermined region of the semiconductor chip 9. In FIG. 1B, three dot marks are formed in a dot shape by laser light irradiation. In this case, the probe 5 is in contact with the electrode pad 11 of the semiconductor chip 9 three times.
[0018]
Next, the semiconductor chip 9 is separated through dicing of the wafer 3. And it mounts in a mounting package and what is called wire bonding is made. In this mounting process, first, classification and classification are performed according to the number of dot marks 12 on the semiconductor chip 9. That is, the semiconductor chip 9 is sorted according to the number of contacts.
[0019]
Next, the semiconductor chips 9 having the same number of contacts are mounted on the bonding apparatus 13 shown in FIG. 2 and controlled to the same conditions for wire bonding. Here, the bonding conditions to be controlled include the substrate temperature of the bonding apparatus 13, the bonding weight, the ultrasonic power amount, and the bonding time. These conditions are optimally set through the control device 14 shown in FIG. 2 corresponding to the number of contacts. For example, the bonding weight in wire bonding is increased with an increase in the number of times the probe is contacted. Alternatively, the ultrasonic power in wire bonding is increased with an increase in the number of times the probe is brought into contact.
[0020]
Next, the above-described series of manufacturing steps and effects thereof will be described with reference to FIG. As shown in FIG. 3A, the probe 5 is applied to the surface of the electrode pad 11 on the semiconductor chip 9 in the test process. Usually, the electrode pad 11 is made of a metal having a relatively high ductility such as aluminum. For this reason, probe marks 15 and 16 are formed on the surface of the electrode pad 11 every time the probe contacts. In the case of FIG. 3, probe marks 15, 16, and 17 and three probe marks are left on the surface of the electrode pad 11, as shown in FIG. 12 is formed. Next, in the above-described mounting process, the bonding wire 18 is connected to the electrode pad 11 on the semiconductor chip 9 as shown in FIG. 3C under the optimized wire bonding conditions corresponding to the three dot marks. Is done. Here, the optimization of the bonding conditions eliminates the influence of the probe traces 15, 16, and 17 generated in the test process, and enables highly reliable wire bonding.
[0021]
In this way, the present invention completely solves the problem that bonding reliability is lowered even if a wire is bonded to a probe mark generated in a test process. Further, in the present invention, it is not necessary to provide a plurality of probing pads on the semiconductor chip, and the area occupied by the electrode pads on the semiconductor chip, which has occurred in the prior art, is increased, and the circuit integration of the semiconductor chip is reduced. This problem can be solved by the simple method of the present invention.
[0022]
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a schematic diagram of another measuring apparatus used in the semiconductor chip test process.
[0023]
As shown in FIG. 4, in the prober 1 constituting the measuring apparatus, the wafer 3 is fixed to the surface of the stage 2 with a vacuum chuck as in FIG. Then, the probe card 4 is attached to the upper part of the wafer 3 so as to face the probe 3 and the probe 5 is applied to the electrode pad on the wafer 3 to measure the electrical characteristics of a predetermined semiconductor chip.
[0024]
The prober 1 sends the coordinate position of the semiconductor chip 9 in the wafer 3, the information of its lot No. and wafer No., and the above contact count information to the storage device 19 and holds the data in units of semiconductor chips. The prober 1 transmits a test start signal to the tester 8 to measure the electrical characteristics. After the test is completed, the prober 1 transmits an end signal to the prober 1 from the tester 8, and the stage 2 moves to another semiconductor chip. By repeating this, the wafer 3 is tested.
[0025]
Next, as described above, the semiconductor chips 9 are separated through dicing of the wafer 3, mounted on a mounting package, and further wire bonded. In this mounting process, the bonding conditions are optimized based on the data stored in the storage device 19. Here, the bonding conditions to be controlled are the substrate temperature, bonding weight, ultrasonic power amount, and bonding time of the bonding apparatus 13 described in the first embodiment. This optimization is performed through the control device 14 described in FIG. 2 corresponding to the number of contacts. In this way, the effect described in the first embodiment is produced.
[0026]
The present invention is not limited to the above-described embodiment, and the embodiment can be appropriately changed within the scope of the technical idea of the present invention.
[0027]
【The invention's effect】
As described above, in the present invention, in the semiconductor chip test process, the wire bonding conditions in the semiconductor chip mounting process are changed in accordance with the number of times the probe is brought into contact with the electrode pad. For example, the bonding weight in wire bonding is increased with an increase in the number of times the probe is contacted. Alternatively, the ultrasonic power in the wire bonding is increased.
[0028]
In this manner, the reliability of the mounted semiconductor device is improved, and the semiconductor device can be easily increased in density or functionality.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a measuring device used for an electrical characteristic test and a plan view of a semiconductor chip for explaining a first embodiment of the present invention.
FIG. 2 is a schematic bonding diagram for explaining the present invention.
FIG. 3 is a cross-sectional view in order of the manufacturing process for explaining the effect of the present invention.
FIG. 4 is a schematic diagram of a measuring device used in an electrical characteristic test for explaining a second embodiment of the present invention.
FIG. 5 is a plan view of a semiconductor chip for explaining a conventional technique.
DESCRIPTION OF SYMBOLS 1 Prober 2 Stage 3 Wafer 4 Probe card 5 Probe 6 Laser marker 7 Identification device 8 Tester 9, 101 Semiconductor chip 10, 102 Circuit part 11 Electrode pad 12 Dot mark 13 Bonding device 14 Control device 15, 16, 17 Probe mark 18 Bonding Wire 19 Memory device 101 Semiconductor chip 102 Circuit portion 103 Wiring 104, 104a Probing pad

Claims (6)

A step of contacting a probe with an electrode pad of a semiconductor chip to perform an electrical characteristic test of a circuit portion of the semiconductor chip and storing the number of times the probe is brought into contact with the electrode pad; and the electrode for mounting the semiconductor chip And a step of wire bonding to the electrode pad by changing bonding conditions in accordance with the number of times the probe is brought into contact with the connection between the pad and the external terminal. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the number of times the probe is brought into contact is stored by irradiating the surface of the semiconductor chip with laser light. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the number of times the probe is brought into contact is stored for each semiconductor chip in a storage medium attached to an apparatus for performing the electrical characteristic test. 4. The method of manufacturing a semiconductor device according to claim 1, wherein a bonding weight in the wire bonding is increased with an increase in the number of times the probe is brought into contact. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the ultrasonic power in the wire bonding is increased with an increase in the number of times the probe is brought into contact. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the electrode pad surface is formed of an aluminum metal film.

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