JP3914151B2 - Data conversion circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device that operates in synchronization with a clock.
[Prior art]
With the increase in CPU speed, semiconductor memory devices such as DRAM (dynamic random access memory) require that data signals be input and output at a higher signal frequency to increase the data transfer speed. Is done. As a semiconductor memory device that meets this requirement, an SDRAM (synchronous dynamic random access memory) realizes high-speed operation by operating in synchronization with an input clock signal.
FIG. 1 shows an example of a circuit configuration around a DRAM memory cell. The circuit in FIG. 1 includes a capacitor 501, NMOS transistors 502 to 512, a PMOS transistor 513, PMOS transistors 521 and 522, and NMOS transistors 523 and 524. The PMOS transistors 521 and 522 and the NMOS transistors 523 and 524 constitute a sense amplifier 520.
One-bit information is stored in the capacitor 501 that is a memory cell. When the sub word line selection signal SW is selected, the NMOS transistor 502 which is a cell gate is turned on, and the data in the capacitor 501 is read out to the bit line BL. At this time, the bit line transfer signal BLT1 is HIGH, and the NMOS transistors 503 and 504 are in a conductive state. On the other hand, the bitsen transfer signal BLT0 is LOW, and the NMOS transistors 505 and 506 are non-conductive. Accordingly, the data of the bit lines BL and / BL are read into the sense amplifier 520 via the NMOS transistors 503 and 504. The sense amplifier 520 operates when the sense amplifier drive signals SA1 and SA2 are activated and the transistors 513 and 512 are turned on, and amplifies the data on the bit lines BL and / BL. When the column line selection signal CL is selected, the amplified data of the bit lines BL and / BL is read to the data buses DB and / DB via the NMOS transistors 510 and 511 which are column gates.
In the case of data writing, the data on the data buses DB and / DB are stored in the capacitor 501 through the reverse procedure of the case of reading.
FIG. 2 is a timing chart for explaining a data read operation in the DRAM.
In the case of data reading as shown in FIG. 2, as commands for the DRAM, a precharge command (PRE) for precharging the bit lines BL and / BL to a predetermined voltage, a / RAS command (R) for row access, The / CAS command (C) for column access is sequentially input.
With reference to FIGS. 1 and 2, timing control in the case of data reading will be described below.
When the / RAS command is input, the bit line transfer signal BLT0 becomes LOW (BLT1 is HIGH), and only the bit lines BL and / BL are connected to the sense amplifier 520. At the same time, the precharge signal PR in FIG. 1 is dropped to LOW, and the reset state of the bit line BL is released. Further, a specific word line is selected by setting the main word line selection signal MW to HIGH and the sub word line selection signal SW to HIGH. As a result, the NMOS transistor 502 is turned on, and the data in the capacitor 501 is read out to the bit line BL. As shown in FIG. 2, data appears on the bit line BL at the timing when the main word line selection signal MW and the sub word line selection signal SW become HIGH.
Next, in order to drive the sense amplifier 520, the sense amplifier drive signals SA1 and SA2 are activated, and the NMOS transistor 512 and the PMOS transistor 513 are turned on. As shown in FIG. 2, when the sense amplifier 520 is driven, the data on the bit lines BL and / BL are amplified and the amplitude is increased.
When the amplitude increases, the column line selection signal CL becomes HIGH corresponding to the / CAS command, and a specific column is selected. The NMOS transistors 510 and 511 (column gates) of the selected column are turned on, and data is read to the data buses DB and / DB. The data read to the data buses DB and / DB is output from the DRAM as a data signal DQ, and, for example, 4-bit continuous data reading is performed.
When a precharge command is input, the precharge signal PR becomes HIGH at an appropriate timing, the NMOS transistors 507 to 509 are turned on, and the bit lines BL and / BL are precharged to a predetermined potential VPR. As a result, the bit lines BL and / BL are reset as shown in FIG. 2 to prepare for data reading corresponding to the next / RAS command.
In the DRAM configured as described above, when data of the same row address (same word line) is continuously read, data of different column addresses are sequentially read by sequentially selecting different columns. I can do it. The sense amplifier 520 of FIG. 1 is provided for each of a plurality of columns, and the plurality of sense amplifiers 520 store data of different column addresses at the same row address. Therefore, if different columns are sequentially selected and the data already stored in the sense amplifier 520 is read, the data can be read continuously.
However, when data at different row addresses (different word lines) is to be read (that is, in the case of page miss hit), data from the memory cell selected by this word line is newly transferred to the bit lines BL and / BL. It is necessary to read out. Further, in order to read new data to the bit lines BL and / BL, it is necessary to precharge the bit lines BL and / BL in advance. Accordingly, when data of a different row address is read after data of a certain row address is read, a large time interval is generated between the read data as shown in FIG. In the operation example of FIG. 2, there is an interval of 10 clocks between reading data of different row addresses.
The occurrence of a large time interval between read data when reading different row addresses in this way has been an impediment to realizing a high-speed data read operation.
In order to successively read different row addresses from one bank, it is conceivable to make row access pipeline. In the conventional DRAM as described above, column access is pipelined to enable continuous reading of column address data, but row access is not pipelined.
The process from the row address input to the data output is divided into a first stage command decode and peripheral circuit operation, a second stage sense amplifier operation, and a third stage data output operation. In order to perform a row pipeline operation, first, the first stage operation is executed for the first row access. When the first row access starts the second stage operation, it starts the first stage operation of the second row access, and when the first row access performs the third stage operation, The second stage operation is performed for the row access and the first operation is performed for the third row access. In this way, if the operations of the first stage, the second stage, and the third stage for different row accesses are executed in parallel in each operation cycle, a row pipeline operation can be realized. I can do it.
[Problems to be solved by the invention]
However, in the conventional DRAM, when a plurality of column addresses are read continuously from the same row address, the burst length can be changed. That is, the mode is set with the number of data to be continuously read as the burst length, and the number of data indicated by the burst length is read from the continuous column addresses. In this case, the period during which the sense amplifier is operating in order to access the continuous column address data, that is, the period of the second stage sense amplifier operation varies depending on the burst length to be set in the mode.
If the operation period of the second stage is changed by the mode setting in this way, it is impossible to execute a pipeline operation without disturbance for the row system. That is, when viewed from the memory controller side, the / RAS command (or activation command) cannot be continuously input at regular intervals. Similarly, it is necessary to change the input timing of the precharge command according to the burst length, making it difficult to execute a pipeline operation related to the row system.
Accordingly, an object of the present invention is to provide a semiconductor memory device capable of high-speed access by realizing pipeline operation of row addresses when accessing different row addresses.
[Means for Solving the Problems]
The semiconductor memory device according to the present invention simultaneously selects a plurality of sense amplifiers that receive and hold data of a memory cell corresponding to a selected word line via a bit line, and a plurality of column gates according to a column address. A column decoder for reading out parallel data of a plurality of bits from the selected sense amplifier, a data conversion unit for converting the parallel data into serial data, and a row access signal for selecting the word line are generated. And a precharge signal generating unit that generates an internal precharge signal after one delay time and resets the bit line and the plurality of sense amplifiers.
In the above invention, when the row address input to the data output are divided into the first stage command decode and peripheral circuit operation, the second stage sense amplifier operation, and the third stage data output operation, The period of the second-stage sense amplifier operation can be made constant regardless of the burst length. That is, it is only necessary to drive the sense amplifier for a fixed period in order to open a plurality of column gates at a time and read data in parallel. As a result, the period of the second-stage sense amplifier operation can be made constant regardless of the burst length, and a low-level pipeline operation without disturbance can be executed. In addition, when the user arbitrarily sets the precharge timing from the outside, this arbitraryness may be a factor disturbing the pipeline operation. In the present invention, this factor is obtained by executing the reset operation by the internal precharge signal. Can be wiped out. Furthermore, immediately after data is read from the sense amplifier, precharge can be executed at an optimal timing, and data can be read in a high-speed cycle close to the limit of the sense amplifier's operating capability. .
In the present invention, the data conversion unit selects a predetermined number of bits of the parallel data in response to the burst length signal and outputs the selected data as serial data. Therefore, it is possible to read data according to different burst length settings while executing a disturbance-free pipeline operation.
[0002]
In the present invention, since a plurality of data are read from the sense amplifier in parallel for one row access, converted into serial data and output to the outside of the semiconductor memory device, continuous data output is realized. I can do it.
In the present invention, the row access instruction and the column access instruction are input to the semiconductor memory device as a single packet. Therefore, it is possible to shorten the time interval between instruction inputs in response to shortening of row access. For example, the row access command and the column access command may be input in response to two successive clock pulses.
In the present invention, the precharge signal generation unit is characterized in that the bit line and the sense amplifier are reset by an internal precharge signal immediately after data is read from the sense amplifier. Therefore, the interval between row accesses can be shortened to the maximum by automatically precharging the sense amplifier immediately after data is accessed.
In the present invention, the precharge signal generation unit can be configured with a simple circuit structure using a delay element array that delays the signal by the first delay time.
In the present invention, the sense amplifier is divided into a plurality of sense amplifier blocks, and the row access operation is executed only for the sense amplifier of the selected sense amplifier block. Therefore, by reducing the number of sense amplifiers to be driven, the load of the control signal necessary for the low access operation is reduced and high-speed signal switching is realized, and the high-speed signal corresponding to the shortening of the time interval between the low accesses. Control can be achieved.
The present invention further includes a word decoder corresponding to each of the plurality of sense amplifier blocks, and the memory cell selected by the word decoder is connected to the bit line only for the selected sense amplifier block during row access. It is characterized by that. Therefore, by providing a word decoder for each sense amplifier block, it is possible to reduce the load of the word selection signal necessary for the row access operation, and a high-speed word selection signal corresponding to the shortening of the time interval between row accesses. Control can be achieved.
The present invention further includes a bit line transfer signal generation unit corresponding to each of the plurality of sense amplifier blocks, and the bit line transfer signal generation unit senses the bit line only for the selected sense amplifier block during row access. It is connected to an amplifier. Therefore, by providing a bit line transfer signal generation unit for each sense amplifier block, it is possible to reduce the load of the bit line transfer signal necessary for the row access operation, which corresponds to shortening the time interval between row accesses. High speed bit line transfer signal control can be achieved.
The present invention further includes a sense amplifier drive signal generation unit corresponding to each of the plurality of sense amplifier blocks, and the sense amplifier drive signal generation unit drives the sense amplifier only for the selected sense amplifier block during low access. It is characterized by doing. Therefore, by providing a sense amplifier drive signal generation unit for each sense amplifier block, it is possible to reduce the load of the sense amplifier drive signal necessary for the row access operation, which corresponds to shortening the time interval between row accesses. High-speed sense amplifier drive signal control can be achieved.
In the present invention, the semiconductor memory device further includes a plurality of banks, each of the plurality of banks including the memory cell, the sense amplifier, and the bit line, and a plurality of sense amplifiers in each of the plurality of banks. It is divided into sense amplifier blocks. Therefore, the semiconductor memory device according to the present invention can be composed of a plurality of banks.
The present invention is characterized by including a bit line transfer signal generation unit provided for each of the plurality of sense amplifier blocks. Therefore, the chip area of the semiconductor memory device can be reduced as compared with the case where the bit line transfer signal generation unit is provided in each sense amplifier block.
In the present invention, when row access instructions are continuously input, a series of processes from when data in a memory cell appears on a bit line until the sense amplifier amplifies the data and thereafter resets the bit line and the sense amplifier. The operation is continuously repeated at the same cycle without being interrupted. Therefore, since the pipeline operation based on the configuration suitable for the pipeline operation can be executed with respect to the row access, the continuous row access operation is performed without interruption in a high-speed cycle close to the limit of the operation capability of the sense amplifier. I can do it.
The present invention further includes a direct sense amplifier circuit for reading data held by the sense amplifier to the data bus via the column gate. Therefore, the potential level of the bit line is not changed by the read operation, the timing for precharging the bit line can be advanced, and the operation cycle can be speeded up.
In the present invention, the row address and the column address are received at the same timing of the clock signal input from the outside. Therefore, even when the clock frequency is set low, the time from the row access command to the data read can be kept constant.
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
FIG. 3 shows a block diagram of a DRAM according to the present invention.
3 includes a plurality of input buffers 11, a packet command decoder 12, a RAS generation unit 13, a PRE generation unit 14, a control unit 15, a predecoder 16, a word decoder 18, a BLT decoder 19, an SA generation unit 20, 4 decoder 21, CAS generation unit 22, control unit 23, predecoder 24, column decoder 25, core circuit 26, RB generation unit 27, read buffer 28, conversion unit 29, output buffer 30, and mode register 31.
A data read operation of the DRAM 10 of FIG. 3 will be described first with respect to a basic operation portion similar to that of a general DRAM.
A clock signal, a control signal, and an address signal are input to the input buffer 11 from the outside of the DRAM 10. The clock signal is supplied to each component in the DRAM 10 in order to synchronously control the operation of the DRAM 10. The control signal is decoded by the packet command decoder 12 and controls the RAS generation unit 13 and the CAS generation unit 22 according to the decoding result. The address signal is supplied to a row address predecoder 16 and a column address predecoder 24.
When an activation command ACT that is a control signal corresponding to the conventional / RAS signal is input, the RAS generation unit 13 generates a signal RASZ that is an internal RAS signal. The RAS generation unit 13 is for generating a signal RASZ continuously and executing a refresh operation when a refresh command is input, and generating a signal RASZ once when an activation command ACT is input. The signal RASZ is a signal for instructing the sense amplifier to read data in the memory cell, and is supplied to the control unit 15. Upon receiving the signal RASZ, the control unit 15 controls the SA generation unit 20 to generate the sense amplifier drive signals SA1 and SA2 at appropriate timing. The 1/4 decoder 21 is a decoder for selecting one subword decoder from four subword decoders subordinate to the selected main word decoder in the conventional hierarchical word decoding system.
The row address predecoder 16 latches and predecodes the supplied row address. The predecode result is supplied to the word decoder 18, the BLT decoder 19, and the ¼ decoder 21. The predecoder 16 includes a block decoder 17 and selects one of a plurality of memory blocks arranged in the DRAM 10. Only in the selected memory block, the word decoder 18, the BLT decoder 19, the SA generation unit 20, and the 1/4 decoder 21 operate, and the data is read from the memory cell in the core circuit 20 and stored in the sense amplifier. To do.
The core circuit 26 includes memory cells 501 shown in FIG. 1 arranged in an array with respect to rows and columns, and the sense amplifier 520 shown in FIG. 1 is provided for each column. By the row address read operation, data of a plurality of memory cells corresponding to the word line selected by the row address is stored in the plurality of sense amplifiers 520.
The CAS generation unit 22 generates an internal CAS signal when a read command RD that is a control signal corresponding to the conventional / CAS signal is input. The internal CAS signal is a signal for instructing to read the data of the sense amplifier 520 from the core circuit 26 to the read buffer 28, and is supplied to the control unit 23. When receiving the internal CAS signal, the control unit 23 controls the column decoder 25 to generate the column line selection signal CL at an appropriate timing.
The column address predecoder 24 latches and predecodes the supplied column address. The predecode result is supplied to the column decoder 25 and also to the RB generation unit. The column decoder 25 supplies a column line selection signal CL to the column specified by the column address, reads data from the sense amplifier 520 of the column, and supplies it to the read buffer 28. The RB generation unit 27 supplies the signal RB to the read buffer 28 at an appropriate timing, and causes the read buffer 28 to read data.
The read buffer 28 amplifies the read data, and the data is sent out of the DRAM 10 via the output buffer 30.
In addition to the above basic operation, the DRAM 10 according to the present invention realizes a raw pipeline operation by providing the packet command decoder 12, the PRE generation unit 14, and the conversion unit 29.
When receiving the signal RASZ that is an internal RAS signal, the PRE generation unit 14 generates the precharge signal PRE after a predetermined time has elapsed. The internally generated precharge signal PRE resets the RAS generation unit 13 to perform a precharge operation, similarly to the case where the precharge signal PRE is supplied from the outside. This precharge operation by the internally generated precharge signal PRE is hereinafter referred to as self-precharge.
When data is read from the core circuit 26, the data at successive column addresses of the sense amplifier 520 is read as parallel data. This parallel data is supplied to the conversion unit 29 via the read buffer 28. The conversion unit 29 converts parallel data into serial data, and supplies a predetermined number of serial data to the output buffer 30 according to the burst length set in the mode register 31.
In the DRAM according to the present invention shown in FIG. 3, by reading data from the sense amplifier 520 in parallel, from the row address input to the data output, the first stage command decode and peripheral circuit operation, the second stage sense amplifier operation, and When considered separately for the third-stage data output operation, the period of the second-stage sense amplifier operation can be made constant regardless of the burst length. While the sense amplifier is open (driven), it is necessary to open the column gate of the selected column and read the data from the sense amplifier. The period during which the sense amplifier is driven to open the gate depends on the burst length. However, in the present invention, a plurality of column gates are opened at a time to read data in parallel, and output data selection based on the burst length is performed by the conversion unit 29, so that the sense amplifier is driven only for a fixed period. You just have to. As a result, the period of the second stage sense amplifier operation can be made constant regardless of the burst length.
In addition, since the period of the second stage sense amplifier operation is constant, it is not necessary for the user to input a precharge command from the outside, and the internal precharge signal PRE generated automatically at an optimal timing. It becomes possible to perform self-precharge. This internal precharge signal is obtained by delaying RASZ, which is an internal RAS signal, for a predetermined time regardless of the burst length or the like. When the user arbitrarily sets the precharge timing from the outside, this optionality can be a factor that disturbs the pipeline operation. In the present invention, this factor can be eliminated. Furthermore, immediately after the data is read from the sense amplifier by the column line selection signal CL, it becomes possible to execute precharge at an optimal timing, and data is read in a high-speed cycle close to the limit of the sense amplifier's operating capability. Can be realized.
FIG. 4 is a diagram schematically showing the operation of the DRAM according to the present invention. A row pipeline operation in the DRAM according to the present invention will be described in more detail with reference to FIG.
As shown in FIG. 4, in the DRAM according to the present invention, when a command (activation command ACT) is input, first, in the first cycle, peripherals related to row access other than command decoding and sense amplifier operation are performed. The operation of the circuit is performed. Thereafter, in the second cycle, a cycle related to the sense amplifier operation is performed. That is, in this second cycle, cell data is output to the bit line by word line selection, bit line data is amplified by a sense amplifier, bit line data is read to the data bus by column line selection, bit line precharge, etc. A reset operation is performed. Next, a data output operation is performed in the third cycle. That is, in this third cycle, parallel data is converted into serial data, and data is output from the output buffer. In the DRAM of the present invention, as shown in FIG. 4, these three cycles overlap each other and operate in a pipeline manner.
In the conventional configuration, the column line selection signal CL is raised once or a plurality of times with the selected burst length to read data, and after this data read, a reset operation is performed by inputting a precharge command. In this conventional configuration, the burst length is selectable by the user and is not fixed. Therefore, after the column line selection signal CL is raised once or a plurality of times to read out data, precharge is performed by a precharge command input by the user. There is a need. Therefore, the activation time of the sense amplifier changes according to the burst length, and the period of the sense amplifier operation in FIG. 4 expands and contracts. Therefore, the activation command ACT is input at the timing of starting the sense amplifier operation. Pipeline operation is extremely difficult to achieve. Even if such a pipeline operation can be realized, the control system is expected to be extremely complicated.
On the other hand, in the DRAM according to the present invention, a plurality of column lines are selected at a time regardless of the burst length to read parallel data, and the parallel data is selected according to the burst length and converted into serial data. With the output configuration, the length of the second cycle in which the sense amplifier operates is fixed. Therefore, it is possible to execute a reset operation by self-precharge at a fixed timing, and there is no need to input a precharge command from the outside as in the prior art. As described above, since it is not necessary to input the precharge command, it is possible to speed up the input of the activation command ACT, and the length of the sense amplifier operation cycle is constant. It is possible to easily control the pipeline operation in which the respective cycles are overlapped.
In such a pipeline operation, as can be seen from FIG. 4, the time tRC, which is an interval for inputting a command (activation command ACT), is made extremely short compared to the conventional configuration in which the pipeline operation is not performed. Is possible. The time tRC is determined by the time of the sense amplifier operation cycle as shown in FIG. This is because the time required for the second cycle is the longest among the first, second, and third cycles in FIG. Therefore, when the longest second cycle is continuously repeated without interruption as shown in FIG. 4, the data read rate becomes the highest and the time of the second cycle corresponds to tRC. FIGS. 5A to 5C are diagrams showing the relationship between the sense amplifier operation cycle and the activation command ACT input interval tRC.
As shown in FIG. 5A, an interval for inputting the activation command ACT is defined as a time tRC. As shown in FIG. 5B, the sense amplifier cycle (sense amplifier operation cycle) can be divided into a word line selection cycle, a sense amplifier drive cycle, and a reset cycle. As shown in FIG. 5C, in the word line selection cycle, the word line selection signal SW becomes HIGH, and cell data appears on the bit lines BL and / BL. In the sense amplifier drive cycle, the sense amplifier drive signals SA1 and SA2 are activated to drive the sense amplifier, thereby amplifying the data on the bit lines BL and / BL. Further, in the sense amplifier driving cycle, after the data of the bit lines BL and / BL are sufficiently amplified, the column line selection signal CL is set to HIGH, and the data of the bit lines BL and / BL are read to the data bus. Next, in the reset cycle, the word line selection signal SW is reset and the precharge signal PR is set to HIGH to precharge the bit lines BL and / BL. At this time, the sense amplifier drive signals SA1 and SA2 are inactive.
As can be seen from FIGS. 5A and 5B, when the activation command ACT is continuously input at time tRC intervals, the sense amplifier cycle is continuously repeated without interruption. Therefore, the activation command ACT input interval tRC is determined according to the length of the sense amplifier cycle including the word line selection cycle, the sense amplifier drive cycle, and the reset cycle. That is, in the configuration of the present invention, if each operation of the sense amplifier cycle is made faster and the time of the sense amplifier cycle is shortened, the time tRC is also shortened and the data read speed of the DRAM can be improved. Become.
[0003]
In FIG. 4, the third cycle (data output) starts after the second cycle (sense amplifier operation) ends, but in more detail, FIG. ) As shown in (c), the third cycle can be started after raising the column selection signal CL to H. In this case, the data output operation and the bit line precharge operation are performed in parallel.
FIG. 6 is a timing chart for explaining an increase in row access speed by self-precharge. As described above, in the present invention, high-speed row access operation can be realized by performing self-precharge at an optimal timing by the internal precharge signal PRE. The timing of the row access operation by the DRAM 10 of the present invention will be described below with reference to FIGS.
When the activation command ACT is input, the RAS generation unit 13 generates a signal RASZ. The signal RASZ is supplied to the control unit 15, and the control unit 15 controls the word decoder 18, the BLT decoder 19, the SA generation unit 20, and the 1/4 decoder 21, and the word line selection signals MW and SW, the bit line transfer signal. BLT and sense amplifier drive signals SA1 and SA2 are generated at an appropriate timing. As a result, data in the memory cell 501 (see FIG. 1) is read to the sense amplifier 520. This corresponds to the fact that the data appears on the bit line BL and the amplitude is amplified thereafter in FIG. The signal RASZ is also supplied to the PRE generation unit 14. The PRE generation unit 14 generates the internal precharge signal PRE after a predetermined time has elapsed after receiving the signal RASZ.
In response to the input of the read command RD, the CAS generation unit 22, the control unit 23, the predecoder 24, and the column decoder 25 operate. By this operation, the column line selection signal CL of the column selected by the column address becomes HIGH, and the data of the sense amplifier 520 (see FIG. 1) is transferred to the global data bus GDB (FIG. 3) via the data buses DB and / DB. Read out.
A read buffer 28 reads and amplifies data on the global data bus GDB. The data held in the read buffer 28 is parallel data, and the data conversion unit 29 converts the data into serial data by performing parallel / serial conversion. This serial data is output from the output buffer 30 to the outside of the DRAM 10.
As shown in FIG. 6, the internally generated precharge signal PRE resets the bit line transfer signal BLT and the word line selection signals MW and SW in the same manner as when the precharge signal is input from the outside. At the same time, the bit lines BL and / BL are precharged to a predetermined potential. The precharge operation by the precharge signal PRE is immediately after data is read from the sense amplifier 520 by the column line selection signal CL as shown in FIG. On the other hand, at the conventional timing shown in FIG. 2, after the data is read by the column line selection signal CL, the precharge command is input from the outside and the precharge operation is executed. Exists.
In the present invention, the precharge signal PRE is internally generated based on the timing of the activation command ACT, so that the precharge operation can be executed immediately after the data reading by the column line selection signal CL. In the present invention, the precharge signal PRE can be easily generated by making the activation time of the sense amplifier constant regardless of the burst length. That is, it can be obtained by delaying the internal RAS signal (RASZ) for a fixed time. This fixed time is the time required to select and start a word line in response to the internal RAS signal, the time required to sufficiently amplify the bit line potential by the sense amplifier, and the bit line opened to the bit line. It may be determined in consideration of the time until the data that has appeared is read out to the data bus. Therefore, when it is necessary to read data of different row addresses, it is possible to greatly shorten the time required to read data of a new row address.
Even after the data is read by the column line selection signal CL, if the sub word line is closed before the data amplification of the bit lines BL and / BL by the sense amplifier is completed, the data of the sense amplifier is stored in the memory cell. Data will be destroyed without being stored in. Therefore, it goes without saying that the precharge operation needs to be performed after the data amplification by the sense amplifier is completed, as in the case of a normal DRAM. Therefore, in the present invention, the period required for the sense amplifier cycle before executing the reset cycle depends on the drive capability of the sense amplifier.
[0004]
In FIG. 6, the active command ACT and the read command RD are fetched in synchronization with two successive clocks. As a result, the column address fetched simultaneously with the read command can be fetched at an earlier timing. This makes it possible to open the column gate at an earlier timing. In addition, a column address is required to divide the sense amplifier block, which will be described later. In the present invention, since the column address is fetched at an early timing, the selective activation operation of the sense amplifier block is started at an early time. I can do it. On the other hand, conventionally, as shown in FIG. 2, there is a certain period (21 ns in FIG. 2) from the input of the active command to the input of the read command. This is because the column gate is opened after the bit line potential is sufficiently amplified by the sense amplifier. In the present invention, such timing control is performed in the control units 15 and 23.
Furthermore, by reading data from the core circuit 26 in parallel and performing parallel-serial conversion by the conversion unit 29, it becomes possible to read data continuously as shown in FIG. In parallel / serial conversion, data selection based on burst length information is also performed.
As described above, in the DRAM 10 of the present invention, the command interval is received by receiving commands in a packet format. That is, in FIG. 6, the activation command ACT and the read command RD are input to the DRAM 10 as one packet extending over two cycles. The user does not need to worry about the input interval between the activation command ACT and the read command RD as in FIG. The input packet command is decoded by the packet command decoder 12. According to the decoding result, a RAS signal is supplied from the packet command decoder 12 to the RAS generation unit 13 and the predecoder 16, and a CAS signal is supplied from the packet command decoder 12 to the CAS generation unit 22 and the predecoder 24.
When the time interval between row accesses is shortened, as can be seen from the comparison between FIG. 2 and FIG. 6, the word line selection signal SW, the bit line transfer signal BLT, and the sense amplifier drive signals SA1 and SA2 The timing between switching is also shortened. In this case, if the signal switching is slow, it cannot be shortened sufficiently. Therefore, in the DRAM 10 of the present invention, the sense amplifier row is divided into a plurality of sense amplifier blocks, and the sense amplifier drive signals SA1 and SA2 are supplied only to the sense amplifiers of the selected sense amplifier block, and the selected sense amplifier block is provided. The word line selection signal SW and the bit line transfer signal BLT are given only to the memory block corresponding to the. As a result, the load on these signals is reduced, and the switching of signals can be made steep. These signals are driven during row access. However, in order to selectively activate the sense amplifier block, a column address is also required. However, since the column address is not input at the time of row access at the conventional timing as shown in FIG. 2, it is impossible to select only a specific column address and drive only the sense amplifier. On the other hand, in the present invention, since the activation command ACT and the read command RD are received as one packet, the column address is already specified at the time of row access. Therefore, it is possible to select a sense amplifier block corresponding to a specific column address and execute a row access operation only for the sense amplifier of the sense amplifier block.
The configuration of each part of the DRAM 10 shown in FIG. 3 will be described below. Note that description of elements that are the same as those in the prior art is omitted.
FIG. 7 is a circuit diagram showing a configuration of the PRE generation unit 14 of FIG.
The PRE generation unit 14 includes inverters 41 to 48, a NAND circuit 49, a plurality of resistors R, and a plurality of capacitors C. The inverters 41 to 44, the plurality of resistors R, and the plurality of capacitors C constitute a first delay element array (delay A). The inverters 45 to 47, the plurality of resistors R, and the plurality of capacitors C constitute a second delay element array (delayB). A signal RASZ that is a HIGH pulse is input to the first delay element array, and the signal PRE becomes HIGH after the first delay time. The delayed signal RASZ is further delayed by a second delay time by the second delay element array, and the signal PRE is set to LOW. Therefore, the rising timing of the precharge signal PRE is determined by the first delay time of the first delay element array, and the period during which the precharge signal PRE is HIGH is determined by the second delay time of the second delay element array. Is done. This first delay time is constant regardless of the burst length. As described above, in the present invention, the activation period of the sense amplifier is constant regardless of the burst length in each read cycle. For this reason, the configuration of the precharge signal PRE generation circuit is also very simple.
If the PRE generation unit 14 having the above-described configuration is used, the internal precharge signal PRE can be generated after a predetermined time has elapsed from the signal RASZ generated by the RAS generation unit 13.
FIG. 8 is a block diagram of the packet command decoder 12 of FIG.
The packet command decoder 12 of FIG. 8 includes a command latch / decoder 50, an address latch 51, inverters 52 and 53, a PMOS transistor 54, an NMOS transistor 55, a PMOS transistor 56, an NMOS transistor 57, a clock buffer 301, and inverters 302 to 305. Including. FIG. 9 is a block diagram of the command latch / decoder 50 of FIG.
As shown in FIG. 9, the command latch / decoder 50 includes four latches 58-1 to 58-4 and a command decoder 59.
FIG. 10 is a block diagram of the command decoder 59 of FIG.
A command decoder 59 shown in FIG. 10 includes a decoder unit 320 including NAND circuits 310 and 311, an inverter 312, a plurality of inverters 313, a NOR circuit 314, an inverter 315, a plurality of inverters 316, and a NOR circuit 317.
In FIG. 9, the latches 58-1 to 58-4 of the command latch / decoder 50 latch control signals / RAS, / CAS, / WE, and / CKE input in synchronization with the clock signal. An activation command ACT and a read command RD are designated by a combination of these control signals. Each of the latches 58-1 to 58-4 latches each control signal and outputs two signals of the same logic signal and an inverted logic signal. For example, for the / RAS signal, two signals rasx and rasz are output.
As shown in FIG. 10, the command decoding unit 320 of the command decoder 59 generates an appropriate combination of the same logic signal and the inverted logic signal for the control signals / RAS, / CAS, / WE, and / CKE. By supplying the input to the circuits 310 and 311, the control signal is decoded. As a decoding result, in the example of FIG. 10, the NAND circuit 310 generates an internal activation signal, and the NAND circuit 311 generates an internal read signal. In the command decode unit 320, the combination of input signals to the NAND circuits 310 and 311 depends on which combination of control signals corresponds to the internal activation signal and the internal read signal, and is a matter to be determined at the time of design. In FIG. 10, detailed connection relations are omitted.
As shown in FIG. 10, two pulse signals AC and AP having different pulse widths are generated in response to the activation command ACT. The active cycle signal AC is a signal synchronized with input signals (rasx, rasz,...), And these input signals are held for one clock cycle by latches 58-1 to 58-4 as will be described later. Signal. Therefore, the active cycle signal AC is a signal having a pulse width corresponding to one clock cycle. The active pulse signal AP rises in synchronization with the input signal, but the fall is a signal controlled by the length of the delay stage composed of the inverter 313. Similarly, two pulse signals CC and CP having different pulse widths are generated in response to the read command RD. The column access cycle signal CC is a signal having a pulse width corresponding to one clock cycle, and the column access pulse signal CP rises in synchronization with the input signal, but the fall is controlled by the length of the delay stage composed of the inverter 316. Signal.
FIG. 11 is a timing chart showing the operation of the command packet decoder 12 of FIG. The operation of the command packet decoder 12 will be described with reference to FIGS.
Since the activation command ACT and the read command RD are input as packets in successive cycles, the activation command ACT is latched in the first cycle, and the read command RD is latched in the second cycle. These latched commands are decoded and interpreted by the command decoder 50 as described above. In response to the activation command ACT, the command decoder 50 generates the active pulse signal AP and the active cycle signal AC at a predetermined timing as described above. The active pulse signal AP is supplied to the RAS generation unit 13, and the active cycle signal AC opens the gate composed of the PMOS transistor 54 and the NMOS transistor 55.
Further, the command decoder 59 generates the column access pulse signal CP and the column access cycle signal CC at a predetermined timing as described above in response to the read command RD. The column access pulse signal CP is supplied to the CAS generation unit 22, and the column access cycle signal CC opens the gate composed of the PMOS transistor 56 and the NMOS transistor 57.
The address latch 51 latches the address signal in synchronization with the clock signal. The latched row address is supplied to the row predecoder 16 at the timing indicated by the active cycle signal AC. At this time, a latch composed of the inverters 302 and 303 holds this row address. The latched column address is supplied to the column predecoder 24 at the timing indicated by the column access cycle signal CC. At this time, a latch composed of the inverters 304 and 305 holds the column address.
When the packet command decoder 12 having the above-described configuration is used, the activation command ACT and the read command RD are input as packets in successive cycles, and the RAS signal and the CAS signal can be distributed to the respective paths. .
FIG. 12A is a configuration diagram of a latch used in each of the latches 58-1 to 58-4 in FIG. FIG. 12B is a timing chart showing the operation of the latch of FIG.
The latch in FIG. 12A includes PMOS transistors 321 to 324, NMOS transistors 325 to 331, inverters 332 and 333, PMOS transistor 334, NMOS transistor 335, PMOS transistor 336, NMOS transistor 337, and inverters 338 to 340. The PMOS transistor 334, the NMOS transistor 335, the PMOS transistor 336, and the NMOS transistor 337 constitute a tristate buffer 350. Inverters 338 and 339 constitute an output latch 351.
The input signal inz is captured in synchronization with the rising edge of the clock signal clkz. The tristate buffer 350 is controlled according to the value of the input signal inz taken in, and output signals outz and outx are output. When the clock signal clkz falls, the state of the tristate buffer 350 becomes the Hi-Z output state. At this time, the data of the input signal inz fetched in synchronization with rising is held by the output latch 351. The data in the output latch 351 is held until new data is captured at the next rising edge of the clock signal inz.
In this way, the latch of FIG. 12A can output the output signals outz and outx for one clock cycle.
FIG. 13 is a timing chart showing a column access operation in the DRAM of FIG.
In synchronization with the external clock signal, for example, a control signal (READ) indicating three read modes is captured. As described with reference to FIGS. 8 to 10, the control signal is decoded by the packet command decoder 12 to generate the column access pulse signal CP. The column access pulse signal CP is supplied to the CAS generation unit 22 shown in FIG.
The CAS generation unit 22 generates a read mode pulse signal readpz and a column address fetch signal caez. The read mode pulse signal readpz is supplied to the control unit 23 in FIG. 3, and the column address fetch signal caez is supplied to the predecoder 24 in FIG.
The control unit 23 that has received the read mode pulse signal readpz generates a column gate selection pulse signal cspz that determines the generation timing and pulse width of the column line selection signal CL. Further, the predecoder 24 that has received the column address fetch signal caez predecodes the column address to generate a column address predecode signal. FIG. 13 shows that 3-bit column address predecode signals 1 to 3 are output from the predecoder 24.
The column decoder 25 in FIG. 3 receives the column address predecode signal and the column gate selection pulse signal cspz, and the column address selection pulse signal cspz designates the column gate of the column address designated by the column address predecode signal. A column gate line selection signal CL with timing and pulse width is supplied.
[0005]
In FIG. 13, a broken line portion of the column line selection signal indicates another column selection different from the column selection line selected last time by a predecode signal (LLL) different from the previous column address predecode signal (HHH). Indicates that a line has been selected. In the figure, the readz signal is a signal used in the selector control unit of FIG. 15 to be described later, and is generated by the control unit 23 of FIG. 3, and the column access pulse signal CP is output in response to the rising edge of the clock. If the pulse signal CP is not output in response to the rising edge of the clock, the signal changes to L.
In this way, data can be read from the core circuit 26 to the read buffer 28.
[0006]
FIG. 14 shows a state in which data is simultaneously read from a plurality of sense amplifiers in the core circuit 26 and the parallel data is transferred to the conversion unit 29 via the global data bus (GDB) and the read buffer 28. It is a schematic diagram. This example shows a state in which 4-bit parallel data is transferred.
[0007]
In the figure, SA0 (1N) to SA3 (4N) indicate 16 sense amplifiers. By selecting one sub word line SW (not shown), the data of the memory cell corresponding to the selected sub word line is transferred to each of these 16 sense amplifiers and amplified.
[0008]
In this state, the column decoder 25 sets the column selection line cl0z to H (the remaining cl1z, cl2z, and cl3z are L). Then, among the 16 sense amplifiers, the column gates corresponding to SA0 (1N) to SA0 (4N) are simultaneously opened, and the read data amplified by SA0 (1N) to SA0 (4N) is parallel to four globals. The data is transferred to the data buses GDB (1N) to GDB (4N).
[0009]
It should be noted here that, regardless of the value of the burst length stored in the mode register 31 (1, 2, 4,...), Four column gates are opened at the same time. Is output.
[0010]
These 4-bit parallel data are taken into the read buffer 28 activated in response to the signal RB, amplified, and further sent to the conversion unit 29.
[0011]
The conversion unit 29 performs parallel / serial conversion on the parallel data supplied from the read buffer 28.
FIG. 15 is a configuration diagram showing the configuration of the conversion unit 29.
15 includes a switch circuit 60, a register circuit 61 including registers 361 to 364, a selector circuit 62 including NAND circuits 369 to 372, an address combination circuit 63 including NAND circuits 365 to 368, a selector control unit 64, It includes a timing circuit 65 including a NOR circuit 373 and an inverter 374, a NAND circuit 375, an inverter 376, a NAND circuit 377, a NOR circuit 378, and level shifters 66 and 67. The level shifters 66 and 67 are connected to the output buffer 30 (see FIG. 3) including a PMOS transistor 379 and an NMOS transistor 380.
When a data enable signal (for example, a signal obtained by delaying the cspz signal for a predetermined time) from the control unit 23 in FIG. 3 is input to the switch circuit 60, the parallel data d0 to d3 from the read buffer 28 in FIG. 361 to 364 (register circuit 61) are read. The parallel data d0 to d3 held by the register circuit 61 is supplied to the selector circuit 62. The selector circuit 62 converts the parallel data d0 to d3 into serial data and outputs it by opening the NAND circuits 369 to 372 operating as gates at the timing controlled by the selector control unit 64. The output serial data is supplied to the level shifters 66 and 67 at the timing generated by the timing circuit 65. The level shifters 66 and 67 shift the voltage level of the data, and supply the data after the voltage shift to the output buffer 30.
[0012]
The level shifter circuits 66 and 67 are configured as shown in FIG. 16, for example. In other words, PMOS 661 and 662 that are cross-connected to each other and inputs from the NAND circuit 377 or NOR circuit 378, an NMOS 663 that is connected in series to the PMOS 661, and an input of an inverted phase from the PMOS 663 via the inverter 665, An NMOS 664 is connected in series to the PMOS 662.
In this way, the parallel data from the read buffer 28 is converted into serial data by the conversion unit 29 and output from the output buffer 30 as the data signal DQ. Note that at the timing when the serial data is not supplied from the selector circuit 62, the output of the timing circuit 65 becomes LOW, and the outputs of the NAND circuit 377 and the NOR circuit 378 become HIGH and LOW, respectively. Therefore, at the timing when serial data is not output, the output of the output buffer 30 is in a floating state (high impedance state). FIG. 17 is a configuration diagram showing the configuration of the selector control unit 64.
The selector control unit 64 in FIG. 17 includes shift registers 381 to 384, a selector switch circuit 385, NAND circuits 386 to 388, and an inverter 389. The selector switch circuit 385 includes switches s1 to s8.
The internal clock signal supplied from the input buffer 11 in FIG. 3 is supplied to the shift registers 381 to 384. The shift registers 381 to 384 further receive the read signal readz at the timing shown in FIG. 13 from the control unit 23 of FIG. Each of the four shift registers 381 to 384 is a 1-bit shift register, and constitutes a 4-bit shift register as a whole. Each of the shift registers 381 to 384 performs up / down once every four periods in synchronization with the internal clock signal while the read signal readz is input.
The selector switch circuit 385 determines which of the switches s1 to s8 is to be turned on based on the burst length and the column address combination signal from the address combination circuit 63. The column address combination signal determines which data among the parallel data d0 to d3 is to be output. Further, the burst length is controlled so that the output DQ becomes high impedance by masking the bits that are not output in the serially output data. This burst length is stored in the mode register 31 of FIG. 3, and there are 1, 2, 4, 8 for example.
As shown in FIG. 17, the switches s1 to s8 are divided into four groups 1N to 4N. The group 1N includes switches s1 to s4. Group 2N includes switches s5 and s6. Group 3N includes switch s7. The group 4N includes a switch s8. The activation / deactivation of each group of switches is controlled by the burst length. For example, when the burst length is 1 (bl1z is selected), only the group 1N is activated and the other groups are deactivated. When the burst length is 2 (bl2z is selected), the groups 1N and 2N are activated and the other groups are deactivated.
Further, the column address signals caa0x / z and caa1x / z (x and z are mutually inverted logic) are combined by NAND circuits 365 to 368 and supplied to the selector switch circuit 385 as column address combination signals as shown in FIG. Is done. Which of the parallel data d0 to d3 is selected is determined by the combination of the column address signals caa0x / z and caa1x / z.
[0013]
FIGS. 18A to 18C are diagrams showing how the selector circuit 62 and the selector switch 385 are selected when the burst length (BL) is 1, 2, and 4, respectively.
When the burst length is 1, as shown in FIG. 18A, the switches s1 to s4 of the group 1N are in the active state, and the switches of the other groups 2N to 4N are inactive. When the burst length is 1, one of the switches s1 to s4 is selected so that one of the NAND circuits 369 to 372 is opened by a combination of the column address signals caa0x / z and caa1x / z. For example, by setting caa0x and caa1x to HIGH, for example, the switch s1 can be selected, and thereby the data d0 can be selected. For example, by setting caa0z and caa1z to HIGH, for example, the switch s4 can be selected, and thereby the data d3 can be selected. As described above, when the burst length is 1, it is possible to determine which data among the data d0 to d3 is output by the combination of the column address signals.
When the burst length is 2, as shown in FIG. 18B, the groups 1N and 2N are in the active state, and the other groups 3N and 4N are inactive. When the burst length is 2, the column address signal caa1x / z is ignored (both are fixed to H), and depending on the column address signal caa0x / z, the NAND circuit 369 and 370 or the NAND circuit 371 and 372 is set. The switch is selected so that one of the pairs is opened. For example, the switch s1 and the switch s5 are selected by setting caa0x to HIGH. As a result, the data d0 and d1 can be output as serial data in synchronization with the internal clock. For example, by setting caa0z to HIGH, for example, the switch s3 and the switch s6 are selected. As a result, the data d2 and d3 can be output as serial data in synchronization with the internal clock.
When the burst length is 4, as shown in FIG. 18C, all the groups 1N to 4N are in the active state. In this case, the switches s1, s5, s7, and s8 are selected regardless of the column address signal. As a result, the data d0 to d3 can be output as serial data in synchronization with the internal clock.
By using the conversion unit 29 configured as described above, the parallel data supplied from the read buffer 28 in FIG. 3 can be converted into serial data and supplied to the output buffer 30. Further, at the same time as converting parallel data into serial data, a necessary number of data can be selected using a part of the burst length signal and the column address signal.
FIG. 19 is a circuit diagram of a word line selection circuit including the word decoder 18 and the ¼ decoder 21 of FIG.
The word line selection circuit in FIG. 19 includes a main 1/4 decoder 70, a sub 1/4 decoder 80, a main word decoder 90, and a sub word decoder 100. The main 1/4 decoder 70 and the sub 1/4 decoder 80 correspond to the 1/4 decoder 21 in FIG. 3, and the main word decoder 90 and the sub word decoder 100 correspond to the word decoder 18 in FIG.
The main 1/4 decoder 70 includes PMOS transistors 71 to 73, NMOS transistors 74 to 76, an inverter 77, and a NAND circuit 78. The NAND circuit 78 is supplied with a block selection signal BS from the BLT decoder 19 and a main 1/4 decoder selection signal QS from the predecoder 16. When the main 1/4 decoder 70 of the block is selected, the NAND circuit 78 outputs LOW. With this LOW output, the main 1/4 decoder 70 outputs HIGH as shown in FIG.
The sub 1/4 decoder 80 includes PMOS transistors 81 to 83 and NMOS transistors 84 to 86. The output from the main 1/4 decoder 70 is input to the gates of the PMOS transistor 81 and the NMOS transistor 85. A column block selection signal CS is supplied to the gate of the NMOS transistor 84. The column block selection signal CS is a signal for selecting a sub word selection line corresponding to the selected sense amplifier block. When the column block selection signal CS and the output of the main 1/4 decoder 70 become HIGH, the sub 1/4 decoder 80 outputs HIGH and LOW as shown in FIG.
The main word decoder 90 includes PMOS transistors 91 to 93, NMOS transistors 94 to 96, an inverter 97, and a NAND circuit 98. The NAND circuit 98 is supplied with a block selection signal BS from the BLT decoder 19 and a main word decoder selection signal MWS from the predecoder 16. When the main word decoder 90 of the block is selected, the NAND circuit 98 outputs LOW. With this LOW output, the main word decoder 90 outputs HIGH to the main word line MW as shown in FIG.
The sub word decoder 100 includes a PMOS transistor 101 and NMOS transistors 102 and 103. When receiving the output of the level shown in FIG. 19 from the main word decoder 90 and the sub 1/4 decoder 80, the sub word decoder 100 outputs HIGH as the sub word selection line signal SW. A specific word line is selected by the sub-word selection line signal SW at the HIGH level.
In FIG. 19, since a column block selection signal CS is supplied to the sub 1/4 decoder 80, a specific sense amplifier block is selected from a plurality of sense amplifier blocks, and a word line is connected to the sense amplifier block. Data can be read out to the bit line by selection.
FIG. 20 shows a bit line transfer signal generation circuit including the BLT decoder 19 of FIG.
The bit line transfer signal generation circuit of FIG. 20 includes a main BLT generation circuit 110 and a sub-BLT generation circuit 120.
The main BLT generation circuit 110 includes PMOS transistors 111 to 113, NMOS transistors 114 to 116, inverters 117 and 118, and a NAND circuit 119. The NAND circuit 119 is supplied with the main BLT generation circuit selection signal BLTS from the predecoder 16 of FIG. When the main BLT generation circuit 110 is selected, the NAND circuit 119 outputs LOW. With this LOW output, the main BLT generation circuit 110 outputs HIGH as shown in FIG. Further, a block selection signal BS is output from the inverter 118, and this signal BS is supplied to the word decoder 18, the SA generation unit 20, and the ¼ decoder 21.
The sub-BLT generation circuit 120 includes PMOS transistors 121 to 124 and NMOS transistors 125 to 128. Outputs from the main BLT generation circuit 110 are input to the gates of the PMOS transistor 121 and the NMOS transistor 126. A column block selection signal CS is supplied to the gate of the NMOS transistor 125. This column block selection signal CS is a signal for selecting a bit line transfer gate corresponding to the selected sense amplifier block. When the column block selection signal CS becomes HIGH and the output of the main BLT generation circuit 110 becomes HIGH, the bit line transfer signal BLT that is the output of the sub BLT generation circuit 120 is driven.
In FIG. 20, since a column block selection signal CS is supplied to the sub-BLT generation circuit 120, a specific sense amplifier block is selected from a plurality of sense amplifier blocks, and a bit line is connected to the sense amplifier block. It can be connected.
FIG. 21 shows a sense amplifier drive signal generation circuit including the SA generation unit 20 of FIG.
The sense amplifier drive signal generation circuit of FIG. 21 includes a main SA generation circuit 130 and a sub SA generation circuit 140.
Main SA generation circuit 130 includes a NAND circuit 131 and an inverter 132. The NAND circuit 131 is supplied with the block selection signal BS from the BLT decoder 19 in FIG. 3 and the main sense amplifier latch signal SA from the predecoder 16 in FIG. When the block is selected, the main SA generation circuit 130 outputs a main sense amplifier latch signal SA ′.
The sub SA generation circuit 140 includes PMOS transistors 141 to 143 and NMOS transistors 144 to 146. The main sense amplifier latch signal SA ′ is input from the main SA generation circuit 130 to the gates of the PMOS transistor 141 and the NMOS transistor 144. A column block selection signal CS is supplied to the gate of the NMOS transistor 144. This column block selection signal CS is a signal for selecting a sense amplifier block. When the column block selection signal CS becomes HIGH, the sense amplifier drive signals SA1 and SA2, which are the outputs of the sub SA generation circuit 140, become LOW and HIGH by the main sense amplifier latch signal SA.
In FIG. 21, since the column block selection signal CS is supplied to the sub SA generation circuit 140, a specific sense amplifier block is selected from a plurality of sense amplifier blocks, and the sense amplifier of the sense amplifier block is driven. It becomes possible.
As described above, the sense amplifier row is divided into a plurality of sense amplifier blocks, and the word line selection signal SW, the bit line transfer signal BLT, and the sense amplifier drive signals SA1 and SA2 are supplied only to the sense amplifiers of the selected sense amplifier block. To drive. As a result, the load on these signals is reduced, and the switching of signals can be made steep.
If the sense amplifier row is divided into a plurality of sense amplifier blocks and controlled for each sense amplifier block in this way, the operation speed can be increased. However, in this case, since each control circuit is required for each sense amplifier block, the chip area is increased. Therefore, in the bit line transfer signal generation circuit, it is conceivable to arrange one sub-BLT generation circuit across a plurality (about 2 to 3) of sense amplifier blocks.
FIG. 22 shows an arrangement in which sub-BLT generation circuits are provided for a plurality of sense amplifier blocks. In FIG. 22, a signal output from the same main BLT generation circuit 110 as in FIG. 20 is supplied to a sub-BLT generation circuit 120A provided for each of the two sense amplifier blocks 164. Here, CS1 to CS8 are column block selection signals for selecting the eight sense amplifier blocks 164 shown in FIG. 22, and are generated by the predecoder 24 of FIG. Each sub-BLT generation circuit 120A further receives two adjacent column block selection signals CSn and CSn + 1 (n: odd number). When any one of the column block selection signals CSn and CSn + 1 becomes HIGH and the signal from the main BLT generation circuit 110 becomes HIGH, the bit line transfer signal BLT that is the output of the sub BLT generation circuit 120A is driven. .
FIG. 23 is a circuit diagram showing a circuit configuration of sub BLT generation circuit 120A.
The sub-BLT generation circuit 120A includes PMOS transistors 121 to 124 and NMOS transistors 125 to 129. Outputs from the main BLT generation circuit 110 are input to the gates of the PMOS transistor 121 and the NMOS transistor 127. A column block selection signal CSn is supplied to the gate of the NMOS transistor 125, and a column block selection signal CSn + 1 is supplied to the gate of the NMOS transistor 126. When the column block selection signals CSn and CSn + 1 become HIGH and the output of the main BLT generation circuit 110 becomes HIGH, the bit line transfer signal BLT which is the output of the sub BLT generation circuit 120A is driven.
Thus, by providing the control circuit (sub-BLT generation circuit 120A) for each of a plurality (two in the example of FIGS. 22 and 23) of sense amplifier blocks, an increase in circuit area can be suppressed. Similarly, a control circuit for resetting the bit line can be provided for each of the plurality of sense amplifier blocks.
FIG. 24 is a diagram showing a chip configuration of the DRAM 10 according to the present invention. As shown in FIG. 24, the DRAM 10 according to the present invention includes, for example, eight cell array blocks (banks) 150-1 to 150-8.
FIG. 25 is a diagram showing a configuration of the cell array block of FIG. FIG. 25 shows a cell array block 150 which is an arbitrary one of the eight cell array blocks (banks) 150-1 to 150-8 shown in FIG.
The cell array block 150 includes a main word decoder area 160 corresponding to the main word decoder 90 of FIG. 19, an m-s cross area 161, and eight sub-blocks 162. Each sub-block 162 includes a sub-word decoder region 163 corresponding to the sub-word decoder 100 in FIG. 19, a sense amplifier block 164 including a plurality of sense amplifiers corresponding to the sense amplifier 520 in FIG. 1, an ss cross region 165, and a memory cell. , A memory cell region 166 including a sub word selection line, a bit line, and the like.
The ms cross region 161 includes the main 1/4 decoder 70 of FIG. 19, the main BLT generation circuit 110 of FIG. 20, and the main SA generation circuit 130 of FIG. The ss cross region 165 includes the sub 1/4 decoder 80 of FIG. 19, the sub BLT generation circuit 120 of FIG. 20, and the sub SA generation circuit 140 of FIG.
[0014]
As shown in FIG. 1, a sense amplifier drive transistor that operates in response to the sense amplifier drive signals SA1 and SA2 and activates the sense amplifier 520, including a PMOS transistor 513 and an NMOS transistor 512, is connected to each sense amplifier block. A pair of common sense amplifiers may be provided for the plurality of sense amplifiers in 164, and the common sense amplifier driving transistors may be provided in the ss cross region 165.
[0015]
On the other hand, when the load for driving a plurality of sense amplifiers in each sense amplifier block is very large, the size of the common sense amplifier driving transistor becomes large, and other circuits exist in the ss cross region 165. It may not be able to enter. In such a case, a sense amplifier drive transistor may be provided for each individual sense amplifier, and the drive transistor may be laid out in the sense amplifier block 164.
With the layout as described above, the sense amplifier row is divided into a plurality of sense amplifier blocks 164, and the word line selection signal SW, the bit line transfer signal BLT, and the sense amplifier drive are only applied to the sense amplifier of the selected sense amplifier block 164. A configuration for driving the signals SA1 and SA2 can be realized. As a result, the load of these signals can be reduced, and the switching of signals can be made steep.
FIG. 26 is a diagram for explaining data reading / data writing by the direct sense amplifier method.
In FIG. 1, a transfer column gate system using NMOS transistors 510 and 511 as column gates is adopted in data reading / data writing. In the transfer column gate system as shown in FIG. 1, when the data on the bit lines BL and / BL are read to the data buses DB and / DB, the bit lines BL and / BL are loaded by the load on the data buses DB and / DB. The voltage level of fluctuates. If the word line selection signal SW is set to LOW and the NMOS transistor 502 serving as the cell gate is closed in a state where the voltage level has changed, the data in the memory cell 501 may change at the changed voltage level. Therefore, it is necessary to set the word line selection signal SW to LOW after waiting for the voltage levels of the bit lines BL and / BL to return to the stable state.
Therefore, when the transfer column gate method is adopted, it is necessary to execute the precharge after the voltage levels of the bit lines BL and / BL return to the stable state, and the self-precharge timing according to the present invention is made much earlier. I can't. Therefore, if the direct sense amplifier system as shown in FIG. 1 is used, the operation speed can be further improved by advancing the self-precharge timing.
In the direct sense amplifier system of FIG. 26, a data read circuit 200 and a data write circuit 210 are used instead of the column gates 510 and 511 of FIG. The data read circuit 200 includes NMOS transistors 201 to 204, and the data write circuit 210 includes NMOS transistors 211 to 214.
At the time of data reading, after the data is read to the bit lines BL and / BL and the data is stabilized, the column line selection signal CL becomes HIGH, and the NMOS transistors 203 and 204 of the data reading circuit 200 are turned on. At this time, the NMOS transistors 201 and 202 of the data read circuit 200 are turned on or off according to the data of the bit lines BL and / BL, so that the data appears on the data buses DB and / DB. At the time of data reading, the write block selection signal WB is LOW, and the NMOS transistors 211 and 214 of the data writing circuit 210 are off.
At the time of data writing, the write block selection signal WB is set to HIGH, and the NMOS transistors 211 and 214 of the data writing circuit 210 are made conductive. Next, the write data reaches the data buses DB and / DB, the column line selection signal CL becomes HIGH, and the NMOS transistors 212 and 213 of the data write circuit 210 are turned on. As a result, the data on the data buses DB and / DB are written to the bit lines BL and / BL. At this time, the NMOS transistors 203 and 204 of the data read circuit 200 are turned on. However, since the drive capability of the write signal is superior, data can be written without any problem.
As described above, in the direct sense amplifier system, when reading data, the bit lines BL and / BL are not directly connected to the data buses DB and / DB, but the voltage levels of the bit lines BL and / BL. By driving the NMOS transistors 201 and 202, data is transferred to the data buses DB and / DB. Therefore, the voltage levels of the bit lines BL and / BL do not fluctuate due to the load on the data buses DB and / DB.
27A and 27B show the timings of the word line selection signal SW, the column line selection signal CL, and the signal of the bit lines BL and / BL in the case of the transfer column gate method and the direct sense amplifier method. It is a timing chart shown regarding.
FIG. 27A shows the case of the transfer column gate system, and when the column line selection signal CL becomes HIGH, the voltage levels of the bit lines BL and / BL change. The word line selection signal SW is reset after waiting for this voltage fluctuation to disappear. On the other hand, in the case of the direct sense amplifier system shown in FIG. 27B, even if the column line selection signal CL becomes HIGH and data is read, the voltage levels of the bit lines BL and / BL do not change. Therefore, immediately after reading the data on the bit lines BL and / BL, it is possible to reset the word line selection signal SW by self-precharging and precharge the bit lines BL and / BL.
If the direct sense amplifier system is used in this manner, the data read speed can be further improved by advancing the self-precharge timing according to the present invention.
FIGS. 28A and 28B are diagrams for explaining problems that occur when the clock frequency is lowered.
The column line selection signal CL reads a column address input simultaneously with the read command RD, and becomes HIGH when a designated column line is selected after a predetermined time. That is, the timing when the column line selection signal CL rises is after a predetermined time has elapsed from the input timing of the read command RD. Therefore, as shown in FIG. 4, in the configuration in which the activation command ACT is input and the read command RD is input in the next cycle, the timing at which the column line selection signal CL rises is the timing at which the activation command ACT is input. Instead, it is determined at the timing when the read command RD is input.
In such a configuration, when the frequency of the clock signal becomes low, there is a problem that the time tRAC from the activation command ACT input to the data output becomes long.
FIG. 28A is a timing chart showing the operation when the clock cycle is 5 ns, for example. As shown in the figure, the column line selection signal CL becomes HIGH 12.5 ns after the read command RD is input. Since one clock is 5 ns, the time interval from when the activation command ACT is input until the column line selection signal CL becomes HIGH is 17.5 ns. Assuming that it takes 12.5 ns from the activation of the column line selection signal CL to HIGH to the data output, the time tRAC from the activation command ACT input to the data output becomes 30 ns.
FIG. 28B is a timing chart showing the operation when the clock cycle is 10 ns, for example. As shown in the figure, the column line selection signal CL becomes HIGH 12.5 ns after the read command RD is input. Since one clock is 10 ns, the time interval from when the activation command ACT is input until the column line selection signal CL becomes HIGH is 22.5 ns. Assuming that 17.5 ns is required from the activation of the column line selection signal CL to HIGH until the data output, the time tRAC from the activation command ACT input to the data output becomes 40 ns.
As described above, in the configuration in which the activation command ACT is input and the read command RD is input in the next cycle, the rise timing of the column line selection signal CL is determined by the read command RD input timing after the activation command ACT is input. Therefore, when the frequency of the clock signal becomes low, the time tRAC from the activation command ACT input to the data output becomes long.
In order to solve this, the activation command ACT and the read command RD may be input simultaneously.
FIG. 29 is a timing chart when the activation command ACT and the read command RD are input simultaneously.
FIG. 29 shows the operation when the clock cycle is 10 ns, and the column line selection signal CL becomes HIGH 17.5 ns after the read command RD is input. Since the activation command ACT and the read command RD are input simultaneously, the time interval from when the activation command ACT is input to when the column line selection signal CL becomes HIGH is also 17.5 ns. If it takes 12.5 ns from the activation of the ACT to the data output after the column line selection signal CL becomes HIGH, the time tRAC from the activation command ACT input to the data output becomes 30 ns, which is the same tRAC as when the clock cycle is 5 ns. . As described above, if the activation command ACT and the read command RD are input simultaneously, the same tRAC can always be guaranteed regardless of the clock frequency. Note that inputting the activation command ACT and the read command RD at the same time means inputting these commands, and also a row address and a column address at the same time. In order to execute this operation, an address input pin for row address and column address may be provided. The input address to the row address input pin is to the row address control system, and the input address to the column address input pin is It only needs to be supplied to the column address control system.
[0016]
In the above description, the activation command ACT and the read command RD are described as separate commands, and the two commands are described as being input simultaneously. However, if a command equivalent to ACT + RD is defined, One command may be input in synchronization with the rising edge of the external CLK.
FIG. 30 shows another configuration example of the DRAM according to the present invention. FIG. 30 shows a configuration when the activation command ACT and the read command RD are simultaneously input as described above. In FIG. 30, the same components as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted.
The DRAM 10A of FIG. 30 includes a separate input buffer 11A that receives a control signal, a row address signal, and a column address signal, and a command decoder 12A. Each input buffer 11A is a normal buffer that captures each signal in synchronization with the internal clock signal supplied from the input buffer 11 that receives the clock signal. The input row address is supplied to a row address predecoder 16 and the input column address is supplied to a column address predecoder 24. In this way, if the row address and column address input buffers are provided separately, and the row address is supplied to the row address control system and the column address is supplied to the column address control system, the row address and the column address can be input simultaneously. Can be realized.
Unlike the packet command decoder 12 of FIG. 3, the command decoder 12A does not need to distribute packet commands to the loadless system and the column address system. Therefore, the command decoder 12A in FIG. 30 may be a normal command decoder. In order to input the activation command ACT and the read command RD at the same time, a command for simultaneously designating the row system control operation start and the column system control operation start may be prepared as a combination of control signals.
Therefore, with respect to the other portions, a configuration in which the activation command ACT and the read command RD are simultaneously input can be realized with the same configuration as in FIG. 3 without changing the design of the control system.
[0017]
FIG. 31 is a block diagram showing another embodiment of the conversion unit 29.
[0018]
The main difference from the embodiment of the conversion unit 29 shown in FIGS. 15 and 17 is that a data bus switch 440 described later is provided as a circuit having the same function as the selector control unit of FIG. The conversion is performed in two stages of 4 bits → 2 bits → 1 bit.
[0019]
That is, the conversion unit 29 in FIG. 31 receives 4-bit parallel data from the read buffer 28 and determines whether the input-side bus line and the output-side bus line are based on the burst length signal and part of the column address information. A data bus switch 440 that changes the connection path between the first register 450 and the second register 460 sequentially connected to the output side of the data bus switch 440, and 4 bits output from the second register 460 A 4-bit → 2-bit conversion circuit 470 for converting parallel data of the configuration into parallel data of 2-bit configuration, and the parallel data of the 2-bit configuration provided on the output side of the 4-bit → 2-bit conversion circuit 470 is converted to 1-bit serial A data output timing switch 480 for converting data and a latch & level shifter circuit 430 It has been.
[0020]
Next, a more detailed configuration and operation of each component will be described.
[0021]
The data bus switch 440 includes switches sw1n, sw2n, sw3n provided corresponding to the four data bus lines d0, d1, d2, and d3, sw24 for connecting the data buses d1 and d3, d0, It comprises a switch sw14 for connecting d3, a switch sw13 for connecting d0 and d2, and a switch sw12 for connecting d0 and d1. These switches are controlled to be turned on / off corresponding to the burst length signal BL and part of the column address signal caa0z and caa1z.
[0022]
FIG. 32 is a table showing the state of each switch when the burst length BL is 1, 2, and 4, respectively. First, when the burst length BL is 4, each data on the data bus lines d0-d3 is directly transmitted to the data bus lines d0′-d3 ′. That is, in this case, regardless of the values of the column address signals caa0z and caa1z, the switches sw1n, sw2n, and sw3n are on, and the switches sw24, sw14, sw13, and sw12 are off.
[0023]
Next, when the burst length BL is 2, the data transmitted to the data bus lines d0 ′ and d1 ′ is output to the outside. Therefore, in this case, the data set of the data bus lines d0 and d1 is transmitted to the data bus lines d0 ′ and d1 ′, or the data set of the data bus lines d2 and d3 is transmitted to the data bus lines d0 ′ and d1 ′. Which data set is transmitted is determined by the logical value of the column address signal caa0z. That is, when the data set of the data bus lines d0 and d1 is transmitted to the data bus lines d0 ′ and d1 ′, the column address signal caa0z is set to the L level. Then, the switches sw1n, sw2n, and sw3n are turned on, and the switches sw24, sw14, sw13, and sw12 are turned off. On the other hand, when the data set of the data bus lines d2 and d3 is transmitted to the data bus lines d0 ′ and d1 ′, the column address signal caa0z is set to the H level. Then, the switches sw3n, sw24, and sw13 are turned on, and the switches sw1n, sw2n, sw14n, and sw12 are turned off. As a result, data on the data bus line d2 is transmitted to the data bus line d0 ′ via the switch sw13, and data on d3 is transmitted to d1 via the switch sw24. When the burst length BL is 2, the logical value of the column address signal caa1z of another bit is not used for switch selection.
[0024]
On the other hand, when the burst length BL is 1, one of the data on the data bus lines d0, d1, d2, and d3 is selected, and the selected data bit is transmitted to the data bus line d0 ′, and this data is Output to the outside. This data selection is performed based on a combination of logical values of the column address signals caa0z and caa1z. That is, when selecting data on the data bus line d0, both caa0z and caa1z are set to L level. Then, the switches sw1n, sw2n, and sw3n are turned on, and the switches sw24, sw14, sw13, and sw12 are turned off. In this case, the data on the data bus line d0 is transmitted to the data bus line d0 ′. When selecting data on the data bus line d1, caa0z is set to H level and caa1z is set to L level. Then, the switches sw2n, sw3n, and sw12 are turned on, and the switches sw1n, sw24, and sw13 are turned off. In this case, the data on the data bus line d1 is transmitted to the data bus line d0 ′ via the switch sw12. Further, when selecting data on the data bus lines d2 and d3, the switches are turned on / off based on the logic table of FIG.
[0025]
The parallel data d0′-d3 ′ output from the data bus switch 440 is transmitted to the first register 450 and further to the second register 460.
The first register 450 includes four delayed flip-flops DFF401-404, and the data fetch timing of each DFF is controlled by the first control signal po0z. Similarly, the second register 460 includes four delayed flip-flops DFF405-408, and the data fetch timing and latch timing of each DFF are controlled by the second control signal po1z.
[0026]
FIG. 33 shows the operation timing of the first and second registers 450 and 460. In the figure, d [0, 2] corresponds to data on the data bus lines d0 ′ and d2 ′, and d [1, 3] corresponds to data on the data bus lines d1 ′ and d3 ′.
[0027]
At time t1 in FIG. 33, parallel data appears on the data bus lines d0′-d3 ′. Next, when the first control signal po0z changes from H to L at time t2, the four delayed flip-flops 401-404 constituting the first register 450 latch the data on the data bus lines d0′-d3 ′, respectively. To do. Next, when the second control signal changes from L to H at time t3, the four delayed flip-flops 405 to 408 constituting the second register 460 are latched in the corresponding delayed flip-flops 401 to 404, respectively. Capture data. At time t4, when the second control signal changes from H to L, the four delayed flip-flops 405 to 408 latch the fetched data. After that, when the first control signal changes from L to H, the four delayed flip-flops 401-404 are again in a state of accepting data on the data bus lines d0′-d3 ′. Through the above operation, parallel data on the data bus lines d0′-d3 ′ is sequentially transferred to the first register 450 and the second register 460.
[0028]
The data latched in the second register 460 is then transmitted to the 4-bit → 2-bit conversion circuit 470. Here, 4-bit parallel data is converted into 2-bit parallel data. The 4-bit → 2-bit conversion circuit 470 includes a delayed flip-flop DFF 409-411 and output buffer circuits 420-423. Further, four control clock signals psc1k0z-psc1k3z are supplied to the 4-bit → 2-bit conversion circuit 470, and these control clocks output the output timing of the output buffer circuits 420-423 and the delayed flip-flops DFF409-411. The data latch timing is controlled. Further, the output line of the output buffer circuit 420 and the output line of 422 are commonly connected to the node dd0. This is a wired OR connection. When data is output from the output buffer circuit 420, the output terminal of the output buffer circuit 422 is in a high impedance state. Conversely, when data is output from the output buffer circuit 422, the output terminal of the output buffer circuit 420 is output. Is in a high impedance state. Next, 2-bit data is output from the 4-bit → 2-bit conversion circuit 470 to the nodes dd0 and dd1, and is transmitted to the data output timing switch 480. The data output timing switch 480 includes two switches swdd0 and swdd1, and the ON / OFF is controlled by output control clock signals outp0z and outp1z, respectively. This data output timing switch 480 first transfers one data bit appearing at the node dd0 to the latch & level shifter circuit 430 by closing one switch swdd0 (on), and then closing the other switch swdd1 to the node dd1. Is transmitted to the latch & level shifter circuit 430. By such an operation, the data output timing switch 480 sequentially transmits the 2-bit data appearing at the nodes dd0 and dd1 to the next latch & level shifter circuit 430 bit by bit. The latch & level shifter circuit 430 latches input data, converts the level of the input data, and transmits it to the output buffer 30 in FIG.
[0029]
FIG. 34 shows the operation timing from the 4-bit → 2-bit conversion circuit 470 to the latch & level shifter circuit 430 when the burst length BL is 4. Hereinafter, the operation of these circuits will be described in more detail with reference to FIG.
[0030]
First, as an initial state, read data is latched in the four DFFs 405 to 408 constituting the second register 460.
[0031]
Then, the four control clock signals psc1k0z-psc1k3z for controlling the operation of the 4-bit → 2-bit conversion circuit 470 sequentially output H pulses in the order of psc1k1z → psc1k2z → psc1k3z → psc1k0z, as shown in FIG. First, when psc1k1z becomes H, the output buffer circuit 420 outputs the data received from the DFF 405 to the node dd0 in response thereto, and at the same time, the DFF 409 latches the data output from the DFF 406. Next, when psc1k2 becomes H, the output buffer circuit 421 responds by outputting the data received from the DFF 409 to the node dd1, and at the same time, the DFF 410 latches the data output from the DFF 407. Such an operation is repeated, and new read data is alternately output from the 4-bit → 2-bit conversion circuit 470 to the nodes dd0 and dd1, as can be seen from the waveforms at the nodes dd0 and dd1 in FIG.
[0032]
The DFF 409-411 in the 4-bit → 2-bit conversion circuit 470 allows the next read data set to be latched in the second register 460 during the conversion operation of the 4-bit → 2-bit conversion circuit 470. It is provided to enable data to be output from the data output terminal DQ without any gap.
[0033]
The two output control clock signals outp0z and outp1z that control the operation of the data output timing switch 480 also alternately output H pulses at the timing shown in FIG. When new data appears at the node dd0, outp0z becomes H after a predetermined time and the switch swdd0 is turned on, whereby the data at the node dd0 is transferred to the latch & level shifter circuit 430. Next, when new data appears at the node dd1, outp1z becomes H after a predetermined time and the switch swdd1 is turned on, whereby the data at the node dd1 is transferred to the latch & level shifter circuit 430. By repeating such an operation, the data of the nodes dd0 and dd1 are alternately and sequentially sent to the latch & level shifter circuit 430, and 2-bit → 1-bit conversion can be performed.
[0034]
The above description of the operation is for the case where the burst length BL is 4. The tables of FIGS. 35A and 35B show the operation states of the four control clock signals psc1k0z-psc1k3z and the two output control clock signals outp0z and outp1z when the burst length is 1, 2, and 4. ing.
[0035]
When the burst length BL is 4, as described above, the four control clock signals psc1k0z-psc1k3z and the two output control clock signals outp0z and outp1z all perform a clocking operation, and the four DFFs 405 of the second register 460 are used. Convert 4-bit parallel data output from -408 into serial data.
[0036]
On the other hand, when the burst length BL is 2, two control clock signals psc1k1z and psc1k2z and two output control clock signals outp0z and outp1z among the four control clock signals perform a clocking operation. When the burst length BL is 2, as described above, read data is sent only to the nodes d0 ′ and d1 ′, and no read data is sent to the nodes d2 ′ and d3 ′. Therefore, only the control clock signal and the output control clock signal necessary for outputting the read data appearing at the nodes d0 'and d1' to the outside perform the clocking operation.
[0037]
When the burst length BL is 1, only one control clock signal psc1k1z of the four control clock signals and only one outp0z of the two output control clock signals perform the clocking operation. When the burst length BL is 1, as described above, read data is sent only to the node d0 ′, and no read data is sent to the nodes d1 ′ to d3 ′. Therefore, only the control clock signal and the output control clock signal necessary for outputting the read data appearing at the node d0 ′ to the outside perform the clocking operation.
[0038]
In the above embodiment, the 4-bit data output from the second register 460 is first converted into 2-bit data by the 4-bit → 2-bit conversion circuit 470, and then the 2-bit data is converted into the data output timing switch 480 and the latch & level shifter 430. Is converted to 1 bit. That is, parallel / serial conversion is performed in two stages.
[0039]
On the other hand, in the above embodiment, the outputs of the four output buffer circuits 420 to 423 in the 4-bit → 2-bit conversion circuit 470 may be commonly wired-ORed, and the data output timing switch 480 may be constituted by one switch. . In this case, the data output timing switch 480 has only one switch, and the configuration is simplified.
[0040]
On the other hand, when the frequency of the clock signal is increased for high-speed operation, it becomes difficult to generate one output control clock signal outp # z for one switch swdd corresponding to the higher frequency. In such a case, as shown in FIG. 31, the data output timing switch 480 is composed of two switches, and these switches are two output control clock signals outp0z having a frequency about half that of the one output control clock signal. , Outp1z may be controlled.
[0041]
FIG. 36A shows a configuration example of the delayed flip-flop DDF in FIG. FIG. 36B is a timing chart showing the operation of FIG.
[0042]
The delayed flip-flop DFF includes a transfer gate 509 including a PMOS 501 and an NMOS 502, inverters 507 and 508, and a clocked inverter 510 including PMOSs 503 and 504 and NMOSs 505 and 506.
[0043]
When the clock signal clkz corresponding to the control signals po0z, po1z, psc1k0z-psc1k3z in FIG. 31 is H, the input data in is taken into the DFF by turning on the transfer gate 509, while the clocked inverter 510 is Off state. Next, when the clock signal clkz becomes L, the transfer gate 509 is turned off, and the input data in is disconnected from the DFF. At the same time, the clocked inverter 510 is activated, and the inverter 508 and the clocked inverter 510 constitute a latch circuit, and latches the data taken in by the DFF when the clock signal clkz becomes L.
[0044]
FIG. 37A is a configuration example of the output buffers 420 to 423 in FIG. FIG. 37 (b) is a timing chart showing the operation of FIG. 37 (a).
[0045]
The output buffer circuit includes inverters 511 and 512, a NAND circuit 515, a NOR circuit 516, a buffer circuit 519 composed of a PMOS 517 and an NMOS 518, and a latch circuit 520 composed of inverters 513 and 514. When the clock signal clkz corresponding to the control signals psc1k0z-psc1k3z in FIG. 31 becomes H, the NAND circuit 515 and the NOR circuit 516 function as inverters, so that output data in phase with the input data appears at the output node out, and this output Data is held in the latch circuit 520. On the other hand, when the clock signal clkz becomes L, both the PMOS 517 and the NMOS 518 are turned off, and the output node is in a high impedance state.
[0046]
FIG. 38 shows a configuration example of the latch & level shifter circuit 403 in FIG. However, a portion 525 composed of the PMOS 547 and the NMOS 548 is an output transistor portion and corresponds to 30 in FIG.
[0047]
The latch & level shifter circuit 403 includes a level shift circuit 521 with a latch composed of PMOSs 531 and 532, NMOSs 533 and 534, inverters 543 and 544, a level shift circuit 522 having the same configuration, and an inverter composed of PMOS 535 and NMOS 536. 523 and an inverter 524 composed of a PMOS 541 and an NMOS 542. In the figure, Vccq and Vssq are power lines independent of the power lines Vii and Vss of the internal circuit, and a potential different from, for example, Vii is supplied to Vccq.
[0048]
The output lines dd0 ′ and dd1 ′ (see FIG. 31) of the data output timing switch 480 are commonly connected to the gates of the PMOSs 533 and 539, respectively. For example, when data is supplied from the output line dd0 ′, if the data on the output line dd0 ′ is H, H data is output to the data output terminal DQ, and if the data on the output line dd0 ′ is L, L data is output to the data output terminal DQ.
[0049]
As another modification, the level shift circuit 522 and the inverter 524 may be omitted, and instead, the output of the inverter 523 may be connected to the gates of the PMOS 547 and the NMOS 548 in common. However, when it is necessary to control the data output terminal DQ to the high impedance state, the configuration as shown in FIG. 38 is more suitable.
[0050]
Further, in place of connecting the gate of the NMOS 539 to the output lines dd0 ′ and dd1 ′, another set of switches swdd00 further controlled by the output control clock signals outp0z and outp1z, respectively, in addition to the data output timing switch 480 in FIG. And swdd11 may be provided, and the gate of the NMOS 539 may be connected to the node dd0 via the switch swdd00 and the node dd1 via the switch swdd11.
[0051]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
【The invention's effect】
In the present invention, when the row address input to the data output are divided into the first stage command decode and peripheral circuit operation, the second stage sense amplifier operation, and the third stage data output operation, The period of the second-stage sense amplifier operation can be made constant regardless of the burst length. That is, it is only necessary to drive the sense amplifier for a fixed period in order to open a plurality of column gates at a time and read data in parallel. As a result, the period of the second-stage sense amplifier operation can be made constant regardless of the burst length, and a low-level pipeline operation without disturbance can be executed.
[0052]
In addition, when the user arbitrarily sets the precharge timing from the outside, this arbitraryness may be a factor disturbing the pipeline operation. In the present invention, this factor is obtained by executing the reset operation by the internal precharge signal. Can be wiped out. Furthermore, immediately after data is read from the sense amplifier, precharge can be executed at an optimal timing, and data can be read in a high-speed cycle close to the limit of the sense amplifier's operating capability. .
[0053]
Accordingly, it is possible to provide a semiconductor memory device capable of high-speed data reading operation, which greatly contributes to industrial development.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example of a circuit configuration around a memory cell of a DRAM.
FIG. 2 is a timing chart for explaining a data read operation in a DRAM.
FIG. 3 is a block diagram of a DRAM according to the present invention.
FIG. 4 is a diagram schematically showing the operation of a DRAM according to the present invention.
FIGS. 5A to 5C are diagrams illustrating a relationship between a sense amplifier operation cycle and an activation command ACT input interval tRC.
6 is a timing chart for explaining an increase in row access speed by self-precharge in the DRAM of FIG. 3;
7 is a circuit diagram showing a configuration of the PRE generation unit of FIG. 3. FIG.
FIG. 8 is a configuration diagram of the packet command decoder of FIG. 3;
9 is a block diagram of the command latch / decoder of FIG. 8. FIG.
10 is a block diagram of the command decoder of FIG. 9. FIG.
FIG. 11 is a timing chart showing an operation of the command packet decoder of FIG. 8;
12A is a configuration diagram of the latch of FIG. 9, and FIG. 12B is a timing diagram illustrating an operation of the latch.
FIG. 13 is a timing chart showing a column access operation in the DRAM of FIG. 3;
FIG. 14 is a schematic diagram illustrating a state in which parallel data read from a plurality of sense amplifiers in a core circuit is transferred to a conversion unit via a global data bus and a read buffer.
15 is a configuration diagram of the conversion unit in FIG. 3;
FIG. 16 is a circuit diagram showing a configuration of a level shifter circuit;
17 is a configuration diagram showing a configuration of the selector control unit of FIG. 15;
FIGS. 18A to 18C are diagrams illustrating a selection method of a selector circuit and a selector switch when burst lengths are 1, 2, and 4;
19 is a circuit diagram of a word line selection circuit including the word decoder and the ¼ decoder of FIG. 3. FIG.
20 is a circuit diagram of a bit line transfer signal generation circuit including the BLT decoder of FIG. 3. FIG.
21 is a circuit diagram of a sense amplifier drive signal generation circuit including the SA generation unit of FIG. 3. FIG.
FIG. 22 is a diagram showing an arrangement in which a sub-BLT generation circuit is provided for a plurality of sense amplifier blocks.
23 is a circuit diagram showing a circuit configuration of a sub-BLT generation circuit of FIG.
FIG. 24 is a diagram showing a chip configuration of a DRAM according to the present invention.
25 is a diagram showing a configuration of a cell array block in FIG. 24. FIG.
FIG. 26 is a diagram for explaining data reading / data writing by a direct sense amplifier method;
FIGS. 27A and 27B show timings of the word line selection signal SW, the column line selection signal CL, and the bit lines BL and / BL in the transfer column gate method and the direct sense amplifier method, respectively. It is a timing chart shown about a case.
FIGS. 28A and 28B are diagrams for explaining problems that occur when the clock frequency is lowered. FIGS.
FIG. 29 is a timing chart when an activation command ACT and a read command RD are input simultaneously.
FIG. 30 is a diagram showing another configuration example of a DRAM according to the present invention;
FIG. 31 is a block diagram showing another embodiment of the conversion unit.
FIG. 32 is a diagram illustrating the state of each switch when the burst length BL is 1, 2, and 4 respectively.
FIG. 33 is a timing chart showing operation timings of the first and second registers.
FIG. 34 is a timing chart showing the operation timing from the 4-bit → 2-bit conversion circuit to the latch & level shifter circuit when the burst length BL is 4. FIG.
FIGS. 35A and 35B are diagrams showing the operation states of four control clock signals and two output control clock signals when the burst length is 1, 2, and 4. FIGS.
36A is a circuit diagram illustrating a configuration example of the delayed flip-flop DFF in FIG. 31, and FIG. 36B is a timing diagram illustrating the operation of FIG.
FIG. 37A is a circuit diagram illustrating a configuration example of the output buffer in FIG. 31, and FIG. 37B is a timing diagram illustrating the operation of FIG.
38 is a circuit diagram showing a configuration example of a latch & level shifter circuit shown in FIG. 31;
[Explanation of symbols]
10 DRAM
11 Input buffer
12 Packet command decoder
13 RAS generation unit
14 PRE generation unit
15 Control unit
16 Predecoder
18 word decoder
19 BLT decoder
20 SA generation unit
21 1/4 decoder
22 CAS generation unit
23 Control unit
24 Predecoder
25 Column decoder
26 Core circuit
27 RB generation unit
28 Read buffer
29 Conversion unit
30 output buffer
31 Mode register

Claims (7)

A data conversion circuit for converting parallel data of a plurality of bits read from a memory cell unit into serial data,
A selector control unit that generates a control signal based on burst length information and address information;
A selector unit that receives the plurality of bits of parallel data and serially outputs the selected bits by a plurality of gates that select and pass a predetermined number of the plurality of bits at a timing based on the control signal; The selector control unit
A plurality of shift circuits that perform a shift operation in response to a clock signal;
The receiving address information, a switch circuit for outputting the control signal in response to a plurality of output clock signals from said plurality of shift circuits,
The switch circuit includes a plurality of switches that receive the plurality of output clock signals, and the plurality of switches are selectively turned on according to the address information and the burst length information to selectively select the plurality of output clock signals. And a predetermined number of the plurality of bits are selected by the selector unit by supplying a predetermined number of output clock signals passed through to the plurality of gates as the control signal . A data output unit provided between the selector unit and a data output terminal;
And a timing circuit that outputs a second control signal to the data output unit so that the data output terminal is in a high impedance state when the control signal from the selector control unit indicates an inactive state. The data conversion circuit according to claim 1, wherein: A data conversion circuit for converting parallel data of a plurality of bits read from a memory cell unit into serial data,
A plurality of first data bus lines for receiving the plurality of bits of parallel data;
A plurality of second data bus lines configured of a plurality of signal lines and outputting data of a predetermined number of signal lines corresponding to the burst length to the outside ;
In response to the burst length signal and the column address signal, a predetermined number of bits of the plurality of bits of parallel data of the plurality of first data bus lines are selected, and the selected bits are converted into the second data. A data bus switch circuit that switches connections between the plurality of first data bus lines and the plurality of second data bus lines so as to be supplied to the predetermined signal line of the bus lines;
A data conversion circuit comprising a parallel / serial conversion circuit for converting data of the predetermined signal line of the plurality of second data bus lines into serial data. 4. The data conversion circuit according to claim 3, wherein the data bus switch circuit includes a switch provided between one of the plurality of second data bus lines and the other one. 5. The data conversion circuit according to claim 4, wherein the switch is ON / OFF controlled in response to the burst length signal and the column address signal. 4. The data conversion circuit according to claim 3, wherein the parallel / serial conversion circuit converts the data of the plurality of second data bus lines into serial data in a plurality of stages. The plurality of second data bus lines includes first, second, third and fourth data buses,
  The parallel / serial conversion circuit includes:
  A first latch circuit connected to the second data bus and operating in response to a first control clock signal;
  A second latch circuit connected to the third data bus and operating in response to a second control clock signal;
  A third latch circuit connected to the fourth data bus and operating in response to a third control clock signal;
  A first output buffer circuit connected to the first data bus and operating in response to the first control clock signal;
  A second output buffer circuit connected to the output of the first latch circuit and operating in response to the second control clock signal;
  Connected to the output of the second latch circuit and operates in response to the third control clock signal A third output buffer circuit that
  A fourth output buffer circuit connected to the output of the third latch circuit and operating in response to a fourth control clock signal;
  A first signal line to which the first and third output buffer circuits are connected in common;
  A second signal line to which the second and fourth output buffer circuits are connected in common;
  A data output timing switch for alternately connecting the first signal line and the second signal line to the output node in response to the output control clock signal
The data conversion circuit according to claim 3, further comprising:

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