JP3915102B2 - Broadcast receiver - Google Patents

Description

[0001]
[Industrial application fields]
  The present invention preserves memory contents with low power consumption at the time of power interruption such as a power failureBroadcast receiverIn particular, as a security device that secures highly confidential information safely and with low power consumption, such as key data essential for conditional access to digital TV broadcast programsBroadcast receiverAbout.
[0002]
[Prior art]
  The digital satellite broadcasting television in the prior art can be used by many broadcasting stations and many satellite broadcasting receivers by using one satellite. This broadcast system is hierarchized into systems, groups, and stations, and satellite broadcast receivers are assigned ID numbers.
[0003]
  As shown in FIG. 21, the program supply company has a studio 1 and a transmission station 2 as a configuration per station (transmission station). In the studio 1, video programs are produced, and the program data is stored and stored in a disk or LMS. In the transmission station 2, the video signal and audio signal of the program data sent from the studio 1 are input to the encoder 3.
[0004]
  The encoder 3 has a function of digitally encoding, data compression, multiplexing, error correction encoding, scrambling, packetizing, and encryption of video / audio analog signals of a plurality of programs.
[0005]
  Data compression uses the MPEG (International Standard for Video Coding) method, such as motion prediction / motion compensation, motion vector coding, etc., and reduces the number of video pixels, the number of bits, the number of transmitted data, etc. Yes.
[0006]
  Multiplexing is performed by arranging a plurality of video / audio / auxiliary signals in series by a multiplexer.
[0007]
  In error correction coding, an error correction code such as a Reed-Solomon code is attached to a multiplexed data block.
[0008]
  Scrambling is performed for energy diffusion. For packetization, a packet header is added to the head of the multiplexed, error correction encoded, and scrambled data stream to form one packet. The packet header includes a synchronization bit and service data.
[0009]
  In encryption, encryption is put in the service data of a packet. The cipher has a hierarchical structure formed by three layers of a session key, a work key, and an individual key. The session key and the work key are keys for decryption and transmitted from the transmitting station 2 as a signal, The individual key will be described later.broadcastStored in the receiver / decoder (IRD).
[0010]
  The high-efficiency encoded and encrypted TV data by the encoder 3 is input to the modulation / amplification unit 5.
  The modulation / amplification unit 5 performs high-power amplification (HPA) after performing multilevel digital modulation, for example, QPSK (4-phase shift keying) modulation on a 12 GHz carrier wave.
[0011]
  The 12 GHz TV signal is transmitted from the antenna 6 toward the satellite 7. The satellite 7 relays the 12 GHz digital TV signal and transmits it to the ground.
[0012]
  The digital TV signal transmitted from the satellite 7 to the ground is received by the satellite broadcast receiver 8A and the antennas 8 and 9 of the CATV station 9A. However, in order for a receiver having the satellite broadcast receiver 8A or a receiver using the CATV station 9A to view a broadcast program, it is necessary to have IRD (Integrated Receiver / Decoder) 10, 10A. . That is, the reception signal from the antenna 8 is reproduced on the TV 11, the VCR 12, the video disk 13, etc. via the IRD 10.
[0013]
  There are a basic system, an IC card system, and a telephone modem system as a digital TV signal reception system by the receiver IRD 10 equipped with the satellite broadcast receiver 8A.
[0014]
  In the basic method, the IRD 10 extracts (accesses) the video / audio signal by decrypting the encryption with the decryption key transmitted from the transmitting station 2 and the individual key stored in the IRD 10, and converts it into the TV. The image data is supplied to the receiver 11, the VCR 12, and the video disk 13.
[0015]
  In the IC card system, program data is accessed by inserting the IC card 14 into the IRD 10. In the telephone modem system, the satellite broadcast receiver can access the program data through the management center via the telephone 15.
[0016]
  On the other hand, the CATV station 9A delivers the television signal received from the satellite 7 to the IRD 10A of the receiver having the CATV receiver 9B contracted with the CATV station 9A via the cable. The operation of the IRD 10A of the receiver having each CATV receiver 9B is the same as that of the IRD 10 of the satellite broadcast receiver 8A.
[0017]
  As a charging method using the IRD 10 of the satellite broadcast receiver 8A and the IRD 10A of the CATV receiver 9B, flat, tier, and pay-per-view (PPV) are possible.
[0018]
  As the PPV method, a pay / program method for charging a program and a pay / time method for charging time are used. The basic system, IC card system, and telephone modem system correspond to the PPV system.
[0019]
  In addition to the digital satellite broadcast television described above, a microcomputer incorporating a CPU and a memory (RAM or ROM) is widely used in various electronic devices. As a means for maintaining at the time of a power failure, a method of saving the contents of a memory to an NVM (Non Voltage Memory) provided outside the microcomputer through an external bus is common.
[0020]
  In addition, as a method that does not require the contents of the memory to be saved outside the microcomputer, it is also well known to switch the power supply of the microcomputer to a backup power supply made of a battery.
[0021]
  On the other hand, not only the digital satellite broadcasting television described above but also a paid digital TV broadcasting system that has been rapidly developing recently, in order to access the encrypted program data and view the program, It is necessary to store key data in the microcomputer memory (conditional access or conditional access). Since this key data is extremely confidential, it must be prevented from being read from the outside.
[0022]
[Problems to be solved by the invention]
  However, the conventional access system (CAS) equipped with a microcomputer has the following problems.
[0023]
  (1) In the method of saving the contents of the memory to the NVM at the time of a power failure or the like, the contents of the NVM can be read by some means from the outside of the microcomputer. Therefore, it is not desirable from the viewpoint of security to save extremely confidential data such as the key data in the NVM.
[0024]
  (2) The method of using a battery as a backup power source at the time of a power failure has only a backup capacity for several power failures because of the large power consumption at the time of backup.
[0025]
  (3) In a normal mask ROM, the format of data to be written is the same, so it is impossible to write the key data of each receiver.
[0026]
  Therefore, the present invention eliminates the above problems and incorporates a memory for storing highly confidential information.Broadcast receiverHowever, there is a problem that must be solved so that the contents of the memory are not saved in the external memory and the power consumption of the backup power source can be reduced in the event of a power failure.
[0027]
[Means for Solving the Problems]
  In order to solve the above-mentioned problem, a broadcast receiving apparatus according to the present invention has received data having a function of decrypting the received data based on encryption information necessary for a conditional access operation included in the received data. Conditional access data including decryption means, the encryption information, and decryption information for decrypting the encryption informationAnd the program information of the received data composed of the encryption information and the non-encryption information and configured in a predetermined data formatIs formed by a plurality of memories built in the microcomputer in the apparatus, and the received data decryption is performed based on the encryption information and the conditional access data stored in the formed memory space. Control means for controlling the conditional access operation together with means, power supply voltage detection means for detecting the voltages of the main power supply and the backup power supply,
When the power supply voltage detecting means detects a voltage drop of the main power supply, the control means shifts to a standby mode that operates with the backup power supply, and the main power supply is Switch to a backup power source, and at least the encryption information and the conditional access dataAnd program information of the received dataCan be held in a state of being stored in a memory space formed by a plurality of memories built in the microcomputer in the apparatus.
[0028]
  Further, the control means stores decryption information for decrypting the encryption information in a predetermined area where write protection of the memory space is performed; the encryption information is used in a conditional access operation of digital satellite broadcasting. The broadcast receiving apparatus is characterized in that the information is encrypted information based on an encrypted structure.
[0029]
[Action]
  The broadcast receiving apparatus configured as described above has the following effects.
Broadcast receiverBy control meansA memory space is formed by a plurality of memories built in the microcomputer in the apparatus, and the conditional access data including encryption information and decryption information for decrypting the encryption information is stored in the formed memory space. Based on this encryption information and conditional access data, the conditional access operation is controlled together with the received data decrypting means, and when the power supply voltage detecting means detects a drop in the voltage of the main power supply, it shifts to the standby mode that operates with the backup power supply. At the same time, the main power source is switched to the backup power source, and the encryption information and the conditional access data stored in the memory space are kept stored, thereby reading out highly confidential information from the outside. Extremely low power consumption in inaccessible memory space It can be held as it is in the stomach condition.
[0030]
  By storing the decryption information for decrypting the decryption information in a predetermined area where the write protection of the memory space is performed, rewriting of the decryption information can be restricted.
[0031]
  Delete
[0032]
  Delete
[0033]
  Delete
[0034]
  Delete
[0035]
【Example】
  Hereinafter, according to the present inventionBroadcast receiverExamples will be described. In this embodiment, the microcomputer of the conditional access system (CAS) in the receiver of the scramble / descramble transmission system through radio waves used in the digital satellite broadcast television shown in FIG. 22 used in the prior art is used. The configuration relates to an integrated receiver decoder IRD (Integrated Receiver Decoder).
[0036]
  That is, in the pay broadcasting, when the decoding information (information for decrypting and descrambling) is sent from the transmission side, the decoding information and the information (key data) of the device owned by the user match (OK for charging). If so, the user can view the desired information, eg, TV.
[0037]
  The encryption structure of the key data constituting this decoding information is three layers, of which the session key and work key are transmitted by radio waves.
[0038]
  The individual key, which is key data for extracting the video / audio signal by decrypting the encryption based on the decryption key transmitted by the above-mentioned radio wave,decoder(Broadcast receiving device)Store in advance inside.Also transmitted by radio wavesConditional access information is delivered by multiplexing a plurality of data in a transmission packet.
[0039]
  In this embodiment, the decoder does not save these key data used by the user to the external memory.The structure for hold | maintaining in the microcomputer in (broadcast receiving apparatus) is shown.
[0040]
  The following items,
[1] IRD (decoder)
  (1) Video / audio section
  (2) Central control unit
  (3) CA Department (Conditional Access Department)
[2] Center microcomputer
  (1) Configuration
  (2) Backup power supply
[3] CAS (Conditional Access System)
  (1) Overview
  (2) CA memory map
  (3) NIF (network interface)
  (4) EEPROM
  (5) CA operation (conditional access operation)
[4] Standby mode function
  (1) Overview
  (2) Standby circuit
  (3) Sleep mode
  (4) Stop mode
  (5) Canceling standby mode
    (A) Canceling sleep mode
    (B) Canceling stop mode
    (C) Instruction execution after standby mode is released
It explains according to.
[0041]
[1] IRD (decoder)
  IRD10(Broadcast receiving device)As shown in FIG. 1, there are roughly divided a video / audio unit 16A for extracting video and audio from an antenna input signal, a central control unit 33A, and a CA unit (conditional Access unit) 41A.
[0042]
(1) Video / audio section
  The video / audio unit 16A includes a tuner 16, a QPSK demodulator 17, a Viterbi decoder 18, an NIF 19, an MPEG audio decoder 20, a coaxial driver 21, an optical driver 22, a digital audio interface (hereinafter referred to as DAI). 23), a digital filter (hereinafter referred to as DF) 24, a D / A converter 25, an MPEG video decoder 26, a microcomputer 27, a D / A converter 28, a mixer 29, and an OSD. The circuit 30 and the OSD / EPG microcomputer 31 are configured.
[0043]
  The tuner 16 selects a channel signal designated by the central control unit 33A from the 12 GHz signal received by the DTH antenna 9 and sends it to the QPSK demodulator 17.
[0044]
  The QPSK demodulator 17 sends multiplexed data obtained by demodulating the signal selected by the tuner 16 to the Viterbi decoder 18.
[0045]
  The Viterbi decoder 18 performs convolution decoding on the multiplexed data demodulated by the QPSK demodulator 17. This is to restore the convolutional encoding on the transmission side. The convolutionally decoded signal is input to the NIF 19.
[0046]
  The NIF 19 outputs the packet signal to the MPEG audio decoder 20 and the MPEG video decoder 26 by decoding the encryption contained in the received data in cooperation with the CA unit 41A.
[0047]
  The NIF 19 separates six types of encrypted information, that is, program information, extended program information, individual information, extended individual information, individual message information, and common message information, which will be described later.CA memory (conditional access memory) spaceIt has a function to write to. This will be described later.
[0048]
  The NIF 19 includes a Reed-Solomon error correction circuit 19a,DeA multiplexor (hereinafter referred to as DMPX) 19b, a descrambling circuit 19c, and a DMPX 19d.
[0049]
  The Reed-Solomon error correction circuit 19 a performs error correction using a Reed-Solomon code attached to the packet output from the Viterbi decoder 18.
[0050]
  The DMPX 19b divides the packet into blocks, and the descrambling circuit 19c unscrambles.
[0051]
  The DMPX 19d further divides the output data of the descrambling circuit 19c into individual video / audio signals and outputs them to the MPEG audio decoder 20 and the MPEG video decoder 26, respectively.
[0052]
  The MPEG audio decoder 20 restores the signal from the NIF 19, that is, the data-compressed digital audio signal, and outputs it to the coaxial driver 21, the optical driver 22 and the DAI 23.
[0053]
  The coaxial driver 21 drives an acoustic device through a coaxial cable, and the optical driver 22 drives an optical acoustic device such as a compact disk through an optical fiber.
[0054]
  The DAI 23 sends the digital audio signal from the MPEG audio decoder 20 to the DF 24.
[0055]
  The DF 24 extracts only a specific digital signal, filters the digital audio signal from the DAI 23, and sends it to the D / A converter 25.
[0056]
  It is converted into the original analog audio signal by the D / A converter 25 and supplied to the speaker of the TV receiver, for example.
[0057]
  On the other hand, the MPEG video decoder 26 decodes the video signal into R, G, and B signals under the control of the microcomputer 27 and supplies the output signal to the D / A converter 28. The analog RGB signal from the D / A converter 28 is supplied to the mixer 29.
[0058]
  The mixer 29 supplies a video signal obtained by superimposing the RGB signal from the D / A converter 28 and the RGB signal from the on-screen display (OSD) 30 to, for example, a CRT of the receiver.
[0059]
  The OSD 30 sends message information stored in the memory 32 to the mixer 29 under the control of the microcomputer 31. As a result, a message or the like is superimposed and displayed at a predetermined position on the video screen.
[0060]
(2) Central control unit
  The central control unit 33A includes a center microcomputer 33, a remote controller 34 operated by a user, a remote control receiver 35 attached to the center microcomputer 33, a front panel key 36, an LED display 37, a rear panel 38, And a power supply circuit 40.
[0061]
  The center microcomputer 33 incorporates various programs, executes a program corresponding to the command code from the remote controller 34, and controls the video / audio unit 16A and the NIF 19 via the bus line.
[0062]
  The center microcomputer 33 performs overall communication by performing mutual communication with the MPEG microcomputer 27, the OSD / EPG microcomputer 31, and the CA microcomputer 41 of the MPEG video decoder 26. The structure of the center microcomputer and the structure of the backup power supply will be described later.
[0063]
  The remote controller 34 is operated by a user and has a function of sending various command codes on infrared rays. The command code output from the remote controller 34 is received by the light receiver 35 and sent to the center microcomputer 33.
[0064]
(3) CA Department (Conditional Access Department)
  The CA unit 41 </ b> A includes a CA microcomputer 41 that communicates with the center microcomputer 33, an IC card reader 42 connected to the CA microcomputer 41, and a modem 43. The IC card reader 42 and the modem 43 have the same configuration as that shown in FIG. That is, the IC card reader 42 is for reading the IC card 14 when used in the IC card reader control system, and the modem 43 is connected via a telephone line when used in the telephone control system.Microcomputer 41 for CAAnd communication between the management center.
[0065]
[2] Center microcomputer
  The IRD 10 configured as described above transmits and receives various data via an interface with the MPEG microcomputer 27, the OSD / EPG microcomputer 31, and the CA microcomputer 41 that communicate with each other via the center microcomputer 33.
  Hereinafter, (1) the configuration of the center microcomputer and (2) the configuration of the backup power source of the center microcomputer will be described.
[0066]
(1) Configuration of center microcomputer
  As shown in FIG. 2, the center microcomputer 33 includes a central processing unit (hereinafter referred to as CPU) 51 and a synchronization / system clock circuit connected to the CPU 51.57 (hereinafter referred to as Circuit 57),RAM 54, ROM 55, power supply circuit52Through the bus line 51A, the prescaler 62, time base timer 63, interrupt controller 64, on-screen display 64a, input / output circuit 64b, timer / counter 64c, remote control circuit 64d, horizontal synchronization counter 64e, AC timer 64f, A / D converter 64g, I2C interface 64h, watchdog timer 64i, 14-bit PWM circuit 64j, 6-bit PWM circuit 64k, and ports A to F are connected to each other.
[0067]
  The ROM 55 is a one-time type (WO) having a read-only memory ROM that cannot be erased once data is written to the memory.
[0068]
  The interrupt controller 64 includes a prescaler 62, a time base timer 63, an interrupt controller 64, an on-screen display 64a, an input / output circuit 64b, a timer / counter 64c, a remote control circuit 64d, a horizontal synchronization counter 64e, an AC timer 64f, and an A / D. A converter 64g, an I2C interface 64h, a watchdog timer 64i, a 14-bit PWM circuit 64j, and a 6-bit PWM circuit 64k are connected to an external microcomputer such as an MPEG microcomputer 27, an OSD / EPG microcomputer 31, respectively. Interrupt control is performed when communicating with the CA microcomputer 41.
[0069]
(2) Backup power supply
  On the other hand, the configuration of the backup power supply of the center microcomputer 33 is as shown in FIG. 2 and mainly as shown in FIG. 3. The backup power supply 45 provided outside, the power supply circuit 52, and the crystal oscillator (crystal oscillator, hereinafter referred to as XTAL). ) 58, diodes 59 and 60 provided outside, and a power supply voltage detection circuit 61.
[0070]
  The backup power supply 45 is supplied from a power supply circuit 40 which is a main power supply that supplies power to the center microcomputer 33 shown in FIG. 1, and is constituted by a battery or a capacitor.
[0071]
  As shown at point A in FIG. 3, the power supply circuit 52 is connected to the power supply circuit 40 and the backup power supply 45 via a diode 59, and its output side is connected to the CPU 51.
[0072]
  Further, between the power supply circuit 40 and the diode 59 and between the power supply circuit 52, as shown at a point B in FIG. 3, a power supply voltage detection circuit 61 is connected via a diode 60.
[0073]
  The diodes 59 and 60 are provided to prevent a voltage shift, for example, a difference of 0.7 volts, and to supply electricity from the backup power supply 45 when not energized.
[0074]
  The power supply voltage detection circuit 61 has a function of detecting the voltage VA of the main power supply supplied from the power supply circuit 40 and the voltage VB of the backup power supply 45 and reporting them to the CPU 51 via the power supply circuit 52.
[0075]
  The center microcomputer 33 configured as described above includes a RAM 54 and a ROM 55, and a condition constructed by the microcomputers 27, 31, 33, and 41 using the memory space formed by the RAM 54 and the ROM 55, that is, the CA memory space. It is possible to realize an attached access, that is, a function for operating a conditional access and a function for operating a mode control program (standby function). Hereinafter, [3] CAS (conditional access system) and [4] standby mode function will be described in this order.
[0076]
[3] CAS (Conditional Access System)
(1) Overview
  CAS is composed of the RAM and ROM described above.CA memory spaceThe data stored in the determined areas are sequentially used to control various microcomputers and execute programs.
[0077]
  On the other hand, CAS is a transmission method using radio waves that provides information for a fee, and is composed of CA data having a predetermined cryptographic structure for checking whether or not a fee is charged when providing information.
[0078]
  This encrypted CA data isCA memory spaceAre stored in a predetermined area and constructed in a predetermined format, read out by the NIF, and appropriately processed. The ROM contains an EEPROM, and this EEPROM is routineized by a method according to a certain rule.
[0079]
  The cryptographic structure consists of three layers: session key, work key, and individual key. Among them, the session key and work key are CA information (conditional access information) transmitted by radio waves.Included in theIndividual key isCA memory spaceIn the predetermined area.
[0080]
  This CA information is classified into the following three types.
  That is,1:Program information consisting of session key, billing method, fee, etc., extended program information,2:Individual information consisting of work key, information sent to individual IRD 10, etc., extended individual information,3:They are classified into individual messages consisting of message information and common messages.
[0081]
  In this way, the CA information transmission multiplexing method classified into three types multiplexes a plurality of data in a transmission packet, and the transmission rate is about 256 Kbps. Also, up to 16 systems of CA information can be transmitted simultaneously. Of course, these speeds and numbers are not limited.
[0082]
  On the other hand, as a charging method, flat, tier, and pay / view (pay / program, pay / time) are possible.
  The pay / view control is compatible with the basic method, IC card method, and telephone modem method. In addition, 7 levels can be set as the parental level.
[0083]
  In addition, as a general feature of CAS, with regard to message delivery, delivery to the IRD and delivery to all IRDs are possible.
[0084]
  Furthermore, it also supports security (Renewable Security) using an IC card.
[0085]
  Also, a plurality of IDs for IRD in units of systems and groups can be included in the IRD, and different control for each business operator is possible.
[0086]
(2) CA memory map
  CAS with such characteristicsCenter microcomputer 33Is formed of a RAM 54 and a ROM 55 as shown in FIG.In CA memory spaceCreate a CA memory map.
[0087]
  This CA memory mapCA memory space to createAre divided by usage.
  For example, 512 bytes from address 0000H are divided into two pages in units of 256 bytes, which are called page 0 and page 1.
[0088]
  Data in these areas can be accessed by an addressing mode such as direct page addressing. On page 0 and page 1, a RAM area and a peripheral hardware (I / O) function register area are secured. Also, the stack area is taken up in one page of RAM.
[0089]
  The built-in program area has addresses B000H / A000H to FFFFH and is divided as shown below.
[0090]
  Addresses C000H to C07FH are areas of the NIF buffer. Addresses C080H to FAFFH are areas where system control programs common to each IRD 10 reside..
[0091]
  Addresses FB00H to FBFFH are areas corresponding to the EEPROM, and key data individually assigned to each IRD 10 is stored. This area is usually protected and cannot be changed. As a special mode, writing is possible as shown in FIG.Center microcomputer 33This is only when a supervisor command is designated from the outside via the input / output circuit 64b corresponding to the serial interface. The EEPROM will be described later.
[0092]
  The 256 bytes of addresses FF00H to FFFFH are called U pages and are used for various purposes.
[0093]
  Of these, 32 bytes of addresses FFC0H to FFDFH contain a subroutine vector address of a table call (TCALL) instruction. An interrupt vector address including a reset vector is entered in 32 bytes of addresses FFE0H to FFFFH.
[0094]
  Next, the aboveCA memory space providedThe conditional access operation (CA operation) in CAS is NIF19.SuchControlled by
[0095]
  That is, the IRD 10 that has received the CA information by the video / audio unit 16A of the IRD 10 selects the six types of encrypted CA data according to the selection.CA memory spaceAre read from the CA memory map by the NIF 19, and each processing is performed.
[0096]
  The six types of CA data are composed of program information, extended program information, individual information, extended individual information, individual messages, and common messages, each of which is organized in a predetermined format.
[0097]
(3) NIF (network interface)
  The NIF 19 has a built-in SRAM as a buffer.CA memory spaceTo C000H to CO7FH.
[0098]
  The NIF 19 buffer is shown in FIG.Within the CA memory space4 blocksDivided,Six types of CA data are stored.
  Block 0 (C000H to C01FH) Program information
  Block 1 (C020H to C03FH) Extended program information
  Block 2 (C040H to C05FH) Individual information, extended individual information
  Block 3 (C060H to C07FH) Individual message, common message
[0099]
  Since the interrupt signal is output every time the CA data from the NIF 19 is written to each of the blocks 0 to 3, the program reads each time and performs the respective processing. In particular, block 0 interrupts occur frequently and are read out once per second.
[0100]
  Data can be written to the NIF buffer by designating predetermined addresses C000H to C029H. Writing to any other address is ignored. Although partially overlapping with the read address, since the read / write buffer is separated in the NIF 19, independent access is possible.
[0101]
  Each format of program information, extended program information, individual information, extended individual information, common message, and individual message constituting CA data is shown in FIGS.
[0102]
  All formats consist of unencrypted information and encrypted information.
  The first type identification (8 bits) of the unencrypted information represents the type of information by the following numbers.
  0: Reserved, 1: Program information, 2: Individual information, 3: Common message, 4: Individual message, 5: Extended program information, 6: Extended individual information, 7: Reserved
[0103]
  The non-encrypted information of each format of program information, extended program information, and common message is the system number (up to 255 systems), group number (up to 65,535 groups), protocol number, and station number (after the type identification). (Up to 255 stations), work key number (KwNo) (up to 255), and CA program number.
[0104]
  In addition, the unencrypted information in each format of individual information, extended individual information, and individual message is configured to include a system number, a group number, and a decoder ID number (232 units) after type identification.
[0105]
  The non-encrypted information portion of each format is followed by the encrypted information portion, and the contents thereof are as follows for each format.
[0106]
  As shown in FIG. 5, the encrypted information portion of the format of the program information includes a session key (Ks), a program configuration (indicating video, audio, and data), block level designation, tier designation (tier mode and (Tier code), real-time clock (year, month, day, hour, minute), program management (program number, etc.), fee information (charging category, charging method, PPV frequency), spare, and alteration detection. The encrypted part of the program information is decrypted with the work key Kw.
[0107]
  As shown in FIG. 6, the encrypted information portion of the format of the extended program information includes spare, extended type, extended designation, and alteration detection. The encrypted part of the extended program information is decrypted by the work key Kw.
[0108]
  As shown in FIG. 7, the encrypted information part of the format of the individual information includes the station number, work key number and work key information, authorization information (forced control method and video (main), video (sub) of all categories. , Audio and data), block level information and tier code information, expiration date information (year, month, day), PPV fee (charge information transfer request, prepayment / postpay, frequency addition information), reserve, and tamper detection Consists of. The encrypted portion of the individual information is decrypted with the individual key Km.
[0109]
  As shown in FIG. 8, the encrypted information portion of the extended individual information format includes a station number, an extension type, extended information, and falsification detection. This is decrypted by the individual key Km.
[0110]
  As shown in FIG. 9, the encryption information portion of the common message format includes message information and tamper detection. This is decrypted by the work key Kw.
[0111]
  As shown in FIG. 10, the encrypted information portion of the format of the individual message includes a station number, message information, and falsification detection. This is decrypted by the individual key Km.
[0112]
(4) EEPROM
  As shown in FIG.CA memory spaceFB00H to FF00H (EEPROM in the ROM 55) hold data having a hierarchical structure as shown in FIG.
  The memory area for storing the system, group, ID number, and individual key Km is normally write-protected, and the contents cannot be changed.
[0113]
  By specifying the station number by the station pointer, the station number, the authorization information, the expiration date information, and the PPV fee information about the station are obtained. By specifying the work key number by the work key pointer for each station, the work key information is obtained. It is supposed to be.
[0114]
(5) CA operation (conditional access operation)
  As shown in FIG.CA memory spaceThat is, using the NIF 19 for processing CA data corresponding to the session key and work key, and the EEPROM storing the individual keys, the center microcomputer 33 can perform the CA operation as shown in FIG. it can.
[0115]
  First, the received signal selected by the tuner 16 is divided into program information, individual information, individual message information, and common message information by the NIF 19 according to service information included in the data block.
[0116]
  In the case of program information, the station number and work key number are input to the EEPROM station pointer and work key pointer from the non-encrypted part (system, group, station, and work key numbers).
[0117]
  As a result, the work key information is read from the EEPROM, and the encrypted part of the program information is unencrypted by this work key information. As a result, the session key Ks and the program configuration information are sent to the descrambler 48. Information is descrambled.
[0118]
  Here, the system, group, ID, and individual key numbers are stored in the EEPROM in a non-writable manner.
  Therefore, the encrypted portion of the individual information is unencrypted with the individual key Km and stored in the EEPROM.
[0119]
  In the case of individual message information, it is unencrypted by the individual key Km, sent to the OSD 30, and displayed superimposed on the video screen.
[0120]
  In the case of the common message information, it is unencrypted by the work key Kw, sent to the OSD 30, and is superimposed on the video screen.
[0121]
  For example,When the output voltage VA of the power supply circuit 40 shown in FIG. 1 decreases due to a power failure or the like, the CPU 51 shown in FIG.To enter the sleep mode described laterWithMain power supplied from the power circuit 40It has a standby mode function that is driven by a so-called mode control program that switches to the backup power source 45.
[0122]
  As will be described later, the sleep mode(Standby mode)Is composed of a RAM 54 and a ROM 55.CA memory spaceIs stored as it is, and is not read from the outside. Also sleep mode(Standby mode)During this period, power consumption is extremely low, so there is no worry about prolonged power outages.
[0123]
[4] Standby mode function
(1) Overview
  As for the standby mode function, two modes are prepared in order to reduce power consumption of devices such as the IRD 10. These two modes are called a sleep mode and a stop mode, and both modes are collectively referred to as a standby mode because program execution is stopped. Further, the CPU clock variable function allows operation in a wide power supply voltage range during battery backup.
[0124]
  In this way, the mode control program that controls the standby mode function constantly monitors the power supply of the IRD 10 even when the above-described CA operation is being performed by the voltage detection means, and when the abnormality is detected, the switching means quickly determines the system. Operates to save the minimum required data.
[0125]
  That is, as shown in FIG. 13, when the CPU 51 shown in FIG. 2 is driven, the voltage VA for the main power supply of the power supply circuit 40 is always compared with the voltage VB of the backup power supply 45 (ST1). .
[0126]
  If the main power supply voltage VA becomes smaller than the backup voltage VB, the input of the power supply circuit 52 shown in FIG. 3 is switched from the power supply circuit 40 to the battery power supply 45 and at the same time a sleep command is issued. ,CA microcomputer 41 etc.The sleep mode(Standby mode)(ST2).
[0127]
  In this state, that is, sleep mode(Standby mode)In this state, the main power supply voltage VA and the backup power supply voltage VB are always compared and wait for equality (ST3).
[0128]
  If the main power supply voltage VA becomes equal to the backup power supply voltage VB, that is, when the main power supply voltage VA is restored, an interrupt request is generated in the interrupt controller 64 shown in FIG. 2 (ST4). ).
[0129]
  And sleep mode(Standby mode)And the power source is switched to the main power source (ST5).
[0130]
  If not in the stopped state, the main power supply voltage VA and the backup power supply voltage VB are compared again, and if in the stopped state, the voltage comparison ends (ST6).
[0131]
(2) Standby circuit
  The center microcomputer 33 has an operation mode and a standby mode. The operation mode is shown in FIG. 2 and FIG.Block DiagramThe circuit group in FIG.
[0132]
  The standby mode is shown in FIGS. 2 and 3 as shown in FIG.Block DiagramIt operates by a standby circuit provided in addition.
[0133]
  The standby mode includes a sleep mode and a stop mode, and the CPU 51 shifts to each mode by a sleep command and a stop command.
[0134]
  As shown in FIG. 14, the standby circuit 70A includes a crystal oscillator 58 (hereinafter referred to as XTAL) 58, a clock circuit 57a, a prescaler 62, a time base timer 63, an overflow detection 63a, a timing generator 65, and a selector. 66, OR circuits 67 and 70, and flip-flops 68, 69, and 69a, and their connection states are as follows.
[0135]
  The input side of the clock circuit 57 a is connected to the XTAL 58, the output side is connected to the prescaler 62 and the timing generator 65, and the control terminal is connected to the plus output side of the flip-flop 68.
[0136]
  The prescaler 62 stops the connected peripheral hardware, and its output side is connected to the selector 66 and its control terminal is connected to the plus output side of the flip-flop 68.
[0137]
  The time base timer 63 generates an interrupt in accordance with the conditions of the prescaler 62, its input side is connected to the selector 66, its output side is connected to the overflow detection 63a, and its control terminal is a flip-flop 68. Is connected to the positive output side.
[0138]
  The timing generator 65 generates the clock of the CPU shown in FIG. 4, its output side is connected to the CPU clock 65 a, and its control terminal is connected to the output side of the OR circuit 67. The CPU clock 65a isCPU51 is a clock necessary for operation.
[0139]
  The output side of the OR circuit 67 is connected to the control terminal of the timing generator 65, one input terminal thereof is connected to the plus output side of the flip-flop 69a, and the other input terminal is connected to the plus output side of the flip-flop 69. ing.
[0140]
  A stop command is input to the set side of the flip-flop 68, and its reset side is connected to the output side of the OR circuit 70.
[0141]
  The sleep command is input to the set side of the flip-flop 69, and the reset side is connected to the output side of the OR circuit 70.
[0142]
  The set side of the flip-flop 69a is connected to the plus output side of the flip-flop 68, and the reset side is connected to the output side of the overflow detection 63a.
[0143]
  The output side of the OR circuit 70 is connected to the reset side of the flip-flops 68 and 69, and one input terminal receives a release signal from the interrupt controller 64, and the other input terminal receives a reset signal. It comes to input.
[0144]
  The standby circuit 70A configured as described above enters the sleep mode or stop mode state shown below by the sleep command or stop command.Dobe able to. Hereinafter, (3) sleep mode, (4) stop mode, and (5) standby mode will be described in this order.
[0145]
(3) Sleep mode
  The sleep mode can be changed by a sleep command in the program. In this mode, the CPU clock supplied for the operation of the CPU 51 can be stopped while the XTAL 58 is operated.
[0146]
  That is, the plus side output of the flip-flop 69 is set to “1” by the sleep instruction, and as a result, the output of the OR circuit 67 is set to “1”, and the timing generator 65 is stopped while the clock circuit 57a is operating.
[0147]
  As a result, the CPU clock (φ) 65a is stopped. In this case, since the output of the flip-flop 68 is “0”, the clock supplied from the prescaler 62 is operating normally, so that the operation of the time base timer 63 and some of the peripheral hardware is possible. .
[0148]
  However, as shown in FIG. 15, shown in FIG.CA memory spaceBy controlling the clock control register existing at the address 00FEH, the clock supplied from the prescaler 62 can also be stopped by the program.
  Therefore, excessive current consumption can be prevented when peripheral hardware other than the time base timer 63 is not used in the sleep mode.
[0149]
  In order to stop the clock supplied to the peripheral hardware, the prescaler 62 sets the peripheral hardware clock control bit (PHON) supplied to the clock control register 71 to “0” as shown in FIGS. To stop peripheral hardware.
[0150]
  In this manner, as shown in FIG. 17, the clock circuit 57a can enter the sleep mode in an oscillated state by the sleep command.
[0151]
  When entering sleep mode,Each circuitThis state is as shown in FIG. That is, the operation state is maintained by the XTAL 58, the prescaler 62, the time base timer 63, the PWM 64j, and 64k.
[0152]
  In sleep modeOperating state atThe contents of various registers, the RAM 54, and the I / O ports A to F are held.
[0153]
  Also, it is the clock circuit that is stopped in the sleep mode.57An on-screen display 64a, an I2C interface 64h, a horizontal synchronization counter 64e, a remote control 64d, an A / D converter 64g, a power frequency counter, a serial I / O 64b, a timer / counter 64c, and a watchdog timer 64i.
[0154]
(4) Stop mode
  The stop mode is executed by a stop instruction in the program. This mode isClock circuitSince the oscillation of 57 is also stopped, all clocks are stopped and ultra-low power consumption can be realized. Note that all register, RAM, and ROM data are maintained.
[0155]
  That is, in the standby circuit shown in FIG. 14, when the stop command is received, the plus side output of the flip-flop 68 becomes “1”, and the clock circuit 57a is stopped. At the same time, when the plus side output of the flip-flop 68 is “1”, the plus side output of the flip-flop 69 a is also set to “1”, the output of the OR circuit 67 is set to “1”, and the operation of the timing generator 65 is stopped. Let Accordingly, as shown in FIG. 19, the XTAL 58 crystal oscillator is operating, but all the clock signals are stopped. At this time, as shown in FIG. 18, only the contents of the register, the contents of the RAM, and the states of the I / O ports A to F are held.
[0156]
(5) Canceling standby mode
  The standby mode is released by three types of release factors. That is,1:Input of a reset signal to the OR circuit 70 shown in FIG.2:Input of a sleep mode release signal or stop mode release signal from the interrupt controller 64,3:In the case of canceling the sleep mode, there are three types of canceling factors: canceling by an interrupt by the time base timer 63 shown in FIG. Hereinafter, (a) cancellation of sleep mode, (b) cancellation of stop mode, and (c) instruction execution after cancellation of standby mode will be described in this order.
[0157]
(A) Canceling sleep mode
  The sleep mode is canceled by inputting a reset signal and an interrupt as shown in FIG. When the reset signal is used, the output side of the OR circuit 70 shown in FIG. 14 becomes “1”, and the clock circuit 57 a can be operated by resetting the flip-flop 68. In case of release by reset signal,DeviceThe initial state is entered, and the registers and the like are defined at reset.
[0158]
  In the case of an interrupt, it is a so-called hardware interrupt, and may be a sleep mode release signal and a time base timer 63. Usually, an interrupt by the time base timer 63 is used.
[0159]
  Release by the sleep mode release signal occurs when there is an external interrupt request.
[0160]
  In the case of release by the time base timer 63, it is released by an interrupt with a long cycle. The time base timer 63 is generated only when the sleep mode is canceled, and when the PHON bit of the prescaler 62 shown in FIG. 14 is “0” (see FIG. 15), that is, when the peripheral hardware clock is stopped. If the interrupt permission flag IE is “1”, an interrupt for canceling the sleep mode is performed.
[0161]
  When the sleep mode is released in this way, as shown in FIG. 17, in the case of a signal due to an interrupt, execution of the instruction is started immediately after the release. In the case of a reset signal, a predetermined instruction is executed after a lapse of time of two or more instruction cycles of the program.
[0162]
(B) Canceling stop mode
  Canceling the stop mode includes a reset signal and a cancel signal by an external interrupt.
[0163]
  For the reset signal,DeviceThe initial state is entered, and the register values are defined at reset.
[0164]
  In the case of a release signal due to an external interrupt, as shown in FIG. 14, the output side of the OR circuit 70 becomes “1”, the clock circuit 57a operates by resetting the flip-flop 68, and at the same time the flip-flop 69 is reset. As a result, the timing generator 65 can operate.
[0165]
  When the stop mode is released in this way, as shown in FIG. 19, the time required for generating the stable pulse signal by driving the clock circuit 57a that has been stopped by the release signal and the reset signal due to the interrupt, that is, the oscillation A normal clock can be generated after the stabilization time has elapsed.
[0166]
  That is, in the case of a cancel signal due to an interrupt, the oscillation stabilization time needs to be set in advance by a program.
[0167]
  In the case of a reset signal, it is necessary to cause a predetermined command to be executed after the lapse of time longer than the oscillation stabilization time.
[0168]
(C) Instruction execution after standby mode is released
  The operation after the standby mode is released differs depending on the contents of the interrupt-related registers before entering the standby mode. This will be described with reference to FIG. First, it is assumed that an interrupt request is generated when a standby mode is entered by a sleep command or a stop command (ST7, ST8, ST9).
[0169]
  Here, the state of each interrupt permission flag (IE flag) is checked. When the IE flag is “0”, the interrupt is blocked, and when it is “1”, the interrupt is permitted (ST10).
[0170]
  Then, as described above, the standby mode is canceled, and the state of the interrupt master permission flag (I flag) is checked at that time (ST11, ST12).
[0171]
  If the I flag is “0”, the process is executed from the instruction next to the sleep instruction or the stop instruction (ST13).
[0172]
  If the I flag is "1", program execution moves to the interrupt service routine (ST14).
[0173]
  Thus, in the sleep mode of the standby mode, data such as RAM and ROM are held as they are,Current consumption isWhen the current that normally flows is 10 mA, the current in the sleep mode is drastically reduced to 10 μA. That is, if the backup power supply 45 with a capacity of 400 mA / H is used, the normal mode has only (400 mA / H) ÷ 10 mA = 40 hours, but in the sleep mode, (400 mA / H) ÷ 10 μA = 40 × 10 @ 3 hours = 1666 days = 55 months = 4.6 years.
[0174]
【The invention's effect】
  As described above, according to the present inventionBroadcast receiverHas the following effects.
  (1)In the event of a power failure, the highly confidential data stored in the memory space formed by the multiple memories built in the microcomputer in the device is retained as it is, so the highly confidential data is saved. Security is improved because the external memory to be used is inexpensive and can be stored so that it cannot be read from the outside.It has an extremely excellent effect.
[0175]
  (2) IRD of pay digital television systemStore in (broadcast receiving device)Conditional accessSince key data (decryption information) for decrypting encryption information is stored in a write-protected area in a memory space formed by a plurality of memories built in the microcomputer in the apparatus, it cannot be changed normally. Key data (decryption information) can be stored in the stateIt has an extremely excellent effect.
[0176]
  (3)When switched to the standby mode, the main power supply is switched to the backup power supply, and highly confidential information is stored in the memory space formed by the multiple memories built in the microcomputer in the device. As a result, the storage state of the memory space can be maintained with extremely low power consumption, so the life of the backup power supply can be maintained for a long time. There is an extremely excellent effect that can be achieved.
[Brief description of the drawings]
[Figure 1]1 is a block diagram showing a configuration of an IRD (broadcast receiving apparatus) to which the present invention is applied in a digital TV satellite broadcasting system.
[Figure 2]IRD (broadcast receiver) shown in FIG.It is a block diagram which shows the structure of a center microcomputer.
[Fig. 3]Of the same IRD (broadcast receiving device)It is the schematic block diagram which showed the structure of the power supply for backup.
[Fig. 4]Of the same IRD (broadcast receiving device)It is explanatory drawing which shows the map state of a conditional access memory.
[Figure 5]In NIF of IRD (broadcast receiving apparatus) in FIG.It is explanatory drawing which shows the map state of a program expansion format.
[Fig. 6]In the same NIFIt is explanatory drawing which shows the map state of an extended program information format.
[Fig. 7]In the same NIFIt is explanatory drawing which shows the map state of an individual information format.
[Fig. 8]In the same NIFIt is explanatory drawing which shows the map state of an extended separate information format.
FIG. 9In the same NIFIt is explanatory drawing which shows the map state of a common message format.
FIG. 10In the same NIFIt is explanatory drawing which shows the map state of an individual message format.
FIG. 11In the IRD (broadcast receiving apparatus) of FIG.It is explanatory drawing which showed the EEPROM data structure of the center microcomputer.
FIG.Same IRD (broadcast receiver)It is explanatory drawing which shows the conditional access operation | movement of.
FIG. 13The IRD (broadcast receiving device)Enter sleep modeTransitionIt is a flowchart figure for detecting a state.
FIG. 14The IRD (broadcast receiving device)It is a schematic standby circuit diagram for operating the standby mode.
FIG. 15Of the standby circuit of FIG.It is explanatory drawing which showed the content of the register | resistor which controls a clock.
FIG. 16 is an explanatory diagram showing a part of the operation state of the standby circuit in a block diagram;
FIG. 17The IRD (broadcast receiving device) of FIG.It is explanatory drawing which showed the state in sleep mode with the timing chart.
FIG. 18Of the same IRD (broadcast receiving device)It is explanatory drawing which showed the state at the time of sleep mode and stop mode as a table | surface.
FIG. 19Of the same IRD (broadcast receiving device)It is explanatory drawing which showed the state of stop mode with the timing chart figure.
FIG. 20Of the same IRD (broadcast receiving device)It is the flowchart figure which showed cancellation of standby mode.
FIG. 21 is an explanatory diagram showing an example of a digital TV satellite broadcasting system.
[Explanation of symbols]
  1 studio
  2 transmitting stations
  3 Encoder
  4 Controller
  5 Modulation / amplification
  6, 8, 9 Antenna
10 IRD
11 TV receiver
12 VCR
13 Video disc
14 IC card
15 Telephone
16A Video / Audio part
16 Tuner
17 QPSK demodulator
18 Viterbi decoder
19 Network interface (NIF)
19a Reed-Solomon error correction circuit
19b Dual multiplexer
19c descrambler
19d Digital multiplexer
20 MPEG audio decoder
21 Coaxial driver
22 Optical driver
23 Digital Audio Interface (DAI)
24 Digital filter (DF)
25 Digital / analog converter (D / A)
26 MPEG video decoder
27 Microcomputer for MPEG
28 Digital / Analog Converter (D / A)
29 Mixer
30 OSD circuit
31 Microcontroller for OSD / EPG
32 memory
33A Central control unit
33 Center microcomputer
34 Remote control
35 Receiver
36 Front panel key
37 LED display
38 Rear panel
40 Power supply circuit
41A CA Department
41 CA microcomputer
42 IC card reader
43 Modem
45 battery
50 Polarity control circuit
51 CPU
52 Power supply circuit
54 RAM
55 ROM
57 Sync / System clock
57a Clock circuit
58 XTAL
59, 60 Diode
61 Power supply voltage detection circuit
62 Prescaler
63 Timebase timer
64 interrupt controller
64a on-screen display
64b I / O circuit
64c timer / counter
64d remote control circuit
64e horizontal sync counter
64f AC timer
64g A / D converter
64h I2 interface
64i watchdog timer
65 Timing Generator
66 selector
67, 70 OR circuit
68, 69, 69a flip-flop
71 registers

Claims (3)

Received data decrypting means having a function of decrypting the received data based on encryption information necessary for the conditional access operation included in the received data;
Stores the encryption information, conditional access data including decryption information for decrypting the encryption information, and program information of the received data composed of the encryption information and non-encryption information in a predetermined data format A memory space to be formed by a plurality of memories built in the microcomputer in the apparatus, and together with the received data decrypting means based on the encryption information and the conditional access data stored in the formed memory space Control means for controlling the conditional access operation;
Power supply voltage detection means for detecting the voltage of the main power supply and the backup power supply;
A broadcast receiving apparatus comprising:
When the control means detects a voltage drop of the main power supply by the power supply voltage detection means, the control means shifts to a standby mode that operates with the backup power supply,
Switch the main power source to the backup power source,
Holding at least the encryption information, the conditional access data , and the program information of the received data in a state of being stored in a memory space formed by a plurality of memories built in a microcomputer in the apparatus. A broadcast receiving device characterized. 2. The broadcast receiving apparatus according to claim 1, wherein the control means stores decryption information for decrypting the encryption information in a predetermined area where write protection of the memory space is performed. The broadcast receiving apparatus according to claim 1, wherein the encryption information is encryption information based on an encryption structure used in a conditional access operation of digital satellite broadcasting.

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