JP3920173B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device in which at least a capacitor and a bipolar transistor are formed on one substrate.
[0002]
[Prior art]
BiCMOS including a bipolar transistor and a CMOS field effect transistor (hereinafter, “MOS field effect transistor” is simply referred to as “MOS transistor”) has a high speed of the bipolar transistor, a high degree of integration and low power of the CMOS transistor. It is widely used as a circuit having both.
[0003]
When an analog circuit is configured with this BiCMOS, a highly accurate capacitive element (capacitor) is also required on the same substrate. As this capacitor, a capacitor (so-called “interpoly oxide capacitor”, hereinafter abbreviated as “IPO capacitor”) having a polycrystalline silicon film doped with impurities as electrodes on both sides of an oxide film is used. Unlike the capacitor (so-called “gate capacitor”) in which an insulating film is formed on a semiconductor substrate and an electrode made of polycrystalline silicon or the like is provided on the IPO capacitor (so-called “gate capacitor”), the capacitance value varies greatly depending on the bias condition. There is no problem.
[0004]
As a conventional example of a BiCMOS circuit provided with this IPO capacitor, there is a structure shown in FIG. This figure is a partial cross-sectional view of a BiCMOS circuit and shows a state before metal wiring is formed. In this example, a bipolar transistor B and a CMOS transistor M are formed in the element region isolated by the element isolation oxide film 14, and an IPO capacitor C is formed on the element isolation oxide film 14.
[0005]
The bipolar transistor B is embedded in the silicon substrate 1 N⁺A layer 11 and an N well 12 are provided, and a collector 31 formed on the N well 12 by a selectively implanted collector (hereinafter abbreviated as “SIC”) and a base formed on the N well 12. (Base region) 17 and an emitter (emitter diffusion layer) 62 formed immediately above the collector 31 of the base 17. Further, an emitter electrode 91A that is in contact with the emitter 62 is formed.
[0006]
The PMOS transistor and the NMOS transistor constituting the CMOS transistor M are formed adjacent to each other in the substrate surface, but only the NMOS transistor is shown in the cross section of FIG. The NMOS transistor M1 is formed in the P well 15, and the PMOS transistor (not shown) is formed in the N well (not shown).
[0007]
The IPO capacitor C includes a lower electrode 93A and an upper electrode 77 made of a polycrystalline silicon film to which impurities are added, and an insulating layer 78a made of a silicon oxide film formed by a CVD method. The lower electrode 93A is formed from a thin film (polycrystalline silicon film doped with impurities) common to the gate electrode 92A of the CMOS transistor M by a photolithography process and an etching process. The upper electrode 77 is formed from a thin film (polycrystalline silicon film doped with impurities) common to the emitter electrode 91A of the bipolar transistor B by a photolithography process and an etching process.
[0008]
In the semiconductor device having the structure shown in FIG. 14, as shown in FIG. 15, the process up to the formation of the base region 17 is completed for the bipolar transistor B, the whole process is finished for the CMOS transistor M, and the IPO capacitor C is finished. After the process up to the formation of the lower electrode 93A is completed, the process of forming the bipolar transistor B and the IPO capacitor C is continued in a state where the CMOS transistor M is protected by the protective film 78. FIG. 15 shows a state in which the resist pattern 25 having the opening 25a corresponding to the emitter region is formed on the protective film 78 in the above state.
[0009]
As the protective film 78, for example, a silicon oxide film is formed with a thickness of about 50 to 200 nm by a low pressure CVD method using TEOS (tetraethoxysilane) as a raw material at a temperature of about 700 ° C. Then, as shown in FIG. 15, phosphorus ions (P) are formed in the N well 12 from the opening 25a corresponding to the emitter region through the protective film 78, the silicon oxide film 22, and the base region 17 by the SIC method.⁺) Is ion-implanted. Thereby, as shown in FIG. 16, the collector 31 is formed directly under the emitter region.
[0010]
Next, by using this resist pattern 25, the protective film 78 and the silicon oxide film 22 corresponding to the opening 25a are etched to form a base region corresponding to the opening 25a as shown in FIG. The portion 17 (the upper surface 17b of the emitter region) is exposed.
Next, after removing the resist pattern 25, a polycrystalline silicon film 79 is formed as shown in FIG. As a result, a polycrystalline silicon film 79 is formed on the exposed surface of the base region 17 and the protective film 78. In this state, arsenic ions (As⁺) Is ion-implanted. Next, for example, by performing a heat treatment that keeps the temperature at about 850 to 1100 ° C., the arsenic ions implanted into the polycrystalline silicon film 79 are diffused to a portion directly above the collector 31 above the base region 17. Thereby, an emitter diffusion layer 62 is formed in the portion (see FIG. 14).
[0011]
Next, a resist pattern corresponding to the shape of the emitter electrode 91A and the shape of the upper electrode 77 (and the insulating film 78a) of the IPO capacitor C is formed on the polycrystalline silicon film 79, and an etching process is performed. The portions other than the electrodes 91A and 77 of the polycrystalline silicon film 79 and the protective film 78 are removed. Thereby, as shown in FIG. 14, the emitter electrode 91A, the insulating film 78a of the IPO capacitor C, and the upper electrode 77 are formed, and the gate electrode 92A of the CMOS transistor M is exposed. In addition, at the outer edge of the emitter diffusion layer 62, a part 78b of the silicon oxide film formed as a protective layer remains between the emitter electrode 91A and the silicon oxide film 22.
[0012]
That is, in the manufacturing method (first method), after the formation process of the CMOS transistor M, the steps after the formation of the collector 31 of the bipolar transistor B (ion implantation by the SIC method) are performed. Is protected by a protective film 78 made of silicon oxide, and this protective film 78 is used as the insulating film 78a of the IPO capacitor C.
[0013]
Japanese Patent Application Laid-Open No. 13-203287 describes that a protective film is used as an insulating film of a capacitor in a manufacturing process of a BiCMOS circuit including a capacitor, as in the above method.
However, in the method described in this publication (second method), the formation of the gate electrode is performed in a state where the formation region of the bipolar transistor is protected by a protective film (for example, a silicon nitride film having a thickness of 30 nm by a low pressure CVD method). Side walls are formed. The capacitor is not an IPO capacitor but a gate capacitor using an N well of a silicon substrate as a lower electrode.
[0014]
[Problems to be solved by the invention]
In the first method, the silicon oxide film formed by the low pressure CVD method is used as the insulating layer of the IPO capacitor. As the insulating layer is thinner, the capacitance of the capacitor increases. However, if the silicon oxide film formed by the low pressure CVD method is thin, the insulation resistance decreases. Therefore, in the first method, a relatively thick silicon oxide film is formed. In the first method, since the silicon oxide film formed as the protective film of the CMOS transistor is used as the insulating layer of the IPO capacitor, it is necessary to form a relatively thick silicon oxide film.
[0015]
On the other hand, in an IPO capacitor having a silicon oxide film formed by heat-treating the surface of the polycrystalline silicon film forming the lower electrode at a temperature of 950 to 1100 ° C. as an insulating layer, the insulating layer obtained by the heat treatment has a thickness. Even if it is thin, it has excellent insulation resistance, so that it is excellent in both capacity and insulation resistance.
However, in the first method, in order to form such a thermal oxide film as an insulating layer of the IPO capacitor, for example, after forming the lower electrode of the IPO capacitor together with the gate electrode of the CMOS transistor, After a relatively thick silicon oxide film as a protective film is formed by the low pressure CVD method (before the resist pattern is formed in FIG. 15), a portion of the silicon oxide film existing on the lower electrode of the IPO capacitor It is necessary to thermally oxidize the polycrystalline silicon film forming the lower electrode. In addition to the thermal oxidation treatment, it is necessary to perform a heat treatment for emitter diffusion.
[0016]
As described above, in the first method, if the insulating layer of the IPO capacitor is formed by thermal oxidation of the polycrystalline silicon film forming the lower electrode, the number of manufacturing steps is significantly increased.
The present invention pays attention to such problems of the prior art, and in a method of manufacturing a semiconductor device in which at least an IPO capacitor and a bipolar transistor are formed on one substrate, a thermal oxide film of a polycrystalline silicon film forming a lower electrode An object of the present invention is to provide a method capable of reducing the number of manufacturing steps while forming an IPO capacitor having an insulating layer as an insulating layer.
[0017]
[Means for Solving the Problems]
  In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device in which a capacitor and a bipolar transistor are formed on a single substrate, wherein a base of the bipolar transistor is formed and an emitter region of the base is exposed. Forming a polycrystalline silicon film on the substrate, adding an impurity to the polycrystalline silicon film, forming an oxide film on the surface of the polycrystalline silicon film after the addition of impurities, and forming an impurity in the emitter region A step of forming a capacitor upper region in the capacitor formation region on the oxide film, a step of removing portions other than the capacitor formation region of the oxide film, and the polycrystalline silicon after the heat treatment Forming an emitter electrode of the bipolar transistor and a lower electrode of the capacitor from the film.The heat treatment step is performed at a temperature of 950 ° C. or higher and 1100 ° C. or lower for a predetermined time in an oxygen atmosphere and then in an inert gas atmosphere, and thermal oxidation in the oxygen atmosphere is performed with an oxidation having a required thickness. Until the film is formed, heat treatment in an inert gas atmosphere is performed until the emitter region reaches an optimum diffusion state.A method for manufacturing a semiconductor device is provided.
[0018]
  The present invention also provides a method of manufacturing a semiconductor device in which a capacitor, a bipolar transistor, and a MOS field effect transistor are formed on a single substrate, wherein a gate oxide film of the MOS field effect transistor is formed, and a base of the bipolar transistor is formed. A step of forming a polycrystalline silicon film on the substrate with the emitter region of the base exposed, a step of adding an impurity to the polycrystalline silicon film, and a surface of the polycrystalline silicon film after the addition of the impurity A heat treatment step of forming an oxide film and diffusing impurities in the emitter region, a step of forming an upper electrode of the capacitor in the capacitor formation region on the oxide film, and a portion of the oxide film other than the capacitor formation region are removed From the polycrystalline silicon film after the heat treatment and the heat treatment of the bipolar transistor. Comprising: a heater electrode, and the lower electrode of the capacitor, a step of a gate electrode is formed simultaneously with MOS field-effect transistor, theThe heat treatment step is performed at a temperature of 950 ° C. or higher and 1100 ° C. or lower for a predetermined time in an oxygen atmosphere and then in an inert gas atmosphere, and thermal oxidation in the oxygen atmosphere is performed with an oxidation having a required thickness. Until the film is formed, heat treatment in an inert gas atmosphere is performed until the emitter region reaches an optimum diffusion state.A method for manufacturing a semiconductor device is provided.
[0019]
  The present invention also provides a method for manufacturing a semiconductor device in which a capacitor, a bipolar transistor, a MOS field effect transistor, and a resistance element are formed on a single substrate, wherein the gate oxide film of the MOS field effect transistor is formed, and the base of the bipolar transistor is A step of forming a polycrystalline silicon film on the substrate formed and exposing the emitter region of the base; a step of adding an impurity to the polycrystalline silicon film; and the polycrystalline silicon film after the addition of the impurity A heat treatment step of forming an oxide film on the surface of the substrate and diffusing impurities in the emitter region; a step of forming an upper electrode of the capacitor in the capacitor formation region on the oxide film; and a portion of the oxide film other than the capacitor formation region Removing the bipolar transistor from the heat-treated polycrystalline silicon film. Comprising data and emitter electrodes of the lower electrode of the capacitor, and the gate electrode of the MOS field-effect transistor, and forming a resistive element at the same time, theThe heat treatment step is performed at a temperature of 950 ° C. or higher and 1100 ° C. or lower for a predetermined time in an oxygen atmosphere and then in an inert gas atmosphere, and thermal oxidation in the oxygen atmosphere is performed with an oxidation having a required thickness. Until the film is formed, heat treatment in an inert gas atmosphere is performed until the emitter region reaches an optimum diffusion state.A method for manufacturing a semiconductor device is provided.
[0020]
  In the method of the present invention, the heat treatment stepThe heat treatment time in is a time including a treatment time in an oxygen atmosphere and an inert gas atmosphere, and is 10 seconds or more and 180 seconds or less.Is preferable.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
FIGS. 1-13 is a figure which shows the partial cross section of the wafer in each process of the method equivalent to one Embodiment of this invention.
As shown in FIG. 1, first, a buried N region is buried in the bipolar transistor region on the silicon substrate 1 after surface oxidation.⁺A layer 11 and an N-well 12 thereon are formed.
[0022]
Embedded N⁺The layer 11 can be formed by the following method, for example. First, acceleration energy 70 KeV, dose amount 2.0 × 10¹⁴cm^-2Arsenic ions (As⁺Then, annealing is performed at 1100 ° C. for 20 minutes, and P-type silicon having a resistivity of about 10 Ωcm is epitaxially grown on the upper portion with a thickness of about 1.5 μm.
[0023]
The N well 12 has, for example, an acceleration energy of 320 KeV and a dose amount of 6.0 × 10.¹²cm^-2Phosphorus ion (P⁺) Is implanted and then annealed at 1100 ° C. for 120 minutes.
Next, by the LOCOS method, the thin silicon oxide film 13 is left in the element formation region, and a thick (300 nm thick) silicon oxide film (element isolation oxide film) 14 is formed in the element isolation region.
[0024]
Next, a P well 15 is formed in the NMOS formation region, and an N well is formed in the PMOS formation region (not shown). For example, the N well has an acceleration energy of 320 KeV and a dose of 1.0 × 10.¹³cm^-2Phosphorus ion (P⁺) Can be formed by ion implantation. The P well 15 for forming the NMOS has, for example, an acceleration energy of 200 KeV and a dose of 1.0 × 10.¹³cm^-2Boron ions (B⁺) Can be formed by ion implantation.
[0025]
Next, ion implantation for adjusting Vth (threshold voltage) is performed in the channel formation region of the P well 15 of the NMOS transistor (and the channel formation region of the N well of the PMOS transistor not shown). Thereby, the Vth adjustment region 16 is formed. This ion implantation is performed under conditions according to the set value of Vth. As the implanted ions, for example, boron difluoride ions (BF₂ ⁺) Can be used. The ion implantation conditions are, for example, acceleration energy of 40 KeV, and the dose amount is 5.0 × 10 in the case of NMOS.¹²cm^-2About 1.5 × 10 for PMOS¹³cm^-2To the extent.
[0026]
Next, ion implantation is performed on the base formation region 12 a of the N well 12 through the thin silicon oxide film 13. This ion implantation is performed by, for example, boron difluoride ions (BF₂ ⁺), Acceleration energy 50 KeV, dose amount 5.0 × 10¹³cm^-2Can be performed under the following conditions. The ions implanted in the base formation region 12a of the N well 12 are diffused and activated in the base formation region 12a by heat treatment performed in the following steps. Thereby, the base region 17 is formed (see FIG. 2).
[0027]
Next, after removing the thin silicon oxide film 13 existing on the Vth adjustment region 16 of the MOS transistor and the base formation region 12a of the bipolar transistor, silicon oxide films 21 and 22 are formed on both portions as shown in FIG. Form. The silicon oxide films 21 and 22 are formed with a thickness of about 6.5 nm, for example, by wet oxidation under conditions of a temperature of 850 ° C. and a water vapor atmosphere. The silicon oxide film 21 on the Vth adjustment region 16 is formed as a gate oxide film.
[0028]
Next, a first polycrystalline silicon thin film 23 is formed on the wafer in this state to a thickness of 100 nm by low pressure CVD using, for example, silane as a raw material. Next, as shown in FIG. 2, a resist pattern 25 having an opening 25a corresponding to the emitter region of the bipolar transistor is formed by a photolithography process, and then a first etching process using chlorine-based plasma is performed. The portion immediately below the opening 25a of the polycrystalline silicon thin film 23 is removed. As a result, an opening 23 a corresponding to the emitter region is formed in the first polycrystalline silicon thin film 23. This etching step is performed so that the silicon oxide film 22 formed below the first polycrystalline silicon thin film 23 is not removed.
[0029]
Next, using the resist pattern 25 as a mask, phosphorus ions enter the N well 12 from the opening 25a of the resist pattern 25 and the opening 23a of the first polycrystalline silicon thin film 23 through the silicon oxide film 22 and the base region 17. (P⁺) Is ion-implanted by the SIC method. This ion implantation is, for example, an acceleration energy of 320 KeV and a dose amount of 6.0 × 10.¹²cm^-2Can be performed under the following conditions. As a result, as shown in FIG. 3, a collector 31 is formed in the N well 12 that is directly below the emitter region.
[0030]
Next, after removing the resist pattern 25 from the wafer in the state of FIG. 3, the silicon oxide film 22 immediately below the opening 23a is etched using the first polycrystalline silicon thin film 23 having the opening 23a as a mask. The upper surface 17b of the emitter region of the base region 17 is exposed. This etching is performed by, for example, HF and NH._FourIt can be performed by a wet etching method using an etching solution containing F as a main component. As a result, the gate oxide film 21 of the CMOS field effect transistor is formed, the base 17 of the bipolar transistor is formed, and the emitter region of this base is exposed.
[0031]
Then, the second polycrystalline silicon film 41 is formed on the wafer in this state with a thickness of 250 nm by low pressure CVD using, for example, silane as a raw material. FIG. 4 shows this state. As a result, the second polycrystalline silicon film 41 is formed on the exposed surface 17 b of the base region 17, on the first polycrystalline silicon film 23, and on the wall surface of the opening 23 a of the first polycrystalline silicon film 23. It is formed.
[0032]
In this state, as shown in FIG. 5, arsenic ions (As⁺) Is ion-implanted. This ion implantation is performed under the condition that the emitter diffusion of the bipolar transistor is optimized. Therefore, for example, acceleration energy 40 KeV, dose amount 1.0 × 10¹⁶cm^-2Perform under the conditions of
Next, by performing the following heat treatment, a thermal oxide film 61 is formed on the surface of the second polycrystalline silicon film 41 and an emitter diffusion layer 62 is formed in the emitter region of the base 17 as shown in FIG. To do.
[0033]
This heat treatment is performed using, for example, an RTP (rapid thermal processor) apparatus at a temperature of 1050 ° C. and a processing time of 29 seconds. The first 25 seconds are performed in an oxygen atmosphere by introducing only oxygen into the chamber at a flow rate of 5 slpm (standard liter per minute). After the passage of 25 seconds, the introduction of oxygen into the chamber is stopped, and at the same time, the introduction of nitrogen at a flow rate of 5 slpm is started, and a heat treatment is performed in a nitrogen atmosphere for 4 seconds.
[0034]
Here, in the case of the second polycrystalline silicon film 41 in which ions are implanted under the above-described conditions, in the case where the heat treatment conditions are a temperature of 1050 ° C. and a 100% oxygen atmosphere, a treatment time of 25 seconds is required to form a 15 nm thermal oxide film. Need. Also, arsenic ions (As that have been ion-implanted into the second polycrystalline silicon film 41).⁺) Is diffused into the emitter region of the base 17 to obtain an optimum diffusion state, the heat treatment at a temperature of 1050 ° C. requires a treatment time of, for example, 29 seconds.
[0035]
Therefore, the heat treatment time is set to a time necessary for obtaining the optimum diffusion state of the emitter region, and the time for performing the thermal oxidation in the oxygen atmosphere in the heat treatment time is the heat formed on the second polycrystalline silicon film 41. By determining the thickness according to the thickness of the oxide film 61, the formation of the thermal oxide film 61 having a predetermined thickness and the formation of the emitter diffusion layer 62 in the optimum diffusion state can be performed in one heat treatment step.
[0036]
Next, as shown in FIG. 7, a third polycrystalline silicon film 71 is formed on the thermal oxide film 61. The third polycrystalline silicon film 71 is formed with a thickness of 250 nm by, for example, a low pressure CVD method using silane as a raw material at a temperature of 640 ° C. Next, phosphorus ions (P⁺) Is ion-implanted. This ion implantation is, for example, an acceleration energy of 50 KeV and a dose amount of 7.0 × 10.¹⁵cm^-2Perform under the conditions of
[0037]
Next, a photolithography process and an etching process are performed on the third polycrystalline silicon film 71 to leave only a portion of the third polycrystalline silicon film 71 as an IPO capacitor, so that the IPO is formed on the thermal oxide film 61. An upper electrode 71a of the capacitor is formed. FIG. 8 shows this state. The ion implantation performed in FIG. 7 is performed to make the upper electrode 71a of the IPO capacitor N-type.
[0038]
In this state, as shown in FIG. 9, after forming a resist pattern 75 that protects only the bipolar transistor formation region by a photolithography process, phosphorus ions are applied to the second polycrystalline silicon film 41 using the resist pattern 75 as a mask. (P⁺) Is ion-implanted. This ion implantation is performed, for example, with an acceleration energy of 20 KeV and a dose of 1.0 × 10.¹⁶cm^-2Perform under the conditions of
[0039]
The purpose of this ion implantation is to adjust the electrical characteristics of the gate electrode of the resistance element formed by patterning the second polycrystalline silicon film 41 (and the first polycrystalline silicon film 23) and the CMOS transistor. It is in. That is, arsenic ions (As) are formed on the second polycrystalline silicon film 41 in the step shown in FIG.⁺) Is ion-implanted, and this ion implantation is performed under the condition that the emitter diffusion of the bipolar transistor is optimized. Under these ion implantation conditions, since the amount of ion implantation into the resistance element and the gate electrode is insufficient, phosphorus ions (P⁺) Injection. At this time, since the emitter region of the bipolar transistor has already been optimized, the bipolar transistor region is protected by the resist pattern 75.
[0040]
Next, by etching the thermal oxide film 61 using the upper electrode 71a as a mask, only the lower portion 61a of the upper electrode 71a of the thermal oxide film 61 is left as an insulating film of the IPO capacitor as shown in FIG. Remove other parts. This etching step may be performed by a dry etching method using fluorine-based plasma or a wet etching method using a hydrogen fluoride (HF) chemical solution.
[0041]
Next, on the wafer in the state of FIG. 10, as shown in FIG. 11, a pattern 81 corresponding to the shape of the emitter electrode of the bipolar transistor, a pattern 82 corresponding to the shape of the gate electrode of the CMOS transistor, and IPO A resist pattern including a pattern 83 corresponding to the shape of the lower electrode of the capacitor and a pattern 84 corresponding to the shape of the resistance element is formed.
[0042]
In this state, the second polycrystalline silicon film 41 and the first polycrystalline silicon film 23 are etched by a dry etching process using chlorine-based plasma using the resist pattern as a mask.
Thereby, as shown in FIG. 12, the emitter electrode 91 of the bipolar transistor, the gate electrode 92 of the CMOS transistor, the lower electrode 93 of the IPO capacitor, and the resistance element 94 are simultaneously formed. These electrodes and resistance elements have a two-layer structure of portions 23 b to 23 e made of the first polycrystalline silicon film 23 and portions 41 a to 41 d made of the second polycrystalline silicon film 41.
[0043]
In the emitter electrode 91, the portion 41 a made of the second polycrystalline silicon film is in contact with the emitter diffusion layer 62, and the portion 23 b made of the first polycrystalline silicon film 23 is on the outer edge of the emitter diffusion layer 62. 2 between the portion 41 a made of the polycrystalline silicon film and the silicon oxide film 22.
Next, the source / drain 96 of the CMOS transistor is formed by implanting ions into the source / drain region of the CMOS transistor. In the source / drain region of the PMOS transistor, for example, an acceleration energy of 60 KeV and a dose of 2.5 × 10¹⁵cm^-2Boron difluoride ion (BF₂ ⁺) Is ion-implanted. In the source / drain region of the NMOS transistor, for example, an acceleration energy of 60 KeV and a dose of 5.0 × 10¹⁵cm^-2Arsenic ions (As⁺) Is ion-implanted.
[0044]
The boron difluoride ion (BF₂ ⁺The external base may be formed outside the emitter diffusion layer 62 by performing ion implantation on the base 17 of the bipolar transistor simultaneously with the source / drain region of the PMOS transistor. Thereby, the contact resistance to the base region can be reduced. Further, after the ion implantation, for example, annealing is performed at a temperature of 950 ° C. for 2 minutes, whereby the implanted ions can be activated.
[0045]
Next, as shown in FIG. 13, after an interlayer insulating film 97 is formed on the entire surface of the wafer, the surface is planarized by CMP. Next, contact holes for wiring to the respective elements are formed at predetermined positions of the interlayer insulating film 97, tungsten plugs 98 are formed in the respective contact holes, and a wiring layer 99 made of an aluminum alloy is formed thereon.
[0046]
Thus, a semiconductor device in which the IPO capacitor C, the bipolar transistor B, the CMOS transistor M, and the resistance element R are formed on one substrate is obtained. The insulating film 61a of the IPO capacitor C is a thermal oxide film formed by thermal oxidation of the lower electrode.
As a performance of the semiconductor device obtained by this method, in the bipolar transistor B, V_CECutoff frequency (Ft) when the (collector-emitter voltage) is 2 V = about 20 GHz, BV_CEO(The breakdown voltage between the collector and the emitter in the base open state) = 3.3 V and the current amplification factor = 60 were obtained.
[0047]
The CMOS transistor C is an NMOS transistor with W (gate width) = 15 μm and L (gate length) = 0.35 μm, and V_th= 0.65 V, Vd (drain voltage) = Vg (gate voltage) = 3.3 V, a saturation current value = 7.3 mA was obtained. A PMOS transistor with W = 15 μm and L = 0.35 μm._thIn the case of = −0.83 V and Vd = Vg = −3.3 V, a saturation current value = 3.6 mA was obtained.
[0048]
For IPO capacitor C, capacitance = 2.2 F / μm², Area 14000μm²In this case, a voltage of 14 V at a current leakage of 1 μA and a breakdown voltage of about 18 V (that is, a breakdown electric field strength of 12 MV / cm) were obtained.
In the capacitive element R, a sheet resistance value of 68Ω / square was obtained.
As described above, in the method of this embodiment, the IPO capacitor C, the bipolar transistor B, the CMOS transistor M, and the resistance element R are formed on one substrate, and the insulating layer of the IPO capacitor is formed on the lower electrode. Although the polycrystalline silicon film is formed by thermal oxidation, the thermal oxidation and emitter diffusion are simultaneously performed in one thermal oxidation process. Further, from the third polycrystalline silicon film 41 (and the second polycrystalline silicon film 23) after the heat treatment, the emitter electrode 91 of the bipolar transistor B, the gate electrode 92 of the CMOS transistor M, and the lower electrode of the IPO capacitor C 93 and the resistance element 94 are formed simultaneously.
[0049]
Therefore, according to the method of this embodiment, the first method described in the prior art is compared with the case where the insulating layer of the IPO capacitor is formed by thermal oxidation of the polycrystalline silicon film forming the lower electrode. Thus, the number of manufacturing steps can be reduced.
[0050]
【The invention's effect】
As described above, according to the method of the present invention, in the method of manufacturing a semiconductor device in which at least the IPO capacitor and the bipolar transistor are formed on one substrate, the thermal oxide film of the polycrystalline silicon film forming the lower electrode is formed. The number of manufacturing steps can be reduced while forming an IPO capacitor as an insulating layer.
[Brief description of the drawings]
FIG. 1 is a diagram showing a partial cross section of a wafer in each step of a method corresponding to an embodiment of the present invention.
FIG. 2 is a view showing a partial cross section of a wafer in each step of a method corresponding to an embodiment of the present invention.
FIG. 3 is a view showing a partial cross section of a wafer in each step of a method corresponding to one embodiment of the present invention.
FIG. 4 is a view showing a partial cross section of a wafer in each step of a method corresponding to an embodiment of the present invention.
FIG. 5 is a view showing a partial cross section of a wafer in each step of a method corresponding to one embodiment of the present invention.
FIG. 6 is a diagram showing a partial cross section of a wafer in each step of a method corresponding to an embodiment of the present invention.
FIG. 7 is a view showing a partial cross section of a wafer in each step of a method corresponding to one embodiment of the present invention.
FIG. 8 is a view showing a partial cross section of a wafer in each step of a method corresponding to one embodiment of the present invention.
FIG. 9 is a view showing a partial cross section of a wafer in each step of a method corresponding to one embodiment of the present invention.
FIG. 10 is a view showing a partial cross section of a wafer in each step of a method corresponding to one embodiment of the present invention.
FIG. 11 is a view showing a partial cross section of a wafer in each step of a method corresponding to one embodiment of the present invention.
FIG. 12 is a view showing a partial cross section of a wafer in each step of a method corresponding to one embodiment of the present invention.
FIG. 13 is a cross-sectional view showing a semiconductor device (a semiconductor device in which an IPO capacitor, a bipolar transistor, a CMOS transistor, and a resistance element are formed on one substrate) obtained by the method of one embodiment of the present invention. FIG.
FIG. 14 is a cross-sectional view showing a conventional example of a semiconductor device in which an IPO capacitor, a bipolar transistor, and a CMOS transistor are formed on one substrate.
15 is a view showing a partial cross section of a wafer in each step of the method for manufacturing the semiconductor device of FIG. 14;
16 is a view showing a partial cross section of a wafer in each step of the method for manufacturing the semiconductor device of FIG. 14;
[Explanation of symbols]
1 Silicon substrate
11 Embedded N⁺layer
12 N-well
13 Thin silicon oxide film
14 Device isolation oxide film
15 P well
16 Vth adjustment area
12a Base formation region
17 Base area
21 Gate oxide film (silicon oxide film)
22 Silicon oxide film
23 First polycrystalline silicon thin film
23b to 23e Part made of the first polycrystalline silicon film
25 resist pattern
25a Resist pattern opening
23a Opening of first polycrystalline silicon thin film
31 Collector
41 Second polycrystalline silicon film
41a to 41d Part made of second polycrystalline silicon film
61 Thermal oxide film
62 Emitter diffusion layer
71 Third polycrystalline silicon film
71a Upper electrode of IPO capacitor
75 resist pattern
78 Protective film
78a Insulating film of IPO capacitor
81 Pattern corresponding to the shape of the emitter electrode
83 Pattern corresponding to the shape of the gate electrode
83 Pattern corresponding to the shape of the lower electrode
84 Pattern corresponding to the shape of the resistive element
91 Emitter electrode of bipolar transistor
92 Gate electrode of CMOS transistor
93 Lower electrode of IPO capacitor
94 Resistance element
96 Source / drain of CMOS transistor
97 Interlayer insulation film
98 Tungsten plug
99 Wiring layer
C IPO capacitor
B Bipolar transistor
M CMOS transistor
R resistance element

Claims (4)

In a method for manufacturing a semiconductor device in which a capacitor and a bipolar transistor are formed on one substrate,
Forming a polycrystalline silicon film on a substrate in which a base of a bipolar transistor is formed and an emitter region of the base is exposed;
Adding an impurity to the polycrystalline silicon film;
A heat treatment step of forming an oxide film on the surface of the polycrystalline silicon film after the impurity addition and diffusing the impurity in the emitter region;
Forming a capacitor upper electrode in the capacitor formation region on the oxide film;
Removing a portion other than the capacitor formation region of the oxide film;
Forming a bipolar transistor emitter electrode and a capacitor lower electrode from the heat-treated polycrystalline silicon film;
Equipped with a,
The heat treatment step is performed at a temperature of 950 ° C. or higher and 1100 ° C. or lower and under an inert gas atmosphere after being performed in an oxygen atmosphere for a predetermined time,
Perform thermal oxidation in an oxygen atmosphere until an oxide film with the required thickness is formed,
A method for manufacturing a semiconductor device, comprising performing heat treatment in an inert gas atmosphere until an emitter region is in an optimum diffusion state . In a manufacturing method of a semiconductor device in which a capacitor, a bipolar transistor, and a MOS field effect transistor are formed on one substrate,
Forming a polysilicon film on a substrate in which a gate oxide film of a MOS field effect transistor is formed, a base of a bipolar transistor is formed, and an emitter region of the base is exposed;
Adding an impurity to the polycrystalline silicon film;
A heat treatment step of forming an oxide film on the surface of the polycrystalline silicon film after the impurity addition and diffusing the impurity in the emitter region;
Forming a capacitor upper electrode in the capacitor formation region on the oxide film;
Removing a portion other than the capacitor formation region of the oxide film;
Forming simultaneously the emitter electrode of the bipolar transistor, the lower electrode of the capacitor, and the gate electrode of the MOS field effect transistor from the polycrystalline silicon film after the heat treatment;
Equipped with a,
The heat treatment step is performed at a temperature of 950 ° C. or higher and 1100 ° C. or lower and under an inert gas atmosphere after being performed in an oxygen atmosphere for a predetermined time,
Perform thermal oxidation in an oxygen atmosphere until an oxide film with the required thickness is formed,
A method for manufacturing a semiconductor device, comprising performing heat treatment in an inert gas atmosphere until an emitter region is in an optimum diffusion state . In a method for manufacturing a semiconductor device in which a capacitor, a bipolar transistor, a MOS field effect transistor, and a resistance element are formed on one substrate,
Forming a polysilicon film on a substrate in which a gate oxide film of a MOS field effect transistor is formed, a base of a bipolar transistor is formed, and an emitter region of the base is exposed;
Adding an impurity to the polycrystalline silicon film;
A heat treatment step of forming an oxide film on the surface of the polycrystalline silicon film after the impurity addition and diffusing the impurity in the emitter region;
Forming a capacitor upper electrode in the capacitor formation region on the oxide film;
Removing a portion other than the capacitor formation region of the oxide film;
A step of simultaneously forming an emitter electrode of a bipolar transistor, a lower electrode of a capacitor, a gate electrode of a MOS field effect transistor, and a resistance element from the heat-treated polycrystalline silicon film;
Equipped with a,
The heat treatment step is performed at a temperature of 950 ° C. or higher and 1100 ° C. or lower and under an inert gas atmosphere after being performed in an oxygen atmosphere for a predetermined time,
Perform thermal oxidation in an oxygen atmosphere until an oxide film with the required thickness is formed,
A method for manufacturing a semiconductor device, comprising performing heat treatment in an inert gas atmosphere until an emitter region is in an optimum diffusion state . The heat treatment time in the heat treatment step is a time including a treatment time in an oxygen atmosphere and an inert gas atmosphere, and is 10 seconds or more and 180 seconds or less. The manufacturing method of the semiconductor device as described in 2 ..

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