JP3923693B2 - Clock duty correction circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock duty correction technique.
[0002]
[Prior art]
FIG. 13 shows a general clock duty correction circuit. Reference numeral 1 denotes a clock transmission unit, which includes an oscillator 2 that oscillates a voltage signal of a reference frequency, a variable reference voltage generation circuit 3 that generates a reference voltage to be input to a voltage comparator 4 described later, an output of the oscillator 2 and a variable reference voltage The voltage comparator 4 is supplied with the reference voltage output from the generation circuit 3 and the buffer 5 is supplied with the output of the voltage comparator 4 as input. Reference numeral 6 denotes a clock receiver, which includes a buffer 7 that receives the output of the buffer 5 and an output terminal 8 that outputs a clock output from the buffer 7 to a subsequent circuit.
[0003]
The voltage signal of the reference frequency oscillated from the oscillator 2 is compared with the reference voltage output from the variable reference voltage generating circuit 3 by the voltage comparator 4 and converted into a binary clock. The clock output from the voltage comparator 4 is output from the clock transmission unit 1 via the buffer 5. The clock output from the transmission unit 1 is received by the clock reception unit 6 via the buffer 7 and supplied from the output terminal 8 to the subsequent circuit.
At this time, the clock supplied to the subsequent circuit includes distortion in the oscillator, voltage offset, delay time from the high level to the low level of the signal in the transmission / reception buffer, the difference in delay time from the low level to the high level, and the transmission path. The duty ratio fluctuates due to the influence of distortion or the like. If the duty of the clock supplied to the post-stage circuit fluctuates beyond the allowable range, the normal operation of the post-stage circuit is affected. Therefore, the clock output from the buffer 7 in the clock receiver 6 is observed with an oscilloscope or the like. The clock duty ratio is corrected by adjusting the reference voltage output from the variable reference voltage generating circuit 3. This is shown in FIG. As shown in FIG. 14, the duty of the clock output from the voltage comparator 4 is adjusted by adjusting the magnitude of the reference voltage.
[0004]
[Problems to be solved by the invention]
In the clock duty correction circuit as described above, the reception clock output from the buffer in the clock reception unit 6 is observed with an oscilloscope, and the variable reference voltage generation circuit 3 is configured so that the duty of the reception clock becomes a predetermined value. The output reference voltage has to be adjusted, and the adjustment work has a problem that requires a large number of man-hours. Even if the clock duty is adjusted by the method described above, the duty is affected by the effects of temperature drift of oscillators, transmission / reception buffers, etc., fluctuations in power supply voltage, signal distortion and delay fluctuations due to changes in peripheral conditions of the transmission line, etc. Variation occurs. Also, by adjusting the duty of the clock previously in the predicate solid way, shift duty due to aging, such as the variable reference voltage generating circuit 3, there is a problem that requires readjustment.
[0005]
As a method for automatically correcting the fluctuation of the duty of the reception clock, a difference value between the reception clock and the inverted clock obtained by inverting the reception clock is smoothed by a low-pass filter and fed back to the clock transmission unit. Japanese Patent Laid-Open No. 5-252007 introduces a method for correcting the duty by adjusting the transmission clock so that the difference becomes zero.
However, with this method, if the high or low level voltage of the reception clock changes due to fluctuations in the power supply voltage, or if the reception clock waveform is distorted due to the peripheral conditions of the transmission path, the difference fed back to the clock transmission unit Since the value also fluctuates, the detection accuracy deteriorates, and the fluctuation of the duty of the reception clock cannot be corrected accurately.
[0006]
The present invention has been made to solve the above-described problems, and is intended to automatically detect and correct a variation in clock duty, and further causes variation and distortion in the clock waveform. Even in such a case, an object is to provide a duty correction circuit that accurately corrects the duty of a reception clock and supplies a good clock to a subsequent circuit.
[0007]
[Means for Solving the Problems]
The clock duty correction circuit according to the present invention compares a voltage signal oscillated from an oscillator with a reference voltage set between the maximum value and the minimum value of the amplitude voltage of the voltage signal, and both high and low levels. A clock generation circuit for generating a clock having a low-pass filter for smoothing the clock output from the clock generation circuit, and high-level and low-level voltages of the clock are sampled and held for each cycle of the clock A sample hold circuit that outputs a voltage, a voltage average circuit that outputs an average value or a weighted average value of the voltages output from the sample hold circuit, and compares the output voltage of the voltage average circuit with the output voltage of the low-pass filter A voltage comparator that outputs a voltage signal representing a magnitude relationship between the two voltages, and the voltage comparator A counter that changes the count value based on the output; and a D / A converter that converts the count value of the counter into a voltage, and adjusts the reference voltage based on the output of the D / A converter. Thus, the duty of the clock is corrected.
[0008]
In the clock duty correction circuit according to the present invention , the voltage signal representing the magnitude relationship between the output voltage of the voltage averaging circuit output from the voltage comparator and the output voltage of the low-pass filter is a binary voltage signal.
[00 09 ]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.
Embodiment 1 FIG.
FIG. 1 shows a clock duty correction circuit according to the first embodiment of the present invention. In the figure, 1 is a clock transmission unit, 2 is an oscillator that oscillates a voltage signal of a reference frequency, 4 is a voltage comparison using an output of the oscillator 1 and a reference voltage output from an upper / lower limit circuit 18 described later as inputs. The comparator 5 is constituted by a buffer that receives the output of the voltage comparator 4 as an input. Reference numeral 6 denotes a clock receiving unit, 7 is a buffer that receives the output of the buffer 5, 8 is an output terminal that outputs a clock that is the output of the buffer 7 to a subsequent circuit, and 9 is a delay that delays the output of the buffer 7. Circuit 10 is a driver that receives the output of delay circuit 9, 11 is a first sample hold circuit that receives the output of buffer 7 and the non-inverted output of driver 10, and 12 is the output of buffer 7 and the inverse of driver 10. A second sample-and-hold circuit that receives the output, 13 and 14 are resistors that add the outputs of the first and second sample-and-hold circuits, and 15 is a low-pass filter that receives the output of the buffer 7. Reference numeral 16 denotes a voltage comparator that receives the output of the resistors 13 and 14 and the output of the low-pass filter 15. Reference numeral 17 denotes an integration circuit that receives the output of the voltage comparator 16. 18 is a lower limit circuit over which receives the output of the integrating circuit 17.
[00 10 ]
The voltage signal of the reference frequency oscillated by the oscillator 2 is compared with a reference voltage output from an upper / lower limit circuit 18 described later by the voltage comparator 4 and converted into a binary clock. The clock output from the voltage comparator 4 is output from the clock transmission unit 1 via the buffer 5. The clock output from the transmitter 1 is received by the clock receiver 6 via the buffer 7 and supplied from the output terminal 8 to the subsequent circuit. The delay circuit 9 has a reception clock output from the buffer 7 sufficiently longer than a hold setup time in a first sample hold circuit 11 and a second sample hold circuit 12 described later and sufficiently shorter than a high level period or a low level period of the clock. Delay time. The delayed clock output from the delay circuit 9 is input to the driver 10, and the driver 10 outputs an inverted output and a ratio inverted output of the delayed clock, respectively. The first sample hold circuit 11 and the second sample hold circuit 12 hold the voltage level of the reception clock at the rising timing of the inverted output and the non-inverted output of the delayed clock output from the driver 10, respectively. This is shown in FIG. As a result, the high level voltage and the low level voltage of the reception clock are output from the first sample hold circuit and the second sample hold circuit, respectively.
[00 11 ]
The high-level and low-level holding voltages of the clocks output from the first sample hold circuit and the second sample hold circuit are added by the resistors 13 and 14, and an average or weighted average of both voltages ( (Hereinafter referred to as the average voltage) is input to the voltage comparator 16. Here, the weighted average of the high level voltage and the low level voltage of the clock is performed based on the duty defined in the subsequent circuit. For example, the resistors 13 and 14 are set so that the weighted average value is output to the high level voltage side when the clock duty specified by the subsequent circuit is larger than 50%, and when the clock duty is smaller than 50%. adjust.
From the low-pass filter 15, a voltage obtained by smoothing the reception clock output from the buffer 7 (hereinafter referred to as a smoothed voltage) is input to the voltage comparator 16. The voltage comparator 16 compares the average voltage with the smoothed voltage. If the smoothed voltage is higher than the average voltage, that is, if the high level period of the reception clock is longer than a predetermined value, the voltage comparator 16 outputs an H level voltage. When the smoothing voltage is lower than the voltage, that is, when the high level period of the reception clock is shorter than the predetermined value, the L level voltage is output.
[00 12 ]
With the above operation, when the high level period of the reception clock is longer than a predetermined value, the H level voltage is input from the voltage comparator 16 to the integration circuit 17, and the reference voltage output from the integration circuit 17 increases. Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high level period of the clock is shortened. When the high level period of the reception clock is shorter than a predetermined value, an L level voltage is input from the voltage comparator 16 to the integrating circuit 17, and the reference voltage output from the integrating circuit 17 decreases. Thereby, as shown in FIG. 3, the reference voltage is guided toward c, and the duty is corrected so that the high level period of the clock becomes longer. The upper / lower limit circuit 18 limits the range of the reference voltage set based on the output of the integration circuit 17 so that the clock is continuously output.
As described above, according to the first embodiment, the average voltage of the high level and low level voltages of the reception clock is compared with the smoothing voltage of the reception clock, and the reference voltage is adjusted based on the magnitude relationship thereof. Since the average voltage follows the level fluctuation even when the clock voltage has a level fluctuation, the duty fluctuation can be accurately detected and corrected.
[00 13 ]
Embodiment 2. FIG.
FIG. 4 shows a clock duty correction circuit according to the second embodiment of the present invention. In the figure, 19 is an initial value input to an up / down counter 20 to be described later, 20 is an up / down counter that receives the output of the buffer 5, the output of the voltage comparator 16, and the initial value 19 and 21 is an up / down counter 20 This is a digital / analog converter to which the output is input.
[00 14 ]
An arbitrary initial value 19 is set in the up / down counter 20 at the same time when the power is turned on. When the output voltage of the voltage comparator 16 is at the H level, the up / down counter 20 adds a predetermined value, for example, 1 to the count value using the transmission clock output from the buffer 5 as a trigger, and the output of the voltage comparator 16 is L In the case of the level, a predetermined value, for example, 1 is subtracted from the count value using the transmission clock output from the buffer 5 as a trigger. The digital / analog converter 21 outputs the voltage obtained by converting the count value of the up / down counter 20 to an analog value to the voltage comparator 4 as a reference voltage. The voltage comparator 4 compares the reference voltage output from the digital / analog converter 21 with the voltage signal of the reference frequency oscillated by the oscillator 2 and converts it into a binary signal clock.
[00 15 ]
With the above operation, when the high level period of the reception clock output from the buffer 7 is longer than a predetermined value, the count value is incremented by 1 for each reception clock by the up / down counter 20 and output from the digital / analog converter 21. The reference voltage increases. Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high level period of the clock is shortened. When the high level period of the reception clock output from the buffer 7 is shorter than a predetermined value, the up / down counter 20 decrements the count value by 1 for each reception clock and outputs the reference voltage output from the digital / analog converter 21. As shown in FIG. 3, the reference voltage is led toward c, and the duty is corrected so that the H level period of the clock becomes longer.
[00 16 ]
Embodiment 3 FIG.
FIG. 5 shows a clock duty correction circuit according to the third embodiment of the present invention. In the figure, reference numeral 22 denotes a multi-output delay circuit which outputs a plurality of clocks whose phases are shifted by delaying the reception clock output from the buffer 7 by an arbitrary minute time, and 23 corresponds to a count value of an up / down counter 29 which will be described later. A selection circuit for selecting a clock having a phase shift output from the multi-delay output circuit 22, a first driver having the output of the buffer 7 as an input, and a second driver having an output of the selection circuit 23 as an input. The driver 26 is a first phase comparator that receives the non-inverted output of the first driver 24 and the inverted output of the second driver 25, and 27 is the inverted output of the first driver 24 and the second driver 25. A second phase comparator having a non-inverted output as an input, 28 is an initial value input to an up / down counter described later, 29 is an input of the first phase comparator and an initial value 28 It is the up-down counter, 30 is a charge pump that receives the output from the second phase comparator.
[00 17 ]
Hereinafter, the operation of the duty correction circuit shown in FIG. 5 will be described.
The reception clock output from the buffer 7 is input to the first driver 24 and the multi-output delay circuit 22. The first driver 7 inputs the non-inverted output and the inverted output of the received clock to the first phase comparator 26 and the second phase comparator 27, respectively. The multi-output delay circuit 22 delays the reception clock by an arbitrary minute time, and outputs a plurality of reception clocks whose phases are shifted. The selection circuit 23 selects the delay clock output from the multi-output delay circuit 22 according to the count value of an up / down counter 29 described later. The delayed clock selected by the selection circuit 23 is input to the second driver 25, and the second driver 25 outputs the inverted output and non-inverted output of the delayed clock to the first phase comparator 26 and the second output, respectively. Input to the phase comparator 27.
[00 18 ]
The first phase comparator 26 receives the non-inverted output of the received clock and the inverted output of the delayed clock selected by the selection circuit 23 via the first and second drivers 24 and 25, respectively. Here, as an example of the first and second phase comparators 26 and 27 described later, FIG. 6 shows a general configuration of a phase comparator that responds to the rise of a pulse. Further, when the non-inverted output of the reception clock output from the first driver 24 and the inverted output of the delayed clock output from the second driver 25 are fp1 and fr1, respectively, the phase difference signals Pu1 and Pd1 are input. An example of the output timing is shown in FIG. According to the phase comparator shown in FIG. 6, the first phase comparator detects the rising phase difference of the delayed clock fr1 with respect to the non-inverted output fp1 of the received clock, as shown in FIG. Are output respectively as signals Pu1 and Pd1. These phase difference signals Pu 1 and Pd 1 output from the first phase comparator are input to the up / down counter 29.
[00 19 ]
An arbitrary initial value 28 is input to the up / down counter 29 at the same time as the power is turned on, and the count value is incremented by one using the clock as a trigger based on the phase difference signals Pu1 and Pd1 input from the first phase comparator 26. Or subtract. The count value of the up / down counter 29 is input to the selection circuit 23, and the selection circuit 23 generates a delay clock that reduces the phase difference detected by the first phase comparator 26 according to the count value. Select from 22 outputs. With the above operation, the rising of the reception clock input to the first phase comparator 26 and the signal obtained by inverting the reception clock are substantially the same. That is, the selection circuit 23 selects and outputs a delay clock whose falling edge coincides with the rising edge of the reception clock among the outputs of the multi-output delay circuit 23.
[00 20 ]
The second phase comparator 27 receives the inverted output of the received clock and the non-inverted output of the delayed clock selected by the selection circuit 23 via the first and second drivers 24 and 25, respectively. Due to the operation of the first phase comparator 26 described above, the falling edges of the two clock waveforms input to the first phase comparator 27 are substantially coincident. The second phase comparator determines the rising phase of the delay clock relative to the rising edge of the inverted output of the received clock, starting from the inverted output of the received clock and the falling edge of the delayed clock output from the first and second drivers 24 and 25. It detects and outputs a phase difference signal indicating the delay amount or the advance amount. Here, when the high level period of the reception clock is longer than the low level period, the rising edge of the inverted output of the reception clock output from the first driver 24 is the non-inverted output of the delayed clock output from the second driver 25. A phase difference signal indicating the amount of delay is output. In contrast, when the high level period of the reception clock is shorter than the low level period, the rising edge of the inverted output of the reception clock output from the first driver 24 is the non-inverted output of the delayed clock output from the second driver 25. A phase error signal representing the amount of advance is output.
[00 21 ]
These phase difference signals output from the second phase comparator 27 are input to the charge pump 30. The charge pump 30 outputs a positive-polarity pulse when these phase difference signals are delayed amounts, and outputs a negative-polarity pulse signal when they are advance amounts. FIG. 8 shows a configuration example of the charge pump 30. Further, the phase difference signals Pu2 and Pd2 and the charge when the inverted output of the reception clock output from the first driver 24 and the non-inverted output of the delayed clock output from the second driver 25 are fp2 and fr2, respectively. A timing chart of the control signal Pout output by the pump 30 is shown in FIG.
[00 22 ]
With the above operation, when the high level period of the reception clock output from the buffer 7 is longer than the low level period, a positive pulse is input from the charge pump to the integration circuit 17 and is output from the integration circuit 17 at this time. The reference voltage increases. Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high level period of the clock is shortened. When the high level period of the reception clock output from the buffer 7 is shorter than the low level period, a negative pulse is input to the integration circuit 17 from the charge pump. At this time, the reference voltage output from the integration circuit 17 is Descend. As a result, as shown in FIG. 3, the reference voltage is guided toward c, and the duty is corrected so that the high level period of the clock is shortened.
[00 23 ]
As described above, the clock duty correction circuit according to the third embodiment receives the received clock based on the phase difference between the rising edge of the delayed clock and the falling edge of the received clock that are delayed so that the falling edge coincides with the rising edge. Therefore, even when a distortion or the like occurs in the signal waveform of the reception clock, it is possible to accurately detect the duty variation and correct it.
Further, the variation in duty can be similarly detected and corrected based on the phase difference between the falling edge of the delayed clock obtained by delaying the receiving clock so that the rising edge coincides with the falling edge and the rising edge of the receiving clock.
[00 24 ]
Embodiment 4 FIG.
FIG. 10 shows a clock duty correction circuit according to the fourth embodiment of the present invention. In the figure, reference numerals 31 and 32 denote inverting circuits that receive the phase difference signal output from the second phase comparator, respectively, and 33 denotes an RS flip-flop that receives the phase difference signal inverted by the inverting circuits 31 and 32. It is. FIG. 11 shows the output of the RS flip-flop 33 to which the phase difference signals Pu2 and Pd2 output from the second phase comparator 27 and the outputs Pu2 ′ and Pd2 ′ obtained by inverting these signals by the inverting circuits 31 and 32 are input. It is a timing chart showing.
As shown in FIG. 11, the inverting circuits 31 and 32 invert the phase difference signals Pu2 and Pd2 output from the second phase comparator 27 and output them. The RS flip-flop 33 sets the RS flip-flop and outputs an H level voltage when the phase difference signal Pu2 is output, and resets the RS flip-flop and outputs an L level voltage when the phase difference signal Pd2 is output. .
[00 25 ]
As a result, when the phase difference signal Pu2 is output, that is, when the high level period of the reception clock output from the buffer 7 is longer than the low level period, an H level voltage is output from the RS flip-flop 33, and the integration circuit 17 The reference voltage output from is increased. Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high level period of the clock is shortened. When the phase error signal Pd2 is output, that is, when the high level period of the reception clock output from the buffer 7 is shorter than the low level period, an L level voltage is output from the RS flip-flop 33, and the integration circuit 17 The output reference voltage signal falls. As a result, as shown in FIG. 3, the reference voltage is guided toward c, and the duty is corrected so that the high level period of the clock is shortened.
[00 26 ]
Embodiment 5 FIG.
FIG. 12 shows a clock duty correction circuit according to the fifth embodiment of the present invention. In this figure, 34 is an initial value input to an up / down counter 35 to be described later, 35 is an initial value 34, and is set to a count value based on a phase difference signal output from the second phase comparator 27. An up / down counter for adding or subtracting a predetermined value, for example, 1.
[00 27 ]
An arbitrary initial value 34 is set in the up / down counter 35 at the same time when the power is turned on. The up / down counter 35 counts at the reception clock cycle when the phase difference signal Pu2 is input from the second phase comparator 27, that is, when the high level period of the reception clock output from the buffer 7 is longer than the low level period. When the phase difference signal Pd2 is input by one, that is, when the high level period of the reception clock output from the buffer 7 is shorter than the low level period, one is subtracted from the count value at the reception clock period. The digital / analog converter 21 outputs a voltage obtained by converting the count value of the up / down counter 35 into an analog quantity to the voltage comparator 4 as a reference voltage. The voltage comparator 4 compares the voltage signal of the reference frequency oscillated by the oscillator 2 with the reference voltage output from the digital / analog converter 21 and converts it into a binary signal clock.
[00 28 ]
With the above operation, when the high level period of the reception clock output from the buffer 7 is shorter than the low level period, the reference voltage output from the digital / analog converter 21 increases. Thereby, as shown in FIG. 3, the reference voltage is guided toward a, and the duty is corrected so that the high level period of the clock is shortened. When the high level period of the reception clock output from the buffer 7 is shorter than the low level period, the analog reference voltage output from the digital / analog converter 21 decreases. As a result, the reference voltage is guided in the direction c as shown in FIG. 3, and the duty is corrected so that the high level period of the clock is shortened.
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[00 29 ]
According to a first aspect of the present invention, there is provided a clock duty correction circuit comprising: a high level of a clock generated by comparing a voltage signal oscillated from an oscillator and a reference voltage set between a maximum value and a minimum value of the voltage signal; The reference voltage is adjusted based on a voltage signal representing the magnitude relationship between the average voltage of the two voltages obtained by adding the low level voltage or the weighted average voltage and the voltage obtained by smoothing the clock by the low-pass filter. Since the configuration is adopted, fluctuations in clock duty can be automatically corrected.
[00 30 ]
According to a second aspect of the present invention, there is provided the clock duty correction circuit according to the present invention, wherein an average voltage or a weighted average voltage of the two voltages obtained by adding the high level and low level voltages of the clock generated by the clock generator. Since the voltage signal representing the magnitude relationship between the voltages obtained by smoothing the clock using the low-pass filter is fed back to the clock generator as a binary voltage signal, fluctuations in the duty of the clock can be automatically corrected.
[00 31 ]
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a clock duty correction circuit according to a first embodiment of the present invention;
FIG. 2 is a diagram showing operations of first and second sample and hold circuits in the first embodiment of the present invention.
FIG. 3 is a diagram illustrating a clock duty correction method according to the first embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a clock duty correction circuit according to a second embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a clock duty correction circuit according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating a configuration example of first and second phase comparators according to a third embodiment of the present invention.
7 is a timing chart of first and second phase comparators in Embodiment 3 of the present invention. FIG.
FIG. 8 is a diagram illustrating a configuration example of a charge pump according to a third embodiment of the present invention.
FIG. 9 is a diagram showing a timing chart of the charge pump in the third embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of a clock duty correction circuit according to a fourth embodiment of the present invention.
FIG. 11 is a timing chart of an RS flip-flop according to Embodiment 4 of the present invention.
FIG. 12 is a block diagram showing a configuration of a clock duty correction circuit according to a fifth embodiment of the present invention.
FIG. 13 is a block diagram showing a conventional clock duty correction circuit;
FIG. 14 is a diagram illustrating a conventional clock duty correction method.
[Explanation of symbols]
2 Oscillator 3 Variable reference voltage generator 4 Voltage comparator 9 Delay circuit
11 first sample and hold circuit, 12 second sample and hold circuit,
13, 14 addition resistor, 15 low-pass filter, 16 voltage comparator,
17 integration circuit, 18 upper / lower limit circuit, 19 initial value,
20 up / down counter, 21 digital / analog converter,
22 multi-output delay circuit, 23 selection circuit, 24 first driver,
25 second driver, 26 first phase comparator,
27 second phase comparator, 28 initial value, 29 up / down counter,
30 charge pump, 31 inverting circuit, 32 inverting circuit,
33 RS flip-flop, 34 initial value,
35 Up / down counter.

Claims (2)

A clock generation circuit for generating a clock having both a high level and a low level by comparing a voltage signal oscillated from an oscillator and a reference voltage set between a maximum value and a minimum value of an amplitude voltage of the voltage signal A low-pass filter that smoothes the clock output from the clock generation circuit; a sample-and-hold circuit that outputs a voltage obtained by sampling and holding the high-level and low-level voltages of the clock every cycle of the clock; A voltage average circuit that outputs an average value or a weighted average value of the voltages output from the sample and hold circuit is compared with an output voltage of the voltage average circuit and an output voltage of the low-pass filter, and represents a magnitude relationship between the two voltages. A voltage comparator that outputs a voltage signal, and a counter that changes the count value based on the output of the voltage comparator. And a D / A converter that converts the count value of the counter into a voltage, and the duty of the clock is corrected by adjusting the reference voltage based on the output of the D / A converter. A clock duty correction circuit characterized by the above. 2. The clock duty correction circuit according to claim 1, wherein the voltage signal representing the magnitude relationship between the output voltage of the voltage averaging circuit output from the voltage comparator and the output voltage of the low-pass filter is a binary voltage signal. A clock duty correction circuit.

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