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JP3923733B2 - Sample preparation method for transmission electron microscope - Google Patents
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JP3923733B2 - Sample preparation method for transmission electron microscope - Google Patents

Sample preparation method for transmission electron microscope Download PDF

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Publication number
JP3923733B2
JP3923733B2 JP2001020495A JP2001020495A JP3923733B2 JP 3923733 B2 JP3923733 B2 JP 3923733B2 JP 2001020495 A JP2001020495 A JP 2001020495A JP 2001020495 A JP2001020495 A JP 2001020495A JP 3923733 B2 JP3923733 B2 JP 3923733B2
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Prior art keywords
ion beam
focused ion
acceleration voltage
sample
fib
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JP2002228562A (en
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直久 鈴木
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Toshiba Corp
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Toshiba Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/30Electron or ion beam tubes for processing objects
    • H01J2237/317Processing objects on a microscale
    • H01J2237/3174Etching microareas
    • H01J2237/31745Etching microareas for preparing specimen to be viewed in microscopes or analyzed in microanalysers

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  • Analysing Materials By The Use Of Radiation (AREA)
  • Sampling And Sample Adjustment (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は透過型電子顕微鏡の試料作成方法に係り、特に高度に微細化された半導体装置の製造工程の評価に適したフォーカスド・イオンビームを用いた透過型電子顕微鏡の試料作成方法に関するものである。
【0002】
【従来の技術】
従来の透過型電子顕微鏡(以下TEM; Transmission Electron Microscopyと呼ぶ)の試料作製方法には、フォーカスド・イオンビーム(以下FIB; Focused Ion Beamと呼ぶ)を用いて所望の試料を加工するものがある。
【0003】
はじめに、図5、図6を用いて、従来のFIBを用いたTEM試料の作製方法を、加工寸法が100nm以下の高度に微細化された半導体装置の製造工程評価に適用する場合に生じる第1の問題点について説明する。
【0004】
図5は、加工寸法が数100nm以上の、従来の半導体装置の製造工程評価に用いるTEM試料の作成方法を示す模式図である。例えば半導体基板上の絶縁膜101に、バリア層102を介して円形のコンタクトプラグ103を埋め込む工程をTEM観察により評価する場合について説明する。なお、この例は、必ずしも現実の半導体装置の部分構造を示すものではなく、従来の問題点を示すための模式図として示すものである。
【0005】
図5(a)は、評価対象とする部分構造の上面図である。バリア層102とコンタクトプラグ103によるコンタクトホール内部の埋め込み状態を評価するため、図5(a)に示すように、コンタクトホールの中心線に沿って垂直に、評価部分を厚さ約100nmの薄膜部にしてTEM観察の試料を作製し、この薄膜部を透過するTEM像を解析することにより評価を行う。
【0006】
薄膜部の垂直断面構造を図5(b)に示す。このように、評価対象とする部分構造の大きさが、薄膜部の厚さ100nmに比べて十分大きい場合には、図5
(b)に示す薄膜部の断面には、評価対象とする部分構造の断面が2次元パターンとして明示されるので、良好なTEM観察を行うことができる。
【0007】
近年半導体装置の微細加工技術が進展し、加工寸法100nm以下の高度に微細化された半導体装置の製造工程を的確に評価する方法としてTEM観察の重要性がますます高まっているが、このとき、TEM観察に用いる試料の薄膜部の厚さが従来の100nm程度の値に留まれば、良好なTEM観察を行うことが事実上不可能になる。
【0008】
次に、図6(a)、図6(b)を用いてこの問題を詳細に説明する。
【0009】
図6(a)に示す評価対象の部分構造の上面図は、図5(a)と同様に、半導体基板上の絶縁膜101と、バリア層102と、コンタクトプラグ103から構成される。しかし、製造工程の微細化が進められ、コンタクトホールの内径が100nm以下に微細化されていることが図5(a)と異なる(図6(a)では、コンタクトホールの内径が丁度100nmの場合が示されている)。
【0010】
このように微細化されたコンタクトホール内部の埋め込み状況や内部構造を評価するため、図6(a)の破線に示すように、コンタクトホールの中心線に沿って垂直に、評価部分を厚さ約100nmの薄膜部にしてTEM観察の試料を作製したとすれば、図6(b)に示す試料の断面には、目的とする部分構造の断面が2次元的に表示されないことになる。
【0011】
評価の対象とする部分構造の大きさが100nm以下と、高度に微細化される場合には、図6(a)の実線に示すように、部分構造の微細化に合わせてTEM観察の試料とする薄膜部の厚さは、少なくとも、約20nm程度に薄くしなければならない。薄膜部の厚さを約20nmとすれば、図6(b)に示すように、薄膜部の垂直断面には評価の対象とする部分構造の断面が2次元的に示され、高精度のTEM観察が可能になる。
【0012】
次に、図7を用いて、従来のFIB加工を用いたTEM試料の作製方法を、高度に微細化された半導体装置の製造工程の評価に適用する場合に生じる、第2の問題点について説明する。従来のFIB加工を用いたTEM試料の作製方法を図7(a)に具体的に示す。
【0013】
図7(a)におけるTEM試料の作製方法を示す断面図は、TEM観察の対象とするTEM試料101と、ガリウムイオンからなるFIBの照射によりTEM観察の対象とする薄膜部の側面に生じた非晶質層(ダメージ層)104から構成される。
【0014】
図7(a)に示すように、TEM試料101の上面に対して垂直方向に、電圧で加速されたガリウムイオンからなるFIBをスキャニングにより選択的に照射し、TEM観察の対象とするTEM試料101の薄膜部を残してその両側を除去する。このとき、FIBの加速電圧の値は30kVから50kVの範囲であるが、加速されたFIBのガリウムイオンによるダメージを薄膜部の側面に受けることで、側面上に片側当り厚さ20nm乃至30nm(図には30nmの場合が示されている)の非晶質層104が形成される。
【0015】
図7(b)に示すように、TEM観察は薄膜部が形成されたTEM試料101の表面に沿って、薄膜部の側面に対して垂直に電子ビームを入射し、電子レンズ系105を用いて薄膜部を透過する電子ビームをTEM像106として結像させることにより行う。TEM観察を行うためには、TEM試料101の上面を深さ方向に約10μm除去することが必要であるが、このとき、薄膜部の両側面に厚さ約30nmの非晶質層104が形成されるため、薄膜部の厚さ100nmに対し両側で合計40nm乃至60nm(図には60nmの場合が示されている)が非晶質層104に変化する。
【0016】
このように、TEM観察の対象とする厚さ100nmの薄膜部の内、両側の厚さ60nmに達する部分が、TEM試料101の本来の構造とは異なる非晶質層104に変化するため、TEM像には非晶質層の影響が大きく現れ、良好なTEM像の解析を行うことが困難になる。特に高度に微細化された半導体装置の製造工程を評価するため、例えば薄膜部の厚さを60nm程度まで薄くしたとすれば、TEM観察の対象とする薄膜部の厚さ全体が非晶質化することになり、製造工程の評価はほぼ不可能になる。
【0017】
次に、図8を用いて、この問題をさらに具体的に説明する。
図8は、FIBの加速電圧30kV、TEM試料の薄膜部の厚さ60nmにおいて、半導体装置の製造工程の一部を評価するため求めたTEM像である。
【0018】
図8に示すTEM像は、シリコン基板107と、STI(Shallow Trench Isolation)の絶縁膜108と、ポリシリコン層109と、層間絶縁膜110と、タングステンプラグ111と、カーボン層112から構成される。ここで、カーボン層112は、TEM観察の際、電子線によるチャージアップを防止するものであり、評価の対象とする構成要素に含まれない。
【0019】
図8に示すように、金属膜はTEM観察における電子線の透過率が低いので、タングステンプラグ111は、両側で厚さ約60nmに達する非晶質層を通しても、なお強いコントラストで結像しているが、シリコン基板107、STIの絶縁膜108、ポリシリコン層109及び層間絶縁膜110は、図のAに矢示したように、破線で示した本来あるべき位置の各構成要素が、TEM像から完全に抜けてしまい、TEM観察による構造評価を行うことができない。
【0020】
このように、異なる素材からなる構成要素のコントラストがTEM像から消滅する理由は、非晶質層の厚さが60nmに達し、薄膜部全体が非晶質化して素材の結晶構造の相違に基づく電子線の透過率の差がなくなるためである。
【0021】
なお、図8の例では、図の左側がやや厚めの傾向があるので、図の左側では辛うじて各構成要素を見分けることが可能であるが、B、Cに矢示したように、シリコン基板107の本来均一であるべき部分に濃淡のコントラストが発生している。その理由は、上層のタングステンプラグにおけるFIBの加工速度がやや低いために、その直下部における他の構成要素が厚めとなり、薄膜部の内部に非晶質化しない層が僅かに残留したためと考えられる。
【0022】
このように、加速電圧30kV乃至50kV程度の従来のFIBをそのまま用いて、単に薄膜部の厚さを薄くすることにより高度に微細化された半導体装置の製造プロセスを評価しようとすれば、非晶質層の形成により素材の異なる構成要素を見分けることができないばかりでなく、TEM試料作製工程のばらつきがTEM像のコントラストを発生させ、本来存在しないものが像として現れることがある。
【0023】
このほか、薄膜部の厚さ全体が非晶質化することなく、薄膜部の内部にTEM試料の構成要素が存在していても、厚い非晶質層を通して電子線を透過させればTEM像の質が著しく低下するという問題がある。
【0024】
すなわち、TEM観察の対象となる薄膜部の側面がFIBのダメージを受けて非晶質化することにより、一般に、次のような問題を生じていた。
(1)薄膜部5の厚さの1/2程度が非晶質化し、TEM試料が有する本来の構造が破壊されるため、TEM試料本来の構造から得られる所要のTEM像の情報量が減少し、TEM像の質が低下する。
【0025】
(2)薄膜部の厚さが、通常のTEM観察における厚さ約100nmよりも小さく、40nm乃至60nm又はそれ以下となる場合には、薄膜部の厚さ全体が非晶質化し、TEM観察によりTEM試料本来の構造を知ることができない。
【0026】
(3)上記(2)項の場合、薄膜部からTEM試料本来の構造が破壊されるのを回避するために、例えば薄膜部を厚く形成したとしても、TEM観察の対象とする所望の部分の構造以外のもの(非晶質層)がTEM像に含まれるため、TEM像の解釈が困難になる。
【0027】
【発明が解決しようとする課題】
上記したように従来のTEM試料の作製方法は、FIBのダメージを受けてTEM観察に用いる薄膜部の側面が非晶質化し、特に薄膜部の厚さが薄い場合には試料本来の構造を知ることが困難になるという問題があった。
【0028】
本発明は上記の問題点を解決すべくなされたもので、薄膜部の厚さが小さい場合でも、TEM観察により試料本来の構造を示すTEM像が得られるTEM試料の作製方法を提供することを目的とする。
【0029】
【課題を解決するための手段】
本発明のTEM試料の作製方法は、FIBのダメージを受けてTEM観察に用いる薄膜部の側面が非晶質化するのを避けるため、FIBの加速電圧を低くすることを主な特徴とする。
【0030】
具体的には本発明のTEM試料の作製方法は、長手方向に伸びたTEM試料上面領域を残して、その両側を一定の深さまで除去する第1の加速電圧を用いた第1のFIB加工と、第1のFIB加工により上面領域の両側に形成された側面に沿って上面領域の両側をさらに除去するための第1の加速電圧より低い第2の加速電圧を用いた第2のFIB加工を含み、第2のFIB加工において、第2のFIBの加速電圧の値を第1のFIBの加速電圧の値に比べて低くすることにより、第2のFIBの径を第1のFIBの径に比べて大きくし、第2のFIB加工におけるスキャン回数を削減することを特徴とする。
【0031】
好ましくは、本発明のTEM試料の作製方法は、第1のFIB加工と第2のFIB加工との間に、第1のFIB加工の加速電圧より低く第2のFIB加工の加速電圧より高い加速電圧を用いた第3のFIB加工を行うことを特徴とする。
【0032】
また、本発明のTEM試料の作製方法において、第1の加速電圧の値は25kV以上、好ましくは30kV乃至50kVの範囲内であり、前記第2の加速電圧の値は25kV以下、好ましくは5kV乃至15kVの範囲内であることを特徴とする。
【0033】
また、好ましくは第1のFIB加工において、側面上に形成される非晶質層の厚さは片側当り20nm乃至30nmの範囲内であり、第2のFIB加工において、側面上に形成される非晶質層の厚さは片側当り7.5nm乃至15nmの範囲内であることを特徴とする。
【0034】
また、好ましくは第2のFIB加工において、側面上に形成される非晶質層の厚さを片側当りdとし、TEM試料作製後の試料の厚さをDとするときD>2dの関係が成り立つことを特徴とする。
【0036】
また、好ましくは第2のFIB加工に引き続き、第2のFIB加工において側面上に形成される非晶質層をエッチング除去することを特徴とする。
また、好ましくは非晶質層をエッチング除去する工程は、フッ化水素酸又はフッ化アンモニウムのいずれかを含むウエットエッチング、アルゴンガスを用いたスパッタリング、又はケミカルドライエッチングのいずれかによりなされることを特徴とする。
【0037】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。
図1は、本発明の第1の実施の形態に係るTEM試料の作製方法を示す鳥瞰図及び工程断面図である。
はじめに図1(a)の鳥瞰図を用いて、第1の実施の形態に係るTEM試料の作製方法の概要について説明する。
【0038】
図1(a)に示すように、例えばダイヤモンドカッタ等を用いて、TEM試料1の両側を除去するためのダイシング加工を行う。このダイシング加工はTEM試料1の形状をFIBによるTEM試料の作成に便利なように加工する前処理的な工程であって、特に本発明の主要部をなすものではない。
【0039】
次に、ダイシング加工されたTEM試料の1a部分に対して垂直にFIBを照射し、ダイシング加工で残留したTEM試料の1a部分の両側をさらに除去し、TEM観察において電子線を透過させる薄膜部を形成する。なお、図1(a)は模式図であって、実際の厚さ及び深さの比は図示されたものと大きく異なっている(例えば、図7(a)の寸法参照)。
【0040】
第1の実施の形態に係るTEM試料作製方法の特徴は、FIBによる薄膜部の形成を複数段階に分けて行うことにある。図1(b)、図1(c)を用いて、FIBによる2段階の薄膜部の形成方法を例として詳細に説明する。
【0041】
図1(b)は、図1(a)のX−X断面を示す図である。
図1(b)に示すTEM試料は、基板部1aと、加速電圧30kVのFIB加工により残留した基板部1aにつながる薄膜部1bと、薄膜部1bの側面2と、FIB加工により薄膜部1bの側面2に発生した非晶質層3と、TEM試料1の加工前の上面の一部からなる薄膜部1bの上面領域4と、FIB加工後のTEM試料1の上面5から構成される。なお、図1(b)において、図1(a)におけるTEM試料1のダイシング面の下部は省略されている。
【0042】
図1(b)に示すように、TEM試料1aの上面に対して垂直に電圧30kVで加速されたガリウムイオンからなるFIBを照射し、TEM観察の対象とする薄膜部1bを残してTEM試料1aの上面を深さ方向に加工する。先に述べたように、FIBの加速電圧を30kVとすれば、非晶質層3の厚さは非晶質層1bの片側当り約20nmとなり、これを用いてTEM観察を行えばTEM像の質が著しく低下する。
【0043】
次に、図1(c)に示すように、FIBの加速電圧を5kVに下げて、再度薄膜部1bの側面をFIB加工する。以下、加速電圧を下げて行うFIB加工をFIB仕上げ加工と呼ぶことにする。ここで、FIBの加速電圧を30kVから5kVに低下させるときのFIB加工の問題点について詳細に説明する。
【0044】
従来、ガリウムイオンを用いたFIB加工において、最適な加速電圧の範囲は30kV乃至50kVであるとされ、これを大幅に低下させる実用的な試みは全くなされていなかった。その理由は次の通りである。
【0045】
(1)FIBの加速電圧を低下させれば、ガリウムイオンの加速エネルギーが小さくなるので、ほぼ加速電圧に比例して加工速度が低下する。
【0046】
(2)FIBの加速電圧を低下させればガリウムイオンのビーム幅が拡大するため加工精度が低下し、また加工速度の一層の低下につながる。
【0047】
しかし、図1(c)に示すように、第1の実施の形態において薄膜部1bの側面に対し加速電圧を5kVに下げてFIB仕上げ加工を行えば、図1(b)の加速電圧30kVにおけるFIB加工で生じた厚さ約20nmの非晶質層3を効率よく削減することができる。
【0048】
すなわち、非晶質層3はFIB加工で生じたダメージ層であるため、構成原子の結合力が弱く、低い加速エネルギーのガリウムイオンでこれを容易に除去することができる。また、加速電圧を下げたFIB仕上げ加工においても薄膜部1bの側面上に非晶質層3が形成されるが、その厚さは、加速電圧の高いFIB加工の非晶質層3の厚さに比べて極めて小さくすることができる。さらに、加速電圧を5kVに下げれば、ガリウムイオンのビーム幅が約50nmに拡大するので、図1(b)の厚い非晶質層3を削減するためのFIB仕上げ加工におけるイオンビームのスキャニング回数を減少させることが可能になる。
【0049】
加速電圧5kVにおけるFIB仕上げ加工の方法を図1(c)に示す。
図1(c)に示すFIB仕上げ加工方法の構成は図1(b)のFIB加工方法と同様であるため、対応する部分に同一の参照番号を付して詳細な説明を省略する。
【0050】
図1(c)に示すように、図1(b)のFIB加工に引き続き、TEM試料1aの上面に対して垂直に、電圧5kVで加速されたガリウムイオンからなるFIBを照射し、TEM観察の対象とする薄膜部1bの側面を深さ方向に仕上げ加工する。先に述べたように、図1(b)のFIB加工の後、非晶質層3の厚さは薄膜部1bの片側当り約20nmとなるが、図1(c)に示すFIB仕上げ加工を行うことにより、非晶質層3の厚さを薄膜部1bの片側当り7.5nmに削減することができる。
【0051】
以上、FIBによる2段階の薄膜部の形成方法を例として、TEM試料の作製方法を説明したが、第1の実施の形態に係るTEM試料の作製方法は、必ずしも2段階に限定されるものではない。例えば、FIBの加速電圧を30kVから5kVまで、n段階(nは3以上の整数)に分けてステップ状に低下させることにより、同様の目的を達成することができる。また、FIBの加速電圧の低下方法は必ずしもステップ状である必要はなく、一定のプログラムの下に最良の結果が得られるように連続的に低下させてもよい。
【0052】
なお、図1(b)のFIB加工における加速電圧の値は、必ずしも30kVに限定されるものではなく、25kV以上、好ましくは30kV乃至50kVの最適範囲内に設定することができる。また図1(c)のFIB仕上げ加工における加速電圧の値は、必ずしも5kVに限定されるものではなく、25kV以下好ましくは5kV乃至15kVの最適範囲内に設定することができる。
【0053】
次に、図2を用いて第2の実施の形態について説明する。
第2の実施の形態では、図1(b)における加速電圧30kVのFIB加工で、シリコン基板からなる薄膜部1bの片側に形成された非晶質層3の垂直断面のTEM像の観察結果について説明する。
【0054】
すなわち、図2に示すTEM像は、図1(b)のようにシリコン基板からなる薄膜部1bの側面上に非晶質層3を形成し、さらに、非晶質層3及び薄膜部1bの垂直面(紙面に平行な面)に沿って基板上面から加速電圧30kVのFIB加工と加速電圧5kVのFIB仕上げ加工を行い、薄膜部1b及び非晶質層3の断面を求めたTEM像の片側部である。図2では、非晶質層3の加工表面の位置を破線で示している。図2に示すTEM像から、非晶質層3の厚さは薄膜部1bの片側当り約30nmであると判定される。
【0055】
次に、図3を用いて第3の実施の形態について説明する。
第3の実施の形態では、図1(c)における加速電圧5kVのFIB仕上げ加工で、シリコン基板からなる薄膜部1bの片側に形成された非晶質層3の垂直断面のTEM像の観察結果について説明する。
【0056】
図3に示すTEM像の観察方法は、図2に示す第2の実施の形態と同様であるため説明を省略する。図3に示すTEM像から、非晶質層3の厚さは薄膜部1bの片側当り約7.5nmであると判定される。
【0057】
第2、第3の実施の形態において、FIB加工の加速電圧を30kVから50kVに変化させたときの非晶質層の厚さの範囲は、薄膜部1bの片側当り、20nm乃至30nmの範囲であり、また、FIB仕上げ加工の加速電圧を5kVから15kVに変化させたときの非晶質層の厚さの範囲は、薄膜部1bの片側当り、7.5nm乃至15nmの範囲である。
【0058】
次に、図4を用いて第4の実施の形態について説明する。
第4の実施の形態では、第1の実施の形態で説明したTEM試料作製方法の優れた特徴を示すTEM観察の結果について詳細に説明する。
TEM観察に用いた試料は、シリコン基板6の上面に形成された厚さ10nm以下のゲート酸化膜7と、ゲート酸化膜7の上に形成されたポリシリコンゲート8からなるMOSトランジスタのゲート電極の下部構造であって、薄膜部1bとしてこのゲート電極下部構造を用いたものである。図4(a)は、図1(b)の段階における加速電圧30kVでFIB加工した薄膜部1bのTEM像である。なお、ゲート酸化膜7は、薄膜部1bの上面と平行に配置されている。
【0059】
図4(a)に示すTEM像は、図1(b)の薄膜部1bの両側に形成された合計40nm(片側20nm×2)の厚い非晶質層3を通して薄膜部1bの微細構造をTEM観察しているので、微細構造本来のパターン情報が減少し、全体的にぼけたTEM像になっている。
【0060】
これに対して、図4(b)に示すTEM像は、加速電圧5kVでFIB仕上げ加工した後の、図4(b)の段階における薄膜部1bのTEM観察で得られたものである。このとき、図1(c)の薄膜部1bの両側に形成された合計15nm(片側7.5nm×2)の薄い非晶質層3を通して薄膜部1bの微細構造をTEM観察するので、微細構造本来のパターン情報が明確に示されている。
【0061】
図4(b)のTEM像に矢示したように、シリコン基板6とゲート酸化膜7とポリシリコンゲート8の境界が極めて明確になり、また、ポリシリコンゲート8の内部の微結晶構造や、シリコン基板6におけるシリコン原子の配列状況までも読み取ることができる。
【0062】
次に、本発明の第5の実施の形態について説明する。
第4の実施の形態で説明したように、TEM観察の際、非晶質層3の厚さが薄いほど分解能の高いTEM像が得られる。また、第1の実施の形態で説明したように、TEM試料作製の際、通常の加速電圧におけるFIB加工において薄膜部1bの側面に形成される厚い非晶質層3を薄くする方法として、加速電圧を大幅に低下させたFIB仕上げ加工を行うことが極めて有効である。
【0063】
しかし、非晶質層を薄くする方法は必ずしもFIB仕上げ加工に限定されるものではない。薄膜部1bの側面に形成される非晶質層は、下地TEM試料と結晶性が大きくことなるため、ウエットエッチング又はドライエッチングに対して非晶質層と下地TEM試料との間にエッチング速度の差(エッチング選択性)を生じる。このエッチング選択性を適切に利用すれば、非晶質層を除去することができると考えられる。
【0064】
エッチングによる非晶質層の除去をTEM試料の作製に適用しようとすれば、TEM観察の対象となる薄膜部の厚さが数10nm以下と極めて薄く、通常非晶質層の厚さが薄膜部全体の厚さの大きな部分を占めるため、一般にエッチングの制御は極めて困難になる。
【0065】
一方、第1の実施の形態で説明したFIB仕上げ加工後の非晶質層の厚さは薄膜部全体の厚さに比べて小さいので、エッチング速度の低いエッチング方法とエッチングの選択性を適切に利用すれば、FIB仕上げ加工後の非晶質層を制御性良く除去することが可能になる。
【0066】
FIB仕上げ加工後における非晶質層のエッチング方法としては、フッ化水素酸又はフッ化アンモニウムのいずれかを含む希釈溶液を用いたウエットエッチング、アルゴンガスを用いたスパッタリング、又はエッチング速度の低いケミカルドライエッチング等を好適に使用することができる。
なお本発明は上記の実施の形態に限定されることはない。その他本発明の要旨を逸脱しない範囲で、種々変形して実施することができる。
【0067】
【発明の効果】
上述したように本発明のTEM試料の作製方法によれば、FIBのダメージを受けてTEM観察に用いる薄膜部の側面が非晶質化し、かつ、薄膜部の厚さが小さい場合でも、さらに薄膜部の側面を加速電圧の低いFIBを用いて仕上げ加工することにより薄膜部における試料本来の構造を示すTEM像が得られ、高度に微細化された半導体装置のプロセス評価に好適に使用することが可能になる。
【図面の簡単な説明】
【図1】第1の実施の形態に係るTEM試料作製方法を示す図であって、
(a)は、ダイシング加工及びFIB加工の工程を示す鳥瞰図。
(b)は、加速電圧の高いFIB加工における厚い非晶質層の形成を示す図。
(c)は、加速電圧の低いFIB仕上げ加工による非晶質層の薄層化を示す図。
【図2】加速電圧の高いFIB加工におけるシリコン基板上の厚い非晶質層の形成を示すTEMの写真。
【図3】加速電圧の低いFIB仕上げ加工におけるシリコン基板上の薄い非晶質層の形成を示すTEMの写真。
【図4】MOSトランジスタのゲート電極下部構造を示すTEMの写真であって、
(a)は、厚い非晶質層が形成される場合のTEMの写真。
(b)は、非晶質層が薄くされた場合のTEMの写真。
【図5】従来の大きい評価試料からTEM観察の薄膜部を形成する状況を示す図であって、
(a)は、評価試料の上面図。
(b)は、薄膜部の断面図。
【図6】高度に微細化された評価試料からTEM観察の薄膜部を形成する場合の従来の問題点を示す図であって、
(a)は、評価試料の上面図。
(b)は、薄膜部の厚さを薄くした状況を示す断面図。
【図7】従来の加速電圧の高いFIB加工を用いるTEM試料の作製方法を示す図であって、
(a)は、FIB加工における薄膜部の厚い非晶質層の形成を示す断面図。
(b)は、薄膜部を用いたTEM像の作成方法を示す図。
【図8】従来の厚い非晶質層によるTEM像の質の低下を示す写真。
【符号の説明】
1…TEM試料
1a…TEM試料のFIB加工部
1b…薄膜部
2…薄膜部側面
3…非晶質層
4…薄膜部上面
5…FIB加工で除去されたTEM試料上面
6…シリコン基板
7…ゲート酸化膜
8…ポリシリコン
101…絶縁膜
102…バリアメタル
103…タングステンプラグ
104…非晶質層
105…レンズ系
106…TEM像
107…シリコン基板
108…STIの絶縁膜
109…ポリシリコン層
110…層間絶縁膜
111…タングステンプラグ
112…カーボン層
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a specimen preparation method for a transmission electron microscope, and more particularly to a specimen preparation method for a transmission electron microscope using a focused ion beam suitable for evaluating a manufacturing process of a highly miniaturized semiconductor device. is there.
[0002]
[Prior art]
2. Description of the Related Art Conventional sample preparation methods for a transmission electron microscope (hereinafter referred to as TEM; Transmission Electron Microscopy) include processing a desired sample using a focused ion beam (hereinafter referred to as FIB). .
[0003]
First, referring to FIGS. 5 and 6, a first method that occurs when a conventional method for manufacturing a TEM sample using FIB is applied to a manufacturing process evaluation of a highly miniaturized semiconductor device having a processing dimension of 100 nm or less. The problem of will be described.
[0004]
FIG. 5 is a schematic view showing a method for producing a TEM sample used for manufacturing process evaluation of a conventional semiconductor device having a processing dimension of several hundred nm or more. For example, a case where a step of embedding a circular contact plug 103 in the insulating film 101 on the semiconductor substrate via the barrier layer 102 is evaluated by TEM observation will be described. This example does not necessarily show a partial structure of an actual semiconductor device, but is shown as a schematic diagram for showing conventional problems.
[0005]
FIG. 5A is a top view of a partial structure to be evaluated. In order to evaluate the embedded state in the contact hole by the barrier layer 102 and the contact plug 103, as shown in FIG. 5A, the evaluation portion is a thin film portion having a thickness of about 100 nm perpendicular to the center line of the contact hole. Then, a sample for TEM observation is prepared, and evaluation is performed by analyzing a TEM image transmitted through the thin film portion.
[0006]
A vertical sectional structure of the thin film portion is shown in FIG. Thus, when the size of the partial structure to be evaluated is sufficiently larger than the thickness of the thin film portion of 100 nm, FIG.
Since the cross section of the partial structure to be evaluated is clearly shown as a two-dimensional pattern in the cross section of the thin film portion shown in (b), good TEM observation can be performed.
[0007]
In recent years, microfabrication technology for semiconductor devices has progressed, and TEM observation has become increasingly important as a method for accurately evaluating the manufacturing process of highly miniaturized semiconductor devices with a processing dimension of 100 nm or less. If the thickness of the thin film portion of the sample used for TEM observation remains at the conventional value of about 100 nm, it is practically impossible to perform good TEM observation.
[0008]
Next, this problem will be described in detail with reference to FIGS. 6 (a) and 6 (b).
[0009]
The top view of the partial structure to be evaluated shown in FIG. 6A includes an insulating film 101 on the semiconductor substrate, a barrier layer 102, and a contact plug 103, as in FIG. 5A. However, it is different from FIG. 5A in that the manufacturing process is further miniaturized and the inner diameter of the contact hole is reduced to 100 nm or less (in FIG. 6A, the inner diameter of the contact hole is just 100 nm. It is shown).
[0010]
In order to evaluate the embedding condition and the internal structure inside the contact hole thus miniaturized, as shown by the broken line in FIG. 6 (a), the evaluation portion has a thickness of about perpendicular to the center line of the contact hole. If a sample for TEM observation is prepared with a thin film portion of 100 nm, the cross section of the target partial structure is not two-dimensionally displayed on the cross section of the sample shown in FIG.
[0011]
When the size of the partial structure to be evaluated is 100 nm or less and is highly miniaturized, as shown by the solid line in FIG. The thickness of the thin film portion to be made must be at least as thin as about 20 nm. If the thickness of the thin film portion is about 20 nm, as shown in FIG. 6 (b), the vertical cross section of the thin film portion shows the cross section of the partial structure to be evaluated two-dimensionally, and a highly accurate TEM Observation becomes possible.
[0012]
Next, with reference to FIG. 7, a second problem that occurs when the conventional method for manufacturing a TEM sample using FIB processing is applied to the evaluation of a manufacturing process of a highly miniaturized semiconductor device will be described. To do. A method for manufacturing a TEM sample using conventional FIB processing is specifically shown in FIG.
[0013]
FIG. 7A is a cross-sectional view showing a method for manufacturing a TEM sample. The TEM sample 101 to be subjected to TEM observation and the non-conductivity generated on the side surface of the thin film portion to be subjected to TEM observation by irradiation with FIB made of gallium ions. It is composed of a crystalline layer (damage layer) 104.
[0014]
As shown in FIG. 7A, FIB made of gallium ions accelerated by voltage is selectively irradiated by scanning in a direction perpendicular to the upper surface of the TEM sample 101, and the TEM sample 101 to be subjected to TEM observation. Remove both sides of the thin film part. At this time, the acceleration voltage value of the FIB is in the range of 30 kV to 50 kV. However, when the side surface of the thin film portion is damaged by the accelerated FIB gallium ions, the thickness per side is 20 nm to 30 nm (see FIG. Is shown in the case of 30 nm).
[0015]
As shown in FIG. 7B, in the TEM observation, an electron beam is incident perpendicularly to the side surface of the thin film portion along the surface of the TEM sample 101 on which the thin film portion is formed, and the electron lens system 105 is used. This is performed by forming an electron beam that passes through the thin film portion as a TEM image 106. TEM sample for TEM observation 101 It is necessary to remove the upper surface of the thin film portion by about 10 μm in the depth direction. At this time, since the amorphous layer 104 having a thickness of about 30 nm is formed on both sides of the thin film portion, the thickness of the thin film portion is reduced to 100 nm. On the other hand, a total of 40 nm to 60 nm (in the figure, the case of 60 nm is shown) is changed to the amorphous layer 104 on both sides.
[0016]
As described above, the portion reaching the thickness of 60 nm on both sides of the thin film portion having a thickness of 100 nm to be subjected to the TEM observation is changed to the amorphous layer 104 different from the original structure of the TEM sample 101. The image is greatly affected by the amorphous layer, making it difficult to analyze a good TEM image. In particular, in order to evaluate the manufacturing process of a highly miniaturized semiconductor device, for example, if the thickness of the thin film portion is reduced to about 60 nm, the entire thickness of the thin film portion to be subjected to TEM observation becomes amorphous. Therefore, the evaluation of the manufacturing process becomes almost impossible.
[0017]
Next, this problem will be described more specifically with reference to FIG.
FIG. 8 is a TEM image obtained to evaluate a part of the manufacturing process of the semiconductor device at an acceleration voltage of FIB of 30 kV and a thickness of the thin film portion of the TEM sample of 60 nm.
[0018]
The TEM image shown in FIG. 8 includes a silicon substrate 107, an STI (Shallow Trench Isolation) insulating film 108, a polysilicon layer 109, an interlayer insulating film 110, a tungsten plug 111, and a carbon layer 112. Here, the carbon layer 112 prevents charge-up by an electron beam during TEM observation, and is not included in the constituent elements to be evaluated.
[0019]
As shown in FIG. 8, since the metal film has a low electron beam transmittance in TEM observation, the tungsten plug 111 still forms an image with strong contrast even through an amorphous layer reaching a thickness of about 60 nm on both sides. However, the silicon substrate 107, the STI insulating film 108, the polysilicon layer 109, and the interlayer insulating film 110, as indicated by arrows A in FIG. Therefore, the structure cannot be evaluated by TEM observation.
[0020]
As described above, the reason why the contrast of the components made of different materials disappears from the TEM image is that the thickness of the amorphous layer reaches 60 nm, the entire thin film portion becomes amorphous, and the difference in the crystal structure of the materials. This is because there is no difference in electron beam transmittance.
[0021]
In the example of FIG. 8, since the left side of the figure tends to be slightly thicker, it is possible to barely distinguish each component on the left side of the figure, but as indicated by arrows B and C, the silicon substrate 107 A contrast of light and shade is generated in a portion that should be uniform. The reason is considered that the processing speed of FIB in the upper tungsten plug is slightly low, so that the other constituent elements immediately below it are thick, and a layer that does not become amorphous remains slightly in the thin film portion. .
[0022]
In this way, if a conventional FIB having an acceleration voltage of about 30 kV to 50 kV is used as it is and an attempt is made to evaluate the manufacturing process of a highly miniaturized semiconductor device by simply reducing the thickness of the thin film portion, an amorphous structure is obtained. The formation of the quality layer not only makes it impossible to distinguish the constituent elements of different materials, but variations in the TEM sample preparation process may cause the contrast of the TEM image to appear as an image that originally does not exist.
[0023]
In addition, the entire thickness of the thin film portion does not become amorphous, and a TEM image can be obtained by transmitting an electron beam through the thick amorphous layer even if the constituent elements of the TEM sample exist inside the thin film portion. There is a problem that the quality of the product is significantly reduced.
[0024]
In other words, the side face of the thin film portion to be observed by TEM becomes amorphous due to the damage of the FIB, and generally causes the following problems.
(1) About 1/2 of the thickness of the thin film portion 5 becomes amorphous, and the original structure of the TEM sample is destroyed, so that the amount of information of a required TEM image obtained from the original structure of the TEM sample is reduced. As a result, the quality of the TEM image is degraded.
[0025]
(2) When the thickness of the thin film portion is smaller than about 100 nm in normal TEM observation and becomes 40 nm to 60 nm or less, the entire thickness of the thin film portion becomes amorphous, and the TEM observation The original structure of the TEM sample cannot be known.
[0026]
(3) In the case of the above (2), in order to avoid the destruction of the original structure of the TEM sample from the thin film portion, for example, even if the thin film portion is formed thick, the desired portion to be subjected to TEM observation Since the structure (amorphous layer) other than the structure is included in the TEM image, it is difficult to interpret the TEM image.
[0027]
[Problems to be solved by the invention]
As described above, the conventional method for preparing a TEM sample is such that the side surface of the thin film portion used for TEM observation becomes amorphous due to the damage of the FIB, and the original structure of the sample is known particularly when the thin film portion is thin. There was a problem that it became difficult.
[0028]
The present invention has been made to solve the above-described problems, and provides a method for preparing a TEM sample in which a TEM image showing the original structure of the sample can be obtained by TEM observation even when the thickness of the thin film portion is small. Objective.
[0029]
[Means for Solving the Problems]
The main feature of the method for manufacturing a TEM sample of the present invention is that the acceleration voltage of the FIB is lowered in order to avoid the side surface of the thin film portion used for TEM observation from becoming amorphous due to the damage of the FIB.
[0030]
Specifically, the method for producing a TEM sample of the present invention includes a first FIB process using a first acceleration voltage that leaves a TEM sample upper surface region extending in the longitudinal direction and removes both sides thereof to a certain depth. The second FIB processing using a second acceleration voltage lower than the first acceleration voltage for further removing both sides of the upper surface region along the side surfaces formed on both sides of the upper surface region by the first FIB processing is performed. Including Thus, in the second FIB processing, the second FIB diameter is reduced to the first FIB diameter by lowering the acceleration voltage value of the second FIB compared to the acceleration voltage value of the first FIB. Increased compared to reduce the number of scans in the second FIB processing It is characterized by that.
[0031]
Preferably, in the method for producing a TEM sample according to the present invention, the acceleration between the first FIB processing and the second FIB processing is lower than the acceleration voltage of the first FIB processing and higher than the acceleration voltage of the second FIB processing. A third FIB process using a voltage is performed.
[0032]
In the method for manufacturing a TEM sample of the present invention, the first acceleration voltage value is 25 kV or more, preferably 30 kV to 50 kV, and the second acceleration voltage value is 25 kV or less, preferably 5 kV to It is in the range of 15 kV.
[0033]
Preferably, in the first FIB processing, the thickness of the amorphous layer formed on the side surface is in the range of 20 nm to 30 nm per side, and in the second FIB processing, the non-layer formed on the side surface is formed. The thickness of the crystalline layer is characterized by being in the range of 7.5 nm to 15 nm per side.
[0034]
Preferably, in the second FIB processing, when the thickness of the amorphous layer formed on the side surface is d per side and the thickness of the sample after the TEM sample is made D is D> 2d It is characterized by being satisfied.
[0036]
Further, preferably, following the second FIB processing, the amorphous layer formed on the side surface in the second FIB processing is removed by etching.
Preferably, the step of removing the amorphous layer by etching is performed by any one of wet etching containing either hydrofluoric acid or ammonium fluoride, sputtering using argon gas, or chemical dry etching. Features.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
1A to 1C are a bird's-eye view and a process cross-sectional view showing a method for manufacturing a TEM sample according to the first embodiment of the present invention.
First, an outline of a method for manufacturing a TEM sample according to the first embodiment will be described using the bird's-eye view of FIG.
[0038]
As shown in FIG. 1A, dicing processing for removing both sides of the TEM sample 1 is performed using, for example, a diamond cutter or the like. This dicing process is a pre-processing step for processing the shape of the TEM sample 1 so as to be convenient for creating a TEM sample by FIB, and does not particularly form the main part of the present invention.
[0039]
Next, FIB is irradiated perpendicularly to the 1a portion of the diced TEM sample, both sides of the 1a portion of the TEM sample remaining after the dicing are further removed, and a thin film portion that transmits an electron beam in TEM observation is obtained. Form. FIG. 1A is a schematic diagram, and the actual thickness / depth ratio is significantly different from that shown in the figure (for example, see the dimensions in FIG. 7A).
[0040]
The feature of the TEM sample manufacturing method according to the first embodiment is that the thin film portion is formed by FIB in a plurality of stages. With reference to FIGS. 1B and 1C, a detailed description will be given of a two-stage thin film portion forming method by FIB as an example.
[0041]
FIG.1 (b) is a figure which shows the XX cross section of Fig.1 (a).
The TEM sample shown in FIG. 1B includes a substrate portion 1a, a thin film portion 1b connected to the substrate portion 1a remaining after FIB processing with an acceleration voltage of 30 kV, a side surface 2 of the thin film portion 1b, and a thin film portion 1b formed by FIB processing. The amorphous layer 3 generated on the side surface 2, the upper surface region 4 of the thin film portion 1 b composed of a part of the upper surface of the TEM sample 1 before processing, and the upper surface 5 of the TEM sample 1 after FIB processing. In FIG. 1B, the lower part of the dicing surface of the TEM sample 1 in FIG.
[0042]
As shown in FIG. 1B, the TEM sample 1a is irradiated with FIB made of gallium ions accelerated at a voltage of 30 kV perpendicularly to the upper surface of the TEM sample 1a, leaving the thin film portion 1b to be subjected to TEM observation. Is processed in the depth direction. As described above, if the acceleration voltage of FIB is set to 30 kV, the thickness of the amorphous layer 3 is about 20 nm per side of the amorphous layer 1b. If TEM observation is performed using this, the TEM image is obtained. The quality is significantly reduced.
[0043]
Next, as shown in FIG. 1C, the acceleration voltage of the FIB is lowered to 5 kV, and the side surface of the thin film portion 1b is FIB processed again. Hereinafter, the FIB processing performed by lowering the acceleration voltage is referred to as FIB finishing processing. Here, the problem of FIB processing when the acceleration voltage of FIB is reduced from 30 kV to 5 kV will be described in detail.
[0044]
Conventionally, in the FIB processing using gallium ions, the optimum acceleration voltage range is 30 kV to 50 kV, and no practical attempt has been made to significantly reduce this range. The reason is as follows.
[0045]
(1) If the acceleration voltage of the FIB is lowered, the acceleration energy of the gallium ions is reduced, so that the processing speed is reduced substantially in proportion to the acceleration voltage.
[0046]
(2) If the acceleration voltage of the FIB is lowered, the beam width of gallium ions is expanded, so that the machining accuracy is lowered and the machining speed is further reduced.
[0047]
However, as shown in FIG. 1C, if the FIB finishing process is performed with the acceleration voltage lowered to 5 kV on the side surface of the thin film portion 1b in the first embodiment, the acceleration voltage at 30 kV in FIG. The amorphous layer 3 having a thickness of about 20 nm generated by the FIB processing can be efficiently reduced.
[0048]
That is, since the amorphous layer 3 is a damaged layer generated by FIB processing, the bonding force of the constituent atoms is weak, and this can be easily removed with gallium ions having low acceleration energy. Also, in the FIB finishing process with the acceleration voltage lowered, the amorphous layer 3 is formed on the side surface of the thin film portion 1b. The thickness of the amorphous layer 3 is the thickness of the FIB process with a high acceleration voltage. It can be made extremely small compared to. Further, if the acceleration voltage is lowered to 5 kV, the beam width of gallium ions is expanded to about 50 nm. Therefore, the number of times of ion beam scanning in the FIB finishing process for reducing the thick amorphous layer 3 in FIG. It becomes possible to decrease.
[0049]
FIG. 1C shows a FIB finishing method at an acceleration voltage of 5 kV.
Since the configuration of the FIB finishing method shown in FIG. 1C is the same as that of the FIB processing method of FIG. 1B, the same reference numerals are assigned to the corresponding portions, and detailed description thereof is omitted.
[0050]
As shown in FIG. 1C, following the FIB processing in FIG. 1B, the FIB made of gallium ions accelerated at a voltage of 5 kV is irradiated perpendicularly to the upper surface of the TEM sample 1a, and the TEM observation is performed. The side surface of the target thin film portion 1b is finished in the depth direction. As described above, after the FIB processing of FIG. 1B, the thickness of the amorphous layer 3 is about 20 nm per one side of the thin film portion 1b, but the FIB finishing processing shown in FIG. By doing so, the thickness of the amorphous layer 3 can be reduced to 7.5 nm per side of the thin film portion 1b.
[0051]
As described above, the method for forming a TEM sample has been described using the FIB two-stage thin film portion forming method as an example. However, the method for manufacturing a TEM sample according to the first embodiment is not necessarily limited to two stages. Absent. For example, the same purpose can be achieved by decreasing the FIB acceleration voltage from 30 kV to 5 kV in steps of n (n is an integer of 3 or more). The method for reducing the acceleration voltage of the FIB does not necessarily have to be stepped, and may be continuously reduced so that the best result is obtained under a certain program.
[0052]
Note that the value of the acceleration voltage in the FIB processing of FIG. 1B is not necessarily limited to 30 kV, and can be set within the optimum range of 25 kV or more, preferably 30 kV to 50 kV. Further, the value of the acceleration voltage in the FIB finishing shown in FIG. 1C is not necessarily limited to 5 kV, and can be set within the optimum range of 25 kV or less, preferably 5 kV to 15 kV.
[0053]
Next, a second embodiment will be described with reference to FIG.
In the second embodiment, the observation result of the TEM image of the vertical cross section of the amorphous layer 3 formed on one side of the thin film portion 1b made of the silicon substrate by FIB processing with an acceleration voltage of 30 kV in FIG. explain.
[0054]
That is, in the TEM image shown in FIG. 2, the amorphous layer 3 is formed on the side surface of the thin film portion 1b made of the silicon substrate as shown in FIG. 1B, and the amorphous layer 3 and the thin film portion 1b are further formed. One side of a TEM image obtained by performing FIB processing at an acceleration voltage of 30 kV and FIB finishing processing at an acceleration voltage of 5 kV from the upper surface of the substrate along a vertical plane (a plane parallel to the paper surface) to obtain cross sections of the thin film portion 1b and the amorphous layer 3 Part. In FIG. 2, the position of the processed surface of the amorphous layer 3 is indicated by a broken line. From the TEM image shown in FIG. 2, it is determined that the thickness of the amorphous layer 3 is about 30 nm per one side of the thin film portion 1b.
[0055]
Next, a third embodiment will be described with reference to FIG.
In the third embodiment, the observation result of the TEM image of the vertical cross section of the amorphous layer 3 formed on one side of the thin film portion 1b made of the silicon substrate by the FIB finishing with the acceleration voltage of 5 kV in FIG. Will be described.
[0056]
The method for observing the TEM image shown in FIG. 3 is the same as that of the second embodiment shown in FIG. From the TEM image shown in FIG. 3, it is determined that the thickness of the amorphous layer 3 is about 7.5 nm per one side of the thin film portion 1b.
[0057]
In the second and third embodiments, the thickness range of the amorphous layer when the acceleration voltage of FIB processing is changed from 30 kV to 50 kV is in the range of 20 nm to 30 nm per side of the thin film portion 1b. In addition, the thickness range of the amorphous layer when the acceleration voltage of FIB finishing is changed from 5 kV to 15 kV is in the range of 7.5 nm to 15 nm per one side of the thin film portion 1b.
[0058]
Next, a fourth embodiment will be described with reference to FIG.
In the fourth embodiment, the result of TEM observation showing the excellent features of the TEM sample manufacturing method described in the first embodiment will be described in detail.
A sample used for the TEM observation is a gate electrode of a MOS transistor including a gate oxide film 7 having a thickness of 10 nm or less formed on the upper surface of the silicon substrate 6 and a polysilicon gate 8 formed on the gate oxide film 7. It is a lower structure, and this gate electrode lower structure is used as the thin film portion 1b. FIG. 4A is a TEM image of the thin film portion 1b subjected to FIB processing at an acceleration voltage of 30 kV in the stage of FIG. The gate oxide film 7 is arranged in parallel with the upper surface of the thin film portion 1b.
[0059]
The TEM image shown in FIG. 4A shows the microstructure of the thin film portion 1b through the thick amorphous layer 3 of 40 nm in total (20 nm × 2 on one side) formed on both sides of the thin film portion 1b in FIG. As a result of the observation, the pattern information inherent to the fine structure is reduced, resulting in a totally blurred TEM image.
[0060]
On the other hand, the TEM image shown in FIG. 4B is obtained by TEM observation of the thin film portion 1b in the stage of FIG. 4B after the FIB finish processing at an acceleration voltage of 5 kV. At this time, since the fine structure of the thin film portion 1b is observed by TEM through the thin amorphous layer 3 of 15 nm in total (7.5 nm × 2 on one side) formed on both sides of the thin film portion 1b in FIG. The original pattern information is clearly shown.
[0061]
As shown by an arrow in the TEM image of FIG. 4B, the boundary between the silicon substrate 6, the gate oxide film 7 and the polysilicon gate 8 becomes very clear, the microcrystalline structure inside the polysilicon gate 8, Even the arrangement state of silicon atoms on the silicon substrate 6 can be read.
[0062]
Next, a fifth embodiment of the present invention will be described.
As described in the fourth embodiment, in TEM observation, a TEM image with higher resolution can be obtained as the amorphous layer 3 is thinner. Further, as described in the first embodiment, when a TEM sample is manufactured, acceleration is performed as a method for thinning the thick amorphous layer 3 formed on the side surface of the thin film portion 1b in FIB processing at a normal acceleration voltage. It is extremely effective to perform FIB finishing with a greatly reduced voltage.
[0063]
However, the method for thinning the amorphous layer is not necessarily limited to FIB finishing. Since the amorphous layer formed on the side surface of the thin film portion 1b has a large crystallinity with the base TEM sample, the etching rate is low between the amorphous layer and the base TEM sample with respect to wet etching or dry etching. A difference (etch selectivity) occurs. It is considered that the amorphous layer can be removed by appropriately using this etching selectivity.
[0064]
If the removal of the amorphous layer by etching is applied to the preparation of a TEM sample, the thickness of the thin film portion to be observed by the TEM is extremely thin, several tens of nm or less, and the thickness of the amorphous layer is usually the thin film portion. Since it occupies a large portion of the overall thickness, it is generally very difficult to control etching.
[0065]
On the other hand, since the thickness of the amorphous layer after the FIB finishing described in the first embodiment is smaller than the thickness of the entire thin film portion, the etching method with a low etching rate and the etching selectivity are appropriately set. If used, the amorphous layer after FIB finishing can be removed with good controllability.
[0066]
As a method for etching an amorphous layer after FIB finishing, wet etching using a dilute solution containing either hydrofluoric acid or ammonium fluoride, sputtering using argon gas, or chemical drying with a low etching rate is used. Etching or the like can be preferably used.
The present invention is not limited to the above embodiment. Various other modifications can be made without departing from the scope of the present invention.
[0067]
【The invention's effect】
As described above, according to the TEM sample manufacturing method of the present invention, even if the side surface of the thin film portion used for TEM observation becomes amorphous due to the damage of the FIB and the thickness of the thin film portion is small, the thin film is further thinned. The side surface of the part is finished with FIB having a low acceleration voltage, so that a TEM image showing the original structure of the sample in the thin film part can be obtained and used suitably for process evaluation of highly miniaturized semiconductor devices. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a diagram showing a TEM sample manufacturing method according to a first embodiment,
(A) is a bird's-eye view which shows the process of a dicing process and FIB process.
(B) is a figure which shows formation of the thick amorphous layer in FIB process with a high acceleration voltage.
(C) is a figure which shows thinning of the amorphous layer by FIB finishing process with a low acceleration voltage.
FIG. 2 is a TEM photograph showing the formation of a thick amorphous layer on a silicon substrate in FIB processing with a high acceleration voltage.
FIG. 3 is a TEM photograph showing the formation of a thin amorphous layer on a silicon substrate in FIB finishing with a low acceleration voltage.
FIG. 4 is a TEM photograph showing a lower structure of a gate electrode of a MOS transistor,
(A) is a TEM photograph when a thick amorphous layer is formed.
(B) is a TEM photograph when the amorphous layer is thinned.
FIG. 5 is a diagram showing a situation in which a thin film portion for TEM observation is formed from a conventional large evaluation sample,
(A) is a top view of an evaluation sample.
(B) is sectional drawing of a thin film part.
FIG. 6 is a diagram showing a conventional problem when a thin film portion for TEM observation is formed from a highly miniaturized evaluation sample,
(A) is a top view of an evaluation sample.
(B) is sectional drawing which shows the condition which made thin the thickness of a thin film part.
FIG. 7 is a diagram showing a method for manufacturing a TEM sample using FIB processing with a conventional high acceleration voltage,
(A) is sectional drawing which shows formation of the thick amorphous layer of the thin film part in FIB process.
(B) is a figure which shows the preparation method of the TEM image using a thin film part.
FIG. 8 is a photograph showing degradation of TEM image quality by a conventional thick amorphous layer.
[Explanation of symbols]
1 ... TEM sample
1a: FIB processing part of TEM sample
1b ... Thin film part
2 ... Side film side
3. Amorphous layer
4. Top surface of thin film
5 ... TEM sample top surface removed by FIB processing
6 ... Silicon substrate
7 ... Gate oxide film
8 ... Polysilicon
101: Insulating film
102 ... Barrier metal
103 ... Tungsten plug
104: Amorphous layer
105 ... Lens system
106 ... TEM image
107: Silicon substrate
108 ... STI insulating film
109 ... polysilicon layer
110 ... Interlayer insulating film
111 ... Tungsten plug
112 ... carbon layer

Claims (7)

長手方向に伸びた試料上面領域を残してその両側を一定の深さまで除去する第1の加速電圧を用いた第1のフォーカスド・イオンビーム加工と、
前記第1のフォーカスド・イオンビーム加工により前記試料上面領域の両側に形成された側面に沿って前記試料上面領域の両側をさらに除去する前記第1の加速電圧より低い第2の加速電圧を用いた第2のフォーカスド・イオンビーム加工とを含み、
前記第2のフォーカスド・イオンビーム加工において、前記第2のフォーカスド・イオンビームの加速電圧の値を前記第1のフォーカスド・イオンビームの加速電圧の値に比べて低くすることにより、前記第2のフォーカスド・イオンビームの径を前記第1のフォーカスド・イオンビームの径に比べて大きくし、前記第2のフォーカスド・イオンビーム加工におけるスキャン回数を削減することを特徴とする透過型電子顕微鏡の試料作製方法。
A first focused ion beam processing using a first acceleration voltage that leaves a sample upper surface region extending in the longitudinal direction and removes both sides thereof to a certain depth;
A second acceleration voltage lower than the first acceleration voltage for further removing both sides of the sample upper surface region along side surfaces formed on both sides of the sample upper surface region by the first focused ion beam processing is used. Second focused ion beam processing
In the second focused ion beam processing, by reducing the value of the acceleration voltage of the second focused ion beam compared to the value of the acceleration voltage of the first focused ion beam, A transmission characterized in that the diameter of the second focused ion beam is made larger than the diameter of the first focused ion beam and the number of scans in the second focused ion beam processing is reduced. Of electron microscope sample preparation.
前記第1のフォーカスド・イオンビーム加工と前記第2のフォーカスド・イオンビーム加工との間に、前記第1のフォーカスド・イオンビーム加工の加速電圧より低く前記第2のフォーカスド・イオンビーム加工の加速電圧より高い加速電圧を用いた第3のフォーカスド・イオンビーム加工を行うことを特徴とする請求項1記載の透過型電子顕微鏡の試料作製方法。  Between the first focused ion beam processing and the second focused ion beam processing, the second focused ion beam is lower than the acceleration voltage of the first focused ion beam processing. The method for preparing a sample for a transmission electron microscope according to claim 1, wherein the third focused ion beam processing is performed using an acceleration voltage higher than the processing acceleration voltage. 前記第1の加速電圧の値は30kV乃至50kVの範囲内であり、前記第2の加速電圧の値は5kV乃至15kVの範囲内であることを特徴とする請求項1、2のいずれか1つに記載の透過型電子顕微鏡の試料作製方法。The value of the first acceleration voltage is in a range of 30 kV to 50 kV, and the value of the second acceleration voltage is in a range of 5 kV to 15 kV. The sample preparation method of the transmission electron microscope as described in one. 前記第1のフォーカスド・イオンビーム加工において、前記側面上に形成される非晶質層の厚さは、前記上面領域の片側当り20nm乃至30nmの範囲内であり、前記第2のフォーカスド・イオンビーム加工において、前記側面上に形成される非晶質層の厚さは、前記上面領域の片側当り7.5nm乃至15nmの範囲内であることを特徴とする請求項1、2のいずれか1つに記載の透過型電子顕微鏡の試料作製方法。  In the first focused ion beam processing, the thickness of the amorphous layer formed on the side surface is in the range of 20 nm to 30 nm per side of the upper surface region, and the second focused ion beam processing is performed. The thickness of the amorphous layer formed on the side surface in the ion beam processing is in the range of 7.5 nm to 15 nm per side of the upper surface region. The sample preparation method of the transmission electron microscope as described in one. 前記第2のフォーカスド・イオンビーム加工において、前記側面上に形成される非晶質層の厚さを片側当りdとし、前記透過型電子顕微鏡の試料作製後の試料の厚さをDとするとき、D>2dの関係が成り立つことを特徴とする請求項1、2のいずれか1つに記載の透過型電子顕微鏡の試料作製方法。  In the second focused ion beam processing, the thickness of the amorphous layer formed on the side surface is d per side, and the thickness of the sample after the preparation of the transmission electron microscope is D. The method for preparing a sample for a transmission electron microscope according to claim 1, wherein a relationship of D> 2d is established. 前記第2のフォーカスド・イオンビーム加工に引き続き、前記第2のフォーカスド・イオンビーム加工において前記側面上に形成される非晶質層をエッチングにより除去することを特徴とする請求項1、2のいずれか1つに記載の透過型電子顕微鏡の試料作製方法。  The amorphous layer formed on the side surface in the second focused ion beam processing is removed by etching following the second focused ion beam processing. The sample preparation method of the transmission electron microscope as described in any one of these. 前記非晶質層をエッチングにより除去する工程は、フッ化水素酸又はフッ化アンモニウムのいずれかを含むウエットエッチング、アルゴンガスを用いたスパッタリング、又はケミカルドライエッチングのいずれかによりなされることを特徴とする請求項6記載の透過型電子顕微鏡の試料作製方法。  The step of removing the amorphous layer by etching is performed by any of wet etching containing either hydrofluoric acid or ammonium fluoride, sputtering using argon gas, or chemical dry etching. A method for preparing a sample for a transmission electron microscope according to claim 6.
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