JP3926515B2 - Electronics - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic apparatus , and more particularly to an address decoder circuit in an electronic apparatus that controls a CPU and a plurality of devices.
[0002]
[Prior art]
The power supply voltage of recent electronic devices is 5.0 V, which has existed for a long time, and 3.3 V due to process miniaturization. In the 3.3V device, the upper limit of the input signal voltage is about 4V, and an input signal of 5.0V is not allowed. Therefore, when a 3.3V device and a 5.0V device are used together, a bus that is used in common, such as a data bus, cannot be used in common at 3.3V and 5.0V. It must be divided by etc. As described above, it is often not easy to change a device that outputs a chip enable signal and various control signals when the mixed use of 3.3 V and 5.0 V power supply devices divided by a buffer is considered. In particular, in the case of controlling by ASIC (application specific integrated circuit), production takes time and cost. In many cases, the power supply voltage is changed due to a change of a connected device or a cost difference, and the change makes the control of the external buffer necessary or unnecessary. Conventionally, in such a case, the ASIC is recreated or the power supply voltage of the device cannot be changed.
[0003]
Conventionally, there was no problem because there was no buffer, but in the case where 3.3V and 5.0V power supply voltages coexist, it becomes a problem whether or not to use the buffer before setting by software at power-on. .
[0004]
[Problems to be solved by the invention]
Therefore, conventionally, when there is an IC with an input level of CMOS level so that it can be used with both power supplies of 3.3V and 5.0V, there is no problem when the power supply voltage is 3.3V, but 5.0V In order to recognize that the input signal is high, the input voltage must be greater than 3.5V. If the power supply of a device that outputs various control signals including chip enable is 3.3 V, a voltage higher than the power supply voltage is not generated, and therefore all signals are recognized as being at a low level.
[0005]
The present invention is for solving these problems, and by making it possible to control whether a signal is output at 3.3 V or 5.0 V for each chip select signal, the ASIC can be controlled. It is an object of the present invention to provide an electronic device having an address decoder circuit that can change wiring without reworking and can flexibly cope with future progress in process technology and a decrease in voltage.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, a CPU, a plurality of devices having different power supply voltages , an address decoder circuit that outputs a selection signal for selecting the device, and at least one of the devices are connected , and a control signal to the device in the electronic device having a buffer that converts the amplitude, the address decoder circuit includes a buffer control signal output unit that outputs a buffer control signal for controlling the buffer, for each device selected by the selection signal, the device viewed from a buffer A buffer enable register that specifies the position of the input signal and an input signal terminal to which an input signal is supplied. When the power is turned on, the buffer is enabled according to the preset signal level of the input signal terminal. The buffer control signal is activated by referring to the predetermined address set in the register. For controlling whether or not to. When the CPU accesses the device, the address decoder circuit switches the amplitude of the control signal to the device in accordance with a predetermined address set in the buffer enable register. Furthermore, devices having the same power supply voltage are connected to each side of the buffer. Therefore, it is possible to provide an electronic device having an address decoder circuit that can change the wiring without remaking the ASIC, and can flexibly cope with the progress of the process technology and the lowering of the voltage in the future.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
In synchronization with the enable signal in the address range to the device, the control signal of the buffer responsible for controlling the access to the device is switched in a programmable manner based on a predetermined signal sequence.
[0008]
【Example】
FIG. 1 is a block diagram showing a main configuration of an electronic apparatus including an address decoder circuit according to an embodiment of the present invention. In the figure, the address decoder circuit of the present embodiment comprises a CPU 11, an ASIC 12, a buffer 13, a flash memory 14, a nonvolatile memory 15, a general purpose synchronous / asynchronous transceiver (hereinafter abbreviated as URAT) 16, and the like. The ASIC in this embodiment has a plurality of selection signals by, for example, a local bus controller, and each selection signal is assigned to a chip select signal such as ROM, NVRAM, IC CARD, OPION BUS, UART, or the like. The buffer enable function in this embodiment has a function for designating whether the device is outside or inside the external buffer for each chip select signal. Further, by setting with a predetermined address in the ACK control buffer enable register in this embodiment, it is specified whether the device is inside or outside the buffer 13. When the device is arranged inside the buffer 13, the LBUF signal does not go low but remains high, and becomes low (active) at a predetermined timing only when it is outside the buffer 13. The LBUF signal and LDIR signal are connected to the EN terminal of the buffer 13 and the LBUF signal is connected to the DIR terminal. As an operation, the value of the register in which the condition for asserting the LBUF signal is always set is referred to, and it is determined whether to activate according to the value.
[0009]
Further, as can be seen from FIG. 2 showing the relationship between the ASIC 12 and the buffer 13 in detail in FIG. 1, the ASIC 12 is provided with a BT5V signal terminal (hardware pin), and the signal to the BT5V signal terminal is fixed to low or high. . Which is fixed depends on the case where the CBOT signal is “H”. The boot device at the time of power-on at this time is the flash memory 14, and if the device is outside the buffer 13, it is set to “L”, and if it is inside, it is set to “H” so that it can be normally accessed at a predetermined timing. it can. As an operation, the signal to the BT5V signal terminal is referred to when the power is turned on, and the value is reflected in the buffer enable register when the flash memory is accessed. In this way, it is possible to specify on which side of the buffer 13 the device exists before writing to the register. Therefore, it is possible to deal with both the device immediately after power-on, whether it is inside or outside the buffer 13.
[0010]
Next, when a new register is provided, the same number of bits as the buffer enable is provided in the register map. The address is set at a predetermined address. When “1” is set in the register, when the area is accessed, the power supply of the output buffer is switched and output with 5.0 V amplitude. Conversely, when “0” is set, the output is 3.3V amplitude. As an operation, when accessing the local bus device with an instruction from the CPU, if the address is decoded, the bit corresponding to the access area of the register is referred to, and the address, read signal, write signal, chip select signal, data signal The amplitude of the control signal is switched. In addition, a 3.3V compatible device is placed outside the buffer, and a 5.0V compatible device is placed inside the buffer. By doing so, a signal having an amplitude of 5.0 V is not applied to the device outside the buffer. Therefore, since the input level is a CMOS level input IC and a device with a 5.0V power supply is accessed, the control signal amplitude can be set to 5.0V. Conditions are more relaxed when selecting a device, and a CMOS level input device can also be used.
[0011]
In addition, this invention is not limited to the said Example, It cannot be overemphasized that various deformation | transformation and substitution are possible if it is description in a claim.
[0012]
【The invention's effect】
As described above, according to the present invention, a CPU, a plurality of devices having different power supply voltages , an address decoder circuit that outputs a selection signal for selecting the device, and at least one of the devices are connected to the device. an electronic device having a buffer that converts the amplitude of the control signal, the address decoder circuit includes a buffer control signal output unit that outputs a buffer control signal for controlling the buffer, for each device selected by the selection signal, the device It has a buffer enable register that specifies the position of the buffer as viewed from the above and an input signal terminal to which an input signal is supplied. When the power is turned on, it depends on the preset signal level of the input signal terminal, and other than when the power is turned on Refers to the predetermined address set in the buffer enable register and outputs the buffer control signal. Controlling whether the revertive. When the CPU accesses the device, the address decoder circuit switches the amplitude of the control signal to the device according to a predetermined address set in the buffer enable register. Furthermore, devices having the same power supply voltage are connected to each side of the buffer. Therefore, it is possible to provide an electronic device having an address decoder circuit that can change the wiring without remaking the ASIC, and can flexibly cope with the progress of the process technology and the lowering of the voltage in the future.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a main configuration of an electronic device including an address decoder circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a partial configuration of FIG.
[Explanation of symbols]
11: CPU, 12: ASIC, 13: buffer,
14: Flash memory, 15: Non-volatile memory, 16: UART.

Claims (3)

A CPU, a plurality of power supply voltages different devices, an address decoder circuit for outputting a selection signal for selecting the device, the at least one connection device, a buffer that converts the amplitude of the control signal to the device In an electronic device having
The address decoder circuit includes: a buffer control signal output unit that outputs a buffer control signal that controls the buffer; and a buffer enable register that specifies a position of the buffer as viewed from the device for each device selected by the selection signal And an input signal terminal to which an input signal is supplied,
Whether to activate the buffer control signal according to the preset signal level of the input signal terminal when the power is turned on, or with reference to a predetermined address set in the buffer enable register except when the power is turned on An electronic device characterized by controlling whether or not.   The electronic apparatus according to claim 1, wherein when the CPU accesses the device, the address decoder circuit switches an amplitude of a control signal to the device according to a predetermined address set in the buffer enable register.   The electronic apparatus according to claim 1, wherein devices having the same power supply voltage are connected to each side of the buffer.

Images