JP3926964B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an ESD (Electro-Static Discharge) protection element for protecting a semiconductor element from electrostatic breakdown, for example, and a method for manufacturing the same.
[0002]
[Prior art]
For example, an ESD protection element is provided in the input portion of the semiconductor device, and even when high static electricity is applied to the input pad, the ESD protection element prevents the elements in the chip from being destroyed. As an ESD protection element of this type, when a high voltage is applied between the source region and the drain region recently, a depletion layer formed between the drain region and the channel reaches the source region, and a punch-through current flows. The type that works is developed.
[0003]
FIG. 14 shows a semiconductor device having a conventional punch-through type ESD protection element. For example, a plurality of element isolation regions 2, 3, 4, 5, 6 are formed in the surface region of the P-type semiconductor substrate 1. An N channel MOS transistor 9 and a P channel MOS transistor 10 having an LDD (Lightly Doped Drain Region) structure are formed in the internal circuit region 7 of the semiconductor substrate 1. In the input circuit region 8, an N channel MOS transistor 11 and a P channel MOS transistor 12 are formed as ESD protection elements. These transistors 11 and 12 have not a LDD structure but a single drain structure. The input pad 13 is connected to the drain regions of the transistors 11 and 12, and is connected to the transistors in the internal circuit region 7 through, for example, the inverter circuit 14. Further, the gate electrodes and the source regions of the transistors 11 and 12 are grounded.
[0004]
In the above configuration, when a high voltage is applied to the input pad 13, for example, a depletion layer formed between the drain region and the channel of the transistor 11 reaches the source region, and a punch-through current flows. For this reason, a current path is formed between the input pad 13, the drain region of the transistor 11, the source region, and the ground, and a current associated with the high voltage applied to the input pad 13 flows through this path.
[0005]
[Problems to be solved by the invention]
In the conventional semiconductor device, the transistors 9 and 10 in the internal circuit region 7 have an LDD structure, and the transistors 11 and 12 constituting the ESD protection element in the input circuit region 8 are formed by a single drain structure transistor. . For this reason, it is difficult to form the transistors 9 and 10 and the transistors 11 and 12 as ESD protection elements by the same manufacturing process, which increases the manufacturing process.
[0006]
Further, the impurities implanted in the source region and drain region of the transistors 11 and 12 diffuse in the annealing process, and part of them reach the lower portion of the gate electrode and overlap the gate electrode. For this reason, when a high voltage is applied to the drain region, a high electric field is applied between the gate electrode and the drain region, and this overlap portion has a problem of dielectric breakdown.
[0007]
  The present invention has been made to solve the above-described problems, and an object of the present invention is to form an internal circuit region transistor and a transistor as an ESD protection element while suppressing an increase in manufacturing steps.Is possibleIt is an object to provide a functional semiconductor device and a method for manufacturing the same.
[0008]
[Means for Solving the Problems]
  An aspect of the semiconductor device of the present invention is as follows.Formed in the input circuit area of the boardA first N-channel transistor having a drain connected to the input pad and a gate and a source grounded, and a first P-channel transistor;Formed in the internal circuit area of the substrateA second N-channel transistor having a LDD structure, and a second P-channel transistor, wherein the first N-channel transistor and the first P-channel transistor have an LDD structure, and the impurity concentration of the channel region is Set lower than the impurity concentration of the second N-channel transistor and the second P-channel transistor;The impurity concentration of the source / drain regions of the LDD structure of the first N-channel transistor and the first P-channel transistor depends on the source / drain of the LDD structure of the second N-channel transistor and the second P-channel transistor. It is characterized by being equal to the impurity concentration of the region.
[0010]
  Manufacturing method of semiconductor device of the present inventionThe first aspect ofForming a plurality of element isolation regions in a surface region of the first conductivity type semiconductor substrate, a first conductivity type first well region, and a second conductivity type second in the internal circuit region of the semiconductor substrate. 2 well regions are formed and formed in the input circuit region of the semiconductor substrate.Impurity concentration is lower than that of the first well region and the second well region.Forming a third well region of the first conductivity type and a fourth well region of the second conductivity type; forming a gate insulating film on the semiconductor substrate; and forming a polysilicon film on the gate insulating film The polysilicon film and the gate insulating film are etched to form first, second, third, and fourth gate electrodes on the first, second, third, and fourth well regions. And forming a second conductivity type first impurity diffusion region by introducing a second conductivity type impurity into the first and third well regions using the first and third gate electrodes as a mask. And a step of introducing a first conductivity type impurity into the second and fourth well regions using the second and fourth gate electrodes as a mask to form a first conductivity type first impurity diffusion region. And forming a sidewall insulating film on the side surfaces of the first to fourth gate electrodes The second conductivity type impurity is introduced into the first and third well regions using the side wall insulating film as a mask, and the second conductivity type impurity having a concentration higher than that of the first impurity diffusion region of the second conductivity type is introduced. The second impurity diffusion region is formed, and the first conductivity type impurity having a concentration higher than that of the first impurity diffusion region of the first conductivity type is formed in the second and fourth well regions using the sidewall insulating film as a mask. And forming a second impurity diffusion region of the first conductivity type,The second conductivity type first and second impurity diffusion regions formed in the third well region forming the source / drain regions of the LDD structure and the fourth well region, respectively. Of the first and second impurity diffusion regions of the first conductivity type, the drain region formed in the third and fourth well regions is connected to an input pad, and the third and fourth gate electrodes and Grounding the source region formed in the third and fourth well regions;TheIt is characterized by comprising.
[0011]
  According to a second aspect of the method for manufacturing a semiconductor device of the present invention, there is provided a step of forming a plurality of element isolation regions in a surface region of a first conductivity type semiconductor substrate, and a first conductivity type in an internal circuit region of the semiconductor substrate. A first well region and a second well type second well region are formed, and a first impurity region having an impurity concentration lower than that of the first well region and the second well region in the input circuit region of the semiconductor substrate. Forming a conductive type third well region and a second conductive type fourth well region, forming a gate insulating film on the semiconductor substrate, and forming a polysilicon film on the gate insulating film; And etching the polysilicon film and the gate insulating film to form first, second, third, and fourth gate electrodes on the first, second, third, and fourth well regions. And the first and third gate electrodes as a mask Then, a second conductivity type impurity is introduced into the first and third well regions to form a second conductivity type first impurity diffusion region, and the second and fourth gate electrodes are used as a mask. Introducing a first conductivity type impurity into the second and fourth well regions to form a first impurity diffusion region of the first conductivity type; and sidewalls on the side surfaces of the first to fourth gate electrodes. A step of forming an insulating film; and introducing a second conductivity type impurity having a higher concentration than the first impurity diffusion region of the second conductivity type into the first well region using the sidewall insulating film as a mask, A second conductivity type impurity diffusion region is formed, and a first conductivity type impurity having a concentration higher than that of the first conductivity type first impurity diffusion region is introduced into the second well region using the sidewall insulating film as a mask. Forming the first conductivity type second impurity diffusion region, and A first impurity diffusion region of the second conductivity type formed in the third well region for forming a source / drain region as a DD region, and the first conductivity type formed in the fourth well region Of the first impurity diffusion regions, the drain regions formed in the third and fourth well regions are connected to an input pad, and the third and fourth gate electrodes and the third and fourth gate electrodes are connected. And grounding the source region formed in the well region.
  The third aspect of the method for manufacturing a semiconductor device of the present invention is:Forming a plurality of element isolation regions in a surface region of a first conductivity type semiconductor substrate; a formation region of a second conductivity type transistor in an internal circuit region of the semiconductor substrate; and a first conductivity type transistor in an input circuit region First conductivity type impurities are introduced into the formation region to form first conductivity type first and second well regions, and the first conductivity type transistor formation region in the internal circuit region of the semiconductor substrate is formed in the first conductivity type. By introducing a second conductivity type impurity, a second conductivity type third well region is formed, and by introducing a second conductivity type impurity into the second well region, the third well region is formed. A step of forming a second well region of a second conductivity type having a lower impurity concentration, a step of forming a gate insulating film on the semiconductor substrate, a polysilicon film on the gate insulating film, Silicon film and front Etching the gate insulating film to form first, second, third, and fourth gate electrodes on the first, third, and fourth well regions and on the semiconductor substrate; and Using the fourth gate electrode as a mask, a second conductivity type impurity is introduced into the first well region and the semiconductor substrate to form a second conductivity type first impurity diffusion region, and the second, Using the third gate electrode as a mask, introducing a first conductivity type impurity into the third and fourth well regions to form a first conductivity type first impurity diffusion region; and A step of forming a sidewall insulating film on a side surface of the fourth gate electrode, and a first impurity diffusion region of the second conductivity type in the first well region and the semiconductor substrate using the sidewall insulating film as a mask. The second conductivity type is introduced by introducing a second conductivity type impurity having a high concentration. Forming a second impurity diffusion region, and using the sidewall insulating film as a mask, the first conductivity type impurity having a concentration higher than that of the first impurity diffusion region of the first conductivity type in the third and fourth well regions; And forming a second impurity diffusion region of the first conductivity type, and a first and second of the second conductivity type formed in the semiconductor substrate respectively forming the source / drain regions of the LDD structure. Of the first conductivity type first and second impurity diffusion regions formed in the second well diffusion region and the fourth well region, and formed in the semiconductor substrate and the fourth well region. Connecting the drain region to an input pad, and grounding the source region formed in the third and fourth gate electrodes, the semiconductor substrate and the fourth well region.
  According to a fourth aspect of the method for manufacturing a semiconductor device of the present invention, a surface region of a semiconductor substrate of the first conductivity type is formed. A step of forming a plurality of element isolation regions; a first conductivity type impurity in a formation region of a second conductivity type transistor in an internal circuit region of the semiconductor substrate and a formation region of a first conductivity type transistor in an input circuit region; Introducing and forming first and second well regions of the first conductivity type, and introducing a second conductivity type impurity into the formation region of the first conductivity type transistor in the internal circuit region of the semiconductor substrate, A second conductivity type third well region is formed, and a second conductivity type impurity is introduced into the second well region, whereby a second conductivity type second well having a lower impurity concentration than the third well region is formed. Forming a well region, forming a gate insulating film on the semiconductor substrate, forming a polysilicon film on the gate insulating film, etching the polysilicon film and the gate insulating film, Above Forming the first, second, third, and fourth gate electrodes on the first, third, and fourth well regions and the semiconductor substrate; and using the first and fourth gate electrodes as a mask, A second conductivity type impurity is introduced into the first well region and the semiconductor substrate to form a second conductivity type first impurity diffusion region, and the second and third gate electrodes are used as a mask. Introducing a first conductivity type impurity into the third and fourth well regions to form a first impurity diffusion region of the first conductivity type; and sidewalls on the side surfaces of the first to fourth gate electrodes. A step of forming an insulating film; and introducing a second conductivity type impurity having a higher concentration than the first impurity diffusion region of the second conductivity type into the first well region using the sidewall insulating film as a mask, A conductive type second impurity diffusion region is formed, and the sidewall insulating film is used as a mask. Introducing a first conductivity type impurity having a concentration higher than that of the first conductivity type first impurity diffusion region into the third well region to form a first conductivity type second impurity diffusion region; A first impurity diffusion region of the second conductivity type formed in the semiconductor substrate for forming a source / drain region as an LDD region, and a first first of the first conductivity type formed in the fourth well region. Of the impurity diffusion regions, the drain region formed in the semiconductor substrate and the fourth well region is connected to an input pad, and the third and fourth gate electrodes, the semiconductor substrate and the fourth well region are connected to the input pad. And grounding the formed source region.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0026]
(First embodiment)
First, the structure of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. In FIG. 1, for example, a P-type well region 21 is formed in a P-type semiconductor substrate 20, and field oxide films 22, 23, 24, 25, 26 as element isolation regions are formed on the surface region of the P-type well region 21. Is formed. An LDD-structured N-channel MOS transistor N1 and an LDD-structured P-channel MOS transistor P1 are formed in the internal circuit region 27 of the semiconductor substrate 20, and an input circuit region 28 includes an N-channel MOS transistor N2 as an ESD protection element and A P-channel MOS transistor P2 is formed. These transistors N2 and P2 also have an LDD structure like the transistors N1 and P1.
[0027]
The transistor N1 includes a gate electrode 37 and a low impurity concentration LDD region n formed in the P-type well region 31.^-And high impurity concentration source / drain regions n⁺It is comprised by. The transistor P1 includes a gate electrode 38 and an LDD region p formed in the N-type well region 34.^-, And source / drain regions p⁺It is comprised by. Further, the transistor P2 includes a gate electrode 39 and an LDD region p formed in an N well region 35 formed by ion implantation of an N-type impurity into the P well region 32, for example.^-, And source / drain regions p⁺It is comprised by. The transistor N2 includes a gate electrode 40 and an LDD region n formed in the P well region 21.^-And source / drain regions n⁺It is comprised by.
[0028]
Side wall insulating films 41 are respectively formed on the side surfaces of the gate electrodes 37, 38, 39, and 40. For example, a cobalt silicide layer is formed on the upper surfaces of the gate electrodes 37, 38, 39, and 40 and the upper surfaces of the source / drain regions. 42 is formed.
[0029]
The input pad 43 is connected to the drains of the transistors N2 and P2 constituting the ESD protection element, and is connected to the transistor in the internal circuit region 27 via the inverter circuit 44. Further, the gate electrodes and sources of the transistors N2 and P2 are grounded.
[0030]
FIG. 2 shows the operation of the ESD protection element shown in FIG. 1, and the same parts as those in FIG. When, for example, a positive high voltage is applied to the input pad 43 by electrostatic discharge, the depletion layer DL formed between the drain region and the channel of the N-channel MOS transistor N2 reaches the source region, and a punch-through current flows. For this reason, a current path is formed between the input pad 43, the drain region of the transistor N2, the source region, and the ground, and a discharge current associated with the high voltage applied to the input pad 43 flows through this path. Therefore, the transistor formed in the internal circuit region is protected.
[0031]
Next, a method for manufacturing the semiconductor device having the above configuration will be described with reference to FIGS.
[0032]
As shown in FIG. 3A, for example, a P-type well region 21 is formed in a P-type semiconductor substrate 20, and field oxide films 22 and 23 as element isolation regions are formed on the surface region of the P-type well region 21. , 24, 25, 26 are formed. Thereafter, a silicon oxide film 27 is formed on the entire surface of the semiconductor substrate 20. Next, a resist film 30 is formed on the entire surface, and this resist film 30 covers the formation region of the P channel MOS transistor P1 in the internal circuit region 28 and the formation region of the N channel transistor N2 as an ESD protection element. Is patterned. For example, boron is ion-implanted in order to form the P-type well region 31 in the formation region of the N-channel MOS transistor N1 and the P-channel MOS transistor P2 using this resist pattern as a mask. The boron dose is, for example, 5 × 10.¹²cm^-2It is.
[0033]
Thereafter, as shown in FIG. 3B, the resist film 30 is removed, and a resist film 33 is formed on the entire surface of the semiconductor substrate 20. The resist film 33 is patterned so as to cover the formation region of the N channel MOS transistor N1 in the internal circuit region 28 and the formation region of the N channel transistor N2 as an ESD protection element. For example, phosphorus is ion-implanted in order to form the N-type well regions 34 and 35 in the formation region of the P-channel MOS transistors P1 and P2 using the resist pattern as a mask. The phosphorus dose is, for example, 7 × 10.¹²cm^-2It is.
[0034]
Here, in the formation region of the P-channel MOS transistor P2 constituting the ESD protection element, both the P-type impurity and the N-type impurity are ion-implanted, and the formation region of the N-channel MOS transistor N2 constituting the ESD protection element is Neither P-type impurities nor N-type impurities are implanted.
[0035]
Next, as shown in FIG. 4A, after the resist film 33 and the silicon oxide film 27 are removed, a silicon oxide film 27a as a gate insulating film is formed. A polysilicon film 36 is formed on the silicon oxide film 27a by, for example, a CVD (Chemical Vapor Deposition) method. At this time, the implanted ions are annealed to form P-type well regions 31 and 32 and N-type well regions 34 and 35 shallower than the P-type well regions 31 and 32. The boron concentration in the P-type well regions 31 and 32 is about 5 × 10 6 in the channel region of the N-channel MOS transistor.¹⁷cm^-3The phosphorus concentration in the N-type well region 34 is about 7 × 10 6 in the channel region of the P-channel MOS transistor.¹⁷cm^-3It is.
[0036]
The phosphorus concentration in the N-type well region 35 where the P-channel MOS transistor P2 as the ESD protection element is formed is about 2 × 10 6 in the channel region.¹⁷cm^-3Thus, the concentration is lower than the phosphorus concentration in the N-type well region 34. Further, boron and phosphorus are not ion-implanted in the region where the N-channel MOS transistor N2 as the ESD protection element is formed. For this reason, the impurity concentration of the channel region in which the transistor N2 is formed is about 1 × 10 5 that is the boron concentration of the P-type well region 21.¹⁷cm^-3It is said that.
[0037]
The polysilicon film 36 and the silicon oxide film 27a are etched by, for example, RIE (Reactive Ion Etching) using a resist film (not shown) patterned corresponding to the gate electrode as a mask, as shown in FIG. 4B. Gate electrodes 37, 38, 39, and 40 are formed. Here, the gate lengths of the gate electrodes 39 and 40 of the transistors P2 and N2 constituting the ESD protection element are set longer than the gate lengths of the gate electrodes 37 and 38 of the transistors N1 and P1 formed in the internal circuit region. When the gate lengths of the gate electrodes 37 and 38 of the transistors N1 and P1 are 0.25 μm, for example, the gate length of the gate electrode 39 of the transistor P2 is set to 0.3 μm, for example, and the gate length of the gate electrode 40 of the transistor N2 is For example, it is set to 0.35 μm. That is, the gate lengths of the gate electrodes 39 and 40 of the transistors P2 and N2 are set so that a discharge current accompanying a high voltage applied to the input pad at a desired voltage flows by the punch-through current. In this embodiment, by setting the gate length, desired characteristics satisfying the MIL standard and the EIAJ standard could be obtained.
[0038]
Next, as shown in FIG. 5A, N-type impurities such as phosphorus are ion-implanted into the P-well regions 31 and 21 using the gate electrodes 37 and 40 as masks, so that the LDD region n^-Is formed. Also, a P-type impurity such as boron is ion-implanted into the N well regions 34 and 35 using the gate electrodes 38 and 39 as a mask, so that the LDD region p^-Is formed. As is well known, the ion non-implanted region is covered with a resist film, for example. LDD region n^-The impurity concentration of, for example, 5 × 10¹⁹cm^-3And the LDD region p^-The impurity concentration of, for example, 5 × 10¹⁹cm^-3It is said that.
[0039]
Next, for example, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 20 by, for example, a CVD method. The silicon oxide film is selectively etched, and sidewall oxide films 41 are formed on the side surfaces of the gate electrodes 37, 38, 39, and 40 as shown in FIG.
[0040]
Thereafter, as shown in FIG. 6A, N-type impurities such as phosphorus are ion-implanted into the P well regions 31 and 21 using the side wall oxide film 41 as a mask, so that the source / drain regions n⁺Is formed. Further, a P-type impurity, for example, boron is ion-implanted into the N well regions 34 and 35 using the sidewall oxide film 41 as a mask, and the source / drain regions p⁺Is formed. As is well known, the ion non-implanted region is covered with a resist film, for example. Source / drain region n⁺The impurity concentration of, for example, 5 × 10²⁰cm^-3And the source / drain region p⁺The impurity concentration of, for example, 5 × 10²⁰cm^-3It is said that.
[0041]
Next, for example, a cobalt film is formed on the entire surface to a thickness of, for example, 15 nm by sputtering, and a cobalt silicide film 42 is formed on the surface of the source / drain region of each transistor and the upper surface of the gate electrode of each transistor by a known salicide process. Is formed. The thickness of the cobalt silicide film 42 is, for example, 50 nm, and the sheet resistance of the cobalt silicide film 42 on the gate electrode is, for example, 5Ω / sq. Set to
[0042]
Thereafter, wiring is formed by a well-known process. As shown in FIG. 1, the drains of the transistors N2 and P2 constituting the ESD protection element are connected to the input pad 43 and connected to the internal via the inverter circuit 44. It is connected to the transistor in the circuit area 27. Furthermore, the gate electrodes and sources of the transistors N2 and P2 are grounded.
[0043]
According to the first embodiment, the transistors N2 and P2 as the ESD protection elements have the same LDD structure as the transistors N1 and P1 formed in the internal circuit region 27. Therefore, the transistors N2 and P2 as the ESD protection elements can be manufactured by the same manufacturing process as the transistors N1 and P1 formed in the internal circuit region 27. Therefore, the manufacturing process can be simplified as compared with the conventional case where only the transistor as the ESD protection element is formed with a single drain structure.
[0044]
In addition, since the transistors N2 and P2 as the ESD protection elements have an LDD structure, the electric field between the drain / gate of these transistors N2 and P2 can be relaxed, and the reliability of the gate insulating film can be improved.
[0045]
Note that, in the region where the P-channel MOS transistor P2 as the ESD protection element is formed, both the P-type impurity and the N-type impurity are ion-implanted. However, the present invention is not limited to this. May be ion-implanted. In this case, the gate length of the gate electrode 39 may be set sufficiently short according to the N-type impurity concentration.
[0046]
In addition, the transistors N2 and P2 as ESD protection elements have high concentration source / drain regions n, similarly to the transistors N1 and P1 formed in the internal circuit region.⁺, P⁺However, the present invention is not limited to this. For example, the transistors N2 and P2 serving as ESD protection elements include high-concentration source / drain regions n.⁺, P⁺Without forming a low concentration region n^-, P^-It is good also as a structure of only. In such a configuration, the low concentration source / drain region n^-, P^-And the capacity of the substrate can be reduced. Therefore, the parasitic capacitance of the ESD protection element can be reduced, the ESD protection element can be prevented from being a bypass of the high frequency signal, and a semiconductor device capable of high speed operation can be configured.
[0047]
In the above manufacturing process, the manufacturing process of the N-channel MOS transistor and the P-channel MOS transistor can be interchanged.
[0048]
FIG. 7 shows a modification of the first embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described. In FIG. 1, the N-channel MOS transistor N <b> 2 as the ESD protection element is formed in the P-type well region 21. In contrast, in this example, a P-type well region 32a is further formed in the P-type well region 21, and an N-channel MOS transistor N2 is formed in the P-type well region 32a.
[0049]
In FIG. 1, a P channel MOS transistor P <b> 2 as an ESD protection element is formed in an N type well region 35 formed in a P type well region 32. On the other hand, in this example, a P-channel MOS transistor P2 is formed in the N-type well region 35a.
[0050]
The impurity concentration of the P-type well region 32a is set lower than the impurity concentration of the P-type well region 31, and the impurity concentration of the N-type well region 35a is set lower than the impurity concentration of the N-type well region 34. .
[0051]
Thus, by forming the N-channel MOS transistor N2 and the P-channel MOS transistor P2 as ESD protection elements in the dedicated well region, the impurity concentration of the P-type well region 32a and the N-type well region 35a can be easily increased. Can be set.
[0052]
(No.1 referenceExample)
  FIG. 8 shows the first aspect of the present invention.1 referenceAn example is shown.
[0053]
  First1 referenceThe example solves the problem that the insulating film is broken at the portion where the gate electrode and the drain region overlap. Specifically, by not forming an extension region (LDD region) in the ESD protection element, formation of an overlap portion between the gate electrode and the drain region is prevented, and thereby insulation between the gate electrode and the drain region of the ESD protection element is achieved. This prevents electrostatic breakdown of the film.
[0054]
  Referring to FIG.1 referenceA method for manufacturing a semiconductor device according to an example will be described.
[0055]
First, as shown in FIG. 8A, element isolation regions 72 and 73 are formed in the semiconductor substrate 71. In the semiconductor substrate 71, a P-type well region 74 is formed in an N-channel transistor formation region 70a in the internal circuit region. For example, an ESD protection element formation region 70c made of a P-channel transistor in the input circuit region, and an internal circuit region N-type well regions 75 and 76 are formed in the P-channel transistor formation region 70b. Further, a plurality of gate electrodes 78 made of, for example, polysilicon are formed on the semiconductor substrate 71 via the gate insulating film 77.
[0056]
Although the case where the ESD protection element is constituted by a P-channel transistor will be described, the N-channel transistor is also formed by the same method as that for the P-channel transistor.
[0057]
Next, as shown in FIG. 8B, impurities are implanted into the semiconductor substrate 71 using the gate electrode 78 as a mask. As a result, an N-type extension diffusion layer 79 as a shallow junction is formed in the P-type well region 74, and a P-type extension diffusion layer 80 is formed in the N-type well region 76. At this time, a patterned resist film (not shown) is used to prevent impurities from being implanted into the ESD protection element formation region 70c during ion implantation. That is, when the N-type extension diffusion layer 79 is formed, the ESD protection element formation region 70c and the P-channel transistor formation region are covered with the resist film. When the P-type extension diffusion layer 80 is formed, the ESD protection element formation region 70c and the N-channel transistor formation region are covered with a resist film. As a result, as shown in FIG. 8B, a structure can be formed in which no extension diffusion layer exists only in the ESD protection element formation region 70c. The impurity concentration of the N-type extension diffusion layer 79 and the P-type extension diffusion layer 80 is set lower than the impurity concentration of the source / drain regions described later.
[0058]
Next, as shown in FIG. 8C, sidewall insulating films 81 made of, for example, a silicon nitride film are formed on the side surfaces of the gate electrode 78, respectively. The sidewall insulating film 81 is not limited to a silicon nitride film, and a silicon oxide film or the like can also be used.
[0059]
Thereafter, as shown in FIG. 8D, N-type impurities and P-type impurities are sequentially ion-implanted into the semiconductor substrate 71 using the sidewall insulating film 81 as a mask to form deep source / drain regions. The That is, an N-type source / drain region 82 is formed in the P-type well region 74, and a P-type source / drain region 83 is formed in the N-type well region 76. Further, a P-type source / drain region 84 is formed in the N-type well region 75. The ESD protection element 85 made of a P-channel transistor formed in this way does not have an extension diffusion layer. Similarly, an ESD protection element made of an N-channel transistor (not shown) formed in the same manner does not have an extension diffusion layer. As in the first embodiment, an input pad is connected to the drain region of the ESD protection element, and the source region and the gate electrode are grounded.
[0060]
  Above1 referenceAccording to the example, the transistor forming the internal circuit has the extension diffusion layer, whereas the transistor forming the ESD protection element 85 does not have the extension diffusion layer. For this reason, the source / drain region 84 of the ESD protection element 85 is located outside the boundary between the gate electrode and the sidewall insulating film, and does not have a portion overlapping the gate electrode. Therefore, even when a high voltage is applied to the drain region, it is possible to prevent a high electric field from being generated between the gate electrode and the drain as in the conventional case. Therefore, destruction of the ESD protection element 85 can be prevented.
[0061]
Further, the ESD protection element 85 has an advantage that it can be formed only by a change equivalent to or minimal in the manufacturing process of the MOSFET constituting the internal circuit.
[0062]
(No.Reference of 2Example)
  9 and 10 show the first aspect of the present invention.Reference of 2An example is given1 referenceThe same parts as those in the example are denoted by the same reference numerals.
[0063]
  FirstReference of 2The example ESD protection element prevents the overlap portion between the gate electrode and the drain region from being formed by removing the gate electrode from the MOSFET type ESD protection element.
[0064]
  Referring to FIG. 9 and FIG.Reference of 2The manufacturing method of the ESD protection element according to the example will be described.
[0065]
First, as shown in FIG. 9A, element isolation regions 72 and 73 are formed in the semiconductor substrate 71. In the semiconductor substrate 71, a P-type well region 74 is formed in an N-channel transistor formation region 70a. For example, an ESD protection element formation region 70c composed of a P-channel transistor and an N-channel transistor formation region 70b include an N-type transistor region 70a. Mold well regions 75 and 76 are formed. Further, a plurality of gate electrodes 78 made of, for example, polysilicon are formed on the semiconductor substrate 71 via the gate insulating film 77.
[0066]
Next, as shown in FIG. 9B, impurities are implanted into the semiconductor substrate 71 using the gate electrode 78 as a mask. As a result, an N-type extension diffusion layer 79 is formed in the P-type well region 74, and P-type extension diffusion layers 80 a and 80 b are formed in the N-type well regions 75 and 76.
[0067]
Next, as shown in FIG. 9C, a sidewall insulating film 81 made of, for example, a silicon nitride film is formed on the side surface of the gate electrode 78 in the same manner as in the first embodiment.
[0068]
Thereafter, as shown in FIG. 9D, N-type impurities and P-type impurities are sequentially ion-implanted into the semiconductor substrate 71 using the sidewall insulating film 81 as a mask. As a result, an N-type source / drain region 82 is formed in the P-type well region 74, and a P-type source / drain region 83 is formed in the N-type well region 76. Further, a P-type source / drain region 84 is formed in the N-type well region 75.
[0069]
Next, the N channel transistor formation region 70a and the P channel transistor formation region 70b are covered with a resist film (not shown), and the ESD protection element formation region 70c is exposed. In this state, the gate electrode 78 and the sidewall insulating film 81 in the ESD protection element formation region 70c are removed by etching.
[0070]
That is, as shown in FIG. 10, the ESD protection element 85 formed as described above has an extension region and a source / drain region like the transistor in the internal circuit part, and does not have a gate electrode. It is configured.
[0071]
  AboveReference of 2According to an example, the ESD protection element 85 does not have a gate electrode. For this reason, since there is no overlap part of a gate electrode and a source / drain region, it can prevent that a high electric field concentrates on the ESD protection element 85, and can prevent destruction of an ESD protection element.
[0072]
Further, the ESD protection element 85 has an advantage that it can be formed only by a change equivalent to or minimal in the manufacturing process of the MOSFET constituting the internal circuit.
[0073]
(No.3 referencesExample)
  11 and 12 show the first embodiment of the present invention.3 referencesAn example is shown1 referenceThe same parts as those in the example are denoted by the same reference numerals.
[0074]
  First3 referencesIn the ESD protection element shown in the example, ion implantation into the formation region of the ESD protection element is performed using a resist film as a mask instead of the gate electrode. An ESD protection element having no gate electrode is formed by such a method.
[0075]
  Referring to FIG. 11 and FIG.3 referencesThe manufacturing method of the ESD protection element which concerns on an example is demonstrated.
[0076]
First, as shown in FIG. 11A, element isolation regions 72 and 73 are formed in the semiconductor substrate 71. In the semiconductor substrate 71, a P-type well region 74 is formed in an N-channel transistor formation region 70a. For example, an ESD protection element formation region 70c composed of a P-channel transistor and an N-channel transistor formation region 70b include an N-type transistor region 70a. Mold well regions 75 and 76 are formed. Further, a plurality of gate electrodes 78 made of, for example, polysilicon are formed on the semiconductor substrate 71 via the gate insulating film 77. At this time, no gate electrode is formed in the ESD protection element formation region 70c.
[0077]
Next, as shown in FIG. 11B, impurities are implanted into the semiconductor substrate 71 using the gate electrode 78 as a mask. As a result, an N-type extension diffusion layer 79 is formed in the P-type well region 74, and a P-type extension diffusion layer 80 is formed in the N-type well region 76. At this time, a patterned resist film (not shown) is used so that impurities are not implanted into the ESD protection element portion during ion implantation. That is, when the N-type extension diffusion layer 79 is formed, the ESD protection element formation region 70c and the P-channel transistor formation region 70b are covered with a resist film. When the P-type extension diffusion layer 80 is formed, the ESD protection element formation region 70c and the N-channel transistor formation region 70a are covered with a resist film. As a result, as shown in FIG. 11B, it is possible to form a structure in which no extension diffusion layer exists only in the ESD protection element.
[0078]
Next, as shown in FIG. 11C, sidewall insulating films 81 made of, for example, a silicon nitride film are formed on the side surfaces of the gate electrode 78, respectively.
[0079]
Thereafter, an N-type source / drain region and a P-type source / drain region are formed.
[0080]
FIG. 12A shows a case where a P-type source / drain region is formed. In this case, a P-type impurity is ion-implanted into the P-channel transistor formation region 70b using the sidewall insulating film 81 as a mask. In addition, in the ESD protection element formation region 70c, a resist film 86 patterned corresponding to the formation position of the gate electrode is formed, and P-type impurity ions are implanted using the resist film 86 as a mask. Further, the N channel transistor formation region 70 a is covered with a resist film 86. In this manner, a P-type source / drain region 83 is formed in the N-type well 76, and a P-type source / drain region 84 is formed in the N-type well 75.
[0081]
FIG. 12A shows a case where an ESD protection element made of a P-channel transistor is formed. However, in the case of forming an ESD protection element composed of an N-channel transistor, a resist film patterned so as to cover the gate electrode position in the ESD protection element formation region and the P-channel transistor formation region 70b is formed. N-type impurity ions may be implanted using as a mask. As a result, an N-type source / drain region 82 is formed in the P-type well region 74, and an N-type source / drain region (not shown) is formed in the formation region of the ESD protection element composed of an N-channel transistor.
[0082]
At this time, the width of the resist film provided in the formation region of the ESD protection element needs to be adjusted so as to be the optimum condition for the ESD protection operation in consideration of the impurity concentration of the well. Specifically, under normal operating conditions, when the ESD protection element is turned off and a high voltage is applied to the drain region of the ESD protection element to destroy the elements of the internal circuit, the punch is quickly punched through and the charge is grounded. It is necessary to escape. For this reason, the width | variety of the resist film which enables such operation | movement is required.
[0083]
Finally, as shown in FIG. 12B, the resist film 86 is removed.
[0084]
As in the first embodiment, the input pad is connected to the drain region of the ESD protection element 85 formed of the P-channel transistor formed as described above, and the source region is grounded. Further, the upper portion of the ESD protection element 85 is covered with an insulating film in the same manner as the internal circuit.
[0085]
  Above3 referencesAccording to the example, the ESD protection element 85 does not have a gate electrode and has a source / drain region 84 having a conductivity type opposite to that of the well 75. For this reason, it is possible to avoid overlap between the gate electrode and the drain region, and it is possible to prevent the ESD protection element from being destroyed when a high voltage is applied to the drain region.
[0086]
  Also thisreferenceIn the case of the example manufacturing method, the gate electrode is not formed in the formation region of the ESD protection element.Reference of 2As in the example, it is not necessary to remove the gate electrode of the ESD protection element. Therefore, there is an advantage that the manufacturing process can be reduced.
[0087]
  The abovereferenceIn the example, the ion implantation into the formation region of the ESD protection element was performed when the source / drain region was formed. However, the present invention is not limited to this, and when forming the extension region, a mask may be formed with a resist in the formation region of the ESD protection element, and ion implantation may be performed.
[0088]
(No.4 referencesExample)
  FIG. 13 shows the first aspect of the present invention.4 referencesAn example is given3 referencesThe same parts as those in the example are denoted by the same reference numerals. thisreferenceThe example is characterized in that impurity ions are implanted into the formation region of the ESD protection element using a salicide block film.
[0089]
  Referring to FIG.4 referencesThe manufacturing method of the ESD protection element which concerns on an example is demonstrated. thisreferenceIn the example, the process until the extension diffusion layer is formed is3 referencesSimilar to the example.
[0090]
That is, element isolation regions 72 and 73 are formed in a semiconductor substrate 71 as shown in FIG. In the semiconductor substrate 71, a P-type well region 74 is formed in an N-channel transistor formation region 70a. For example, an ESD protection element formation region 70c composed of a P-channel transistor and an N-channel transistor formation region 70b include an N-type transistor region 70a. Mold well regions 75 and 76 are formed. Further, a plurality of gate electrodes 78 made of, for example, polysilicon are formed on the semiconductor substrate 71 via the gate insulating film 77. At this time, no gate electrode is formed in the ESD protection element formation region 70c.
[0091]
Next, as shown in FIG. 13B, impurities are implanted into the semiconductor substrate 71 using the gate electrode 78 as a mask. As a result, an N-type extension diffusion layer 79 is formed in the P-type well region 74, and a P-type extension diffusion layer 80 is formed in the N-type well region 76.
[0092]
Next, as shown in FIG. 13C, sidewall insulating films 81 made of, for example, a silicon nitride film are formed on the side surfaces of the gate electrode 78, respectively. At this time, in the formation region 70c of the ESD protection element, an insulating film as a salicide formation blocking layer having the same shape as the gate electrode obtained by patterning the sidewall insulating film corresponding to the formation position of the gate electrode 90 is formed.
[0093]
That is, for example, after a silicon nitride film is deposited on the entire surface of the semiconductor substrate 71, a resist film patterned corresponding to the formation position of the gate electrode is formed in the ESD protection element formation region 70c. The insulating film 90 shown in FIG. 13C is formed by etching, for example, by RIE using this resist film as a mask.
[0094]
The insulating film 90 as the salicide formation blocking layer is formed, for example, when the silicide layer is formed on the source / drain regions and the gate electrode by self-alignment in the ESD protection element formation region 70c at the gate electrode formation position. Is prevented from being formed. In this embodiment, the side wall insulating film 81 and the insulating film 90 are formed in the same process, but may be performed in separate processes. For example, after the resistor is formed of polysilicon, the insulating film 90 may be formed when preventing a silicide layer from being formed on the resistor.
[0095]
Thereafter, an N-type source / drain region and a P-type source / drain region are formed. At this time, impurity ions are implanted in the ESD protection element formation region 70c using the insulating film 90 as a mask. In this way, N-type source / drain regions 82 are formed in the P-type well 74. A P-type source / drain region 83 is formed in the N-type well 76, and a P-type source / drain region 84 is formed in the N-type well 75.
[0096]
  Above4 referencesAccording to the example, the ESD protection element 85 does not have a gate electrode, has an insulating film 90 made of a salicide block layer, and has a source / drain region 84 having a conductivity type opposite to that of the well 75. For this reason, it is possible to avoid overlap between the gate electrode and the drain region, and it is possible to prevent the ESD protection element from being destroyed when a high voltage is applied to the drain region.
[0097]
Further, the ESD protection element 85 has an advantage that it can be formed only by a change equivalent to or minimal in the manufacturing process of the MOSFET constituting the internal circuit.
[0098]
In addition, this invention is not limited to the said Example, Of course, various deformation | transformation implementation is possible in the range which does not change the summary of invention.
[0099]
【The invention's effect】
  As described above in detail, according to the present invention, an increase in the number of manufacturing steps can be suppressed and a transistor in an internal circuit region and a transistor as an ESD protection element can be formed.Is possibleCapable semiconductor devices and manufacturing methods thereof.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device of the present invention.
FIG. 2 is a diagram showing an operation of the ESD protection element shown in FIG.
FIGS. 3A and 3B are cross-sectional views showing manufacturing steps of the semiconductor device shown in FIG.
4 (a) and 4 (b) are cross-sectional views showing manufacturing steps subsequent to FIG. 3 (b).
FIGS. 5A and 5B are cross-sectional views showing manufacturing steps subsequent to FIG.
6 (a) and 6 (b) are cross-sectional views showing manufacturing steps subsequent to FIG. 5 (b).
FIG. 7 is a cross-sectional view showing a modification of FIG.
FIG. 8 (a) to FIG. 8 (d) show the first of the present invention.1 referenceSectional drawing which shows an example and shows in order of a manufacturing process.
FIG. 9 (a) to FIG. 9 (d) show the first of the present invention.Reference of 2Sectional drawing which shows an example and shows in order of a manufacturing process.
10 is a cross-sectional view showing a manufacturing step that follows FIG. 9 (d). FIG.
FIG. 11 (a) to FIG. 11 (c) show the first of the present invention.3 referencesSectional drawing which shows an example and shows in order of a manufacturing process.
12 (a) and 12 (b) are cross-sectional views showing manufacturing steps subsequent to FIG. 11 (c).
FIG. 13 (a) to FIG. 13 (d) show the first of the present invention.4 referencesSectional drawing which shows an example and shows in order of a manufacturing process.
FIG. 14 is a cross-sectional view illustrating an example of a conventional semiconductor device.
[Explanation of symbols]
    20 ... Semiconductor substrate,
    21 ... P-type well region,
    22, 23, 24, 25, 26 ... field oxide film,
    27. Internal circuit area,
    28: Input circuit area,
    31, 32 ... P-type well region,
    34, 35 ... N-type well region,
    37-40 ... gate electrode,
    n^-, P^-... LDD region,
    n⁺, P⁺... source / drain regions,
    41 ... sidewall insulating film,
    42 ... cobalt silicide layer,
    43 ... Input pad,
    N1, N2 ... N channel MOS transistors,
    P1, P2 ... P-channel MOS transistors,
    71 ... Semiconductor substrate,
    74: P-type well region,
    75, 76 ... N-type well region,
    78 ... Gate electrode,
    79 ... N-type extension diffusion layer,
    80, 80a, 80b ... P-type extension diffusion layer,
    81 ... sidewall insulating film,
    82 ... N-type source / drain regions,
    83, 84... P-type source / drain regions,
    85 ... ESD protection element,
    86: Resist film,
    90: An insulating film made of a salicide block layer.

Claims (6)

A first N-channel transistor having a drain formed in an input circuit region of the substrate connected to an input pad, a gate and a source grounded, and a first P-channel transistor;
A second N-channel transistor having an LDD structure formed in an internal circuit region of the substrate, and a second P-channel transistor;
The first N-channel transistor and the first P-channel transistor have an LDD structure, and the impurity concentration of the channel region is set lower than the impurity concentration of the second N-channel transistor and the second P-channel transistor. The impurity concentration of the source / drain regions of the LDD structure of the first N-channel transistor and the first P-channel transistor is the same as that of the source / drain regions of the LDD structure of the second N-channel transistor and the second P-channel transistor. A semiconductor device characterized by being equal in impurity concentration.   2. The gate lengths of the first N-channel transistor and the first P-channel transistor are set to be longer than the gate lengths of the second N-channel transistor and the second P-channel transistor. The semiconductor device described. Forming a plurality of element isolation regions in a surface region of a first conductivity type semiconductor substrate;
Forming a first well region of a first conductivity type and a second well region of a second conductivity type in an internal circuit region of the semiconductor substrate; and forming the first well region in an input circuit region of the semiconductor substrate; and Forming a first conductivity type third well region and a second conductivity type fourth well region having an impurity concentration lower than that of the second well region;
Forming a gate insulating film on the semiconductor substrate;
A polysilicon film is formed on the gate insulating film, the polysilicon film and the gate insulating film are etched, and first, second, and second well regions are formed on the first, second, third, and fourth well regions. 3, forming a fourth gate electrode;
Using the first and third gate electrodes as a mask, a second conductivity type impurity is introduced into the first and third well regions to form a second conductivity type first impurity diffusion region, and the first A step of introducing a first conductivity type impurity into the second and fourth well regions using the second gate electrode as a mask and forming a first conductivity type first impurity diffusion region;
Forming a sidewall insulating film on a side surface of the first to fourth gate electrodes;
Using the side wall insulating film as a mask, a second conductivity type impurity having a higher concentration than the first impurity diffusion region of the second conductivity type is introduced into the first and third well regions. A second impurity diffusion region is formed, and the first conductivity type impurity having a higher concentration than the first impurity diffusion region of the first conductivity type is applied to the second and fourth well regions using the sidewall insulating film as a mask. Introducing and forming a second impurity diffusion region of the first conductivity type;
The second conductivity type first and second impurity diffusion regions formed in the third well region forming the source / drain regions of the LDD structure, respectively, and the first well region formed in the fourth well region. Of the first and second impurity diffusion regions of one conductivity type, the drain region formed in the third and fourth well regions is connected to an input pad, and the third and fourth gate electrodes and And grounding the source region formed in the third and fourth well regions. A method of manufacturing a semiconductor device, comprising: Forming a plurality of element isolation regions in a surface region of a first conductivity type semiconductor substrate;
Forming a first well region of a first conductivity type and a second well region of a second conductivity type in an internal circuit region of the semiconductor substrate; and forming the first well region in an input circuit region of the semiconductor substrate; and Forming a first conductivity type third well region and a second conductivity type fourth well region having an impurity concentration lower than that of the second well region;
Forming a gate insulating film on the semiconductor substrate;
A polysilicon film is formed on the gate insulating film, the polysilicon film and the gate insulating film are etched, and first, second, and second well regions are formed on the first, second, third, and fourth well regions. 3, forming a fourth gate electrode;
Using the first and third gate electrodes as a mask, a second conductivity type impurity is introduced into the first and third well regions to form a second conductivity type first impurity diffusion region, and the first A step of introducing a first conductivity type impurity into the second and fourth well regions using the second gate electrode as a mask and forming a first conductivity type first impurity diffusion region;
Forming a sidewall insulating film on a side surface of the first to fourth gate electrodes;
Using the sidewall insulating film as a mask, a second conductivity type impurity having a concentration higher than that of the first conductivity diffusion region of the second conductivity type is introduced into the first well region, and the second impurity diffusion of the second conductivity type is introduced. A first conductivity type impurity having a concentration higher than that of the first impurity diffusion region of the first conductivity type is introduced into the second well region using the sidewall insulating film as a mask. A step of forming two impurity diffusion regions;
A first impurity diffusion region of the second conductivity type formed in the third well region forming a source / drain region as an LDD region, respectively, and the first conductivity formed in the fourth well region. Of the first impurity diffusion region of the mold, the drain region formed in the third and fourth well regions is connected to an input pad, and the third and fourth gate electrodes and the third and fourth gate electrodes are connected. And a step of grounding the source region formed in the well region of the semiconductor device. Forming a plurality of element isolation regions in a surface region of a first conductivity type semiconductor substrate;
Impurities of the first conductivity type are introduced by introducing a first conductivity type impurity into the formation region of the second conductivity type transistor in the internal circuit region of the semiconductor substrate and the formation region of the first conductivity type transistor in the input circuit region. A second well region is formed, and a second conductivity type impurity is introduced into the formation region of the first conductivity type transistor in the internal circuit region of the semiconductor substrate, thereby forming a second well type third well region. Forming a second conductivity type fourth well region having an impurity concentration lower than that of the third well region by introducing and introducing a second conductivity type impurity into the second well region;
Forming a gate insulating film on the semiconductor substrate;
A polysilicon film is formed on the gate insulating film, the polysilicon film and the gate insulating film are etched, and the first and second well regions are formed on the first, third, and fourth well regions and on the semiconductor substrate. Forming the third and fourth gate electrodes;
A second conductivity type first impurity diffusion region is formed by introducing a second conductivity type impurity into the first well region and the semiconductor substrate using the first and fourth gate electrodes as a mask; Introducing a first conductivity type impurity into the third and fourth well regions using the second and third gate electrodes as a mask to form a first conductivity type first impurity diffusion region; ,
Forming a sidewall insulating film on a side surface of the first to fourth gate electrodes;
Using the sidewall insulating film as a mask, a second conductivity type impurity having a concentration higher than that of the first impurity diffusion region of the second conductivity type is introduced into the first well region and the semiconductor substrate, thereby providing a second conductivity type. The second impurity diffusion region is formed, and the first conductivity type having a higher concentration than the first impurity diffusion region of the first conductivity type is formed in the third and fourth well regions using the sidewall insulating film as a mask. Introducing an impurity to form a second impurity diffusion region of the first conductivity type;
The first conductivity formed in the first and second impurity diffusion regions of the second conductivity type and the fourth well region formed in the semiconductor substrate respectively forming the source / drain regions of the LDD structure. Of the first and second impurity diffusion regions of the mold, the drain region formed in the semiconductor substrate and the fourth well region is connected to an input pad, the third and fourth gate electrodes, and the semiconductor Grounding the substrate and the source region formed in the fourth well region;
A method for manufacturing a semiconductor device, comprising: Forming a plurality of element isolation regions in a surface region of a first conductivity type semiconductor substrate;
Second conductive transistor formation region and input circuit region in the internal circuit region of the semiconductor substrate First conductivity type impurities are introduced into the first conductivity type transistor formation region to form first conductivity type first and second well regions, and the first conductivity type in the internal circuit region of the semiconductor substrate is formed. By introducing a second conductivity type impurity into the transistor formation region, a second conductivity type third well region is formed, and by introducing the second conductivity type impurity into the second well region. Forming a second conductivity type fourth well region having an impurity concentration lower than that of the third well region;
Forming a gate insulating film on the semiconductor substrate;
A polysilicon film is formed on the gate insulating film, the polysilicon film and the gate insulating film are etched, and the first and second well regions are formed on the first, third, and fourth well regions and on the semiconductor substrate. Forming the third and fourth gate electrodes;
A second conductivity type first impurity diffusion region is formed by introducing a second conductivity type impurity into the first well region and the semiconductor substrate using the first and fourth gate electrodes as a mask; Introducing a first conductivity type impurity into the third and fourth well regions using the second and third gate electrodes as a mask to form a first conductivity type first impurity diffusion region;
Forming a sidewall insulating film on a side surface of the first to fourth gate electrodes;
Using the sidewall insulating film as a mask, a second conductivity type impurity having a concentration higher than that of the first conductivity diffusion region of the second conductivity type is introduced into the first well region, and the second impurity diffusion of the second conductivity type is introduced. A first conductivity type impurity having a concentration higher than that of the first conductivity type first impurity diffusion region is introduced into the third well region using the sidewall insulating film as a mask. A step of forming two impurity diffusion regions;
A first impurity diffusion region of the second conductivity type formed in the semiconductor substrate, which respectively forms a source / drain region as an LDD region, and a first conductivity type of the first conductivity type formed in the fourth well region. Of the one impurity diffusion region, the drain region formed in the semiconductor substrate and the fourth well region is connected to an input pad, and the third and fourth gate electrodes, the semiconductor substrate, and the fourth well region are connected. Grounding the source region formed in
A method for manufacturing a semiconductor device, comprising:

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