JP3929966B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP3929966B2 JP3929966B2 JP2003393695A JP2003393695A JP3929966B2 JP 3929966 B2 JP3929966 B2 JP 3929966B2 JP 2003393695 A JP2003393695 A JP 2003393695A JP 2003393695 A JP2003393695 A JP 2003393695A JP 3929966 B2 JP3929966 B2 JP 3929966B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01251—Changing the shapes of bumps
- H10W72/01255—Changing the shapes of bumps by using masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
11…半導体基板(シリコン基板)、
12…電極パッド(各デバイスの配線層の一部分)、
13…パッシベーション膜(SiN層又はPSG層)、
14…絶縁膜(ポリイミド樹脂層)、
15…金属薄膜(給電層/めっきベース膜)、
16…導体層(再配線層/再配線パターン)、
17…メタルポスト(Cuポスト)、
18…バリヤメタル層、
19…メタル層(W層、Mo層など)、
20…封止樹脂層、
21…外部接続端子(はんだバンプ)、
30…半導体ウエハ(シリコンウエハ)、
BL…ダイサーのブレード、
R1,R2…レジスト層(めっきレジスト)、
VH…開口部(ビアホール)。
Claims (4)
- シリコンからなる半導体ウエハの複数のデバイスが作り込まれている側の表面に、各デバイスの電極パッドが露出する開口部を有するように絶縁膜を形成する工程と、
次いで、該絶縁膜上に、前記電極パッドが露出する開口部を覆うように所要の形状にパターニングされた導体層を形成する工程と、
次いで、該導体層上に、該導体層の端子形成部分が露出する開口部を有するようにレジスト層を形成する工程と、
次いで、該レジスト層をマスクにして前記導体層の端子形成部分にメタルポストを形成する工程と、
次いで、前記半導体ウエハの前記メタルポストが形成されている側と反対側の面を研削して、所定の厚さになるまで薄化する工程と、
次いで、前記レジスト層を除去した後、前記半導体ウエハの薄化された面に、直接、当該半導体ウエハの線膨張係数に近い線膨張係数を有するモリブデンからなるメタル層を形成する工程と、
次いで、前記メタルポストの頂上部を露出させて封止樹脂でウエハ表面を封止する工程と、
次いで、前記メタルポストの頂上部に金属バンプを接合する工程と、
次いで、該金属バンプが接合された半導体ウエハを前記各デバイス単位に分割する工程とを含むことを特徴とする半導体装置の製造方法。 - 前記メタル層をスパッタリング又は蒸着により形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記メタルポストを形成する工程において、該メタルポストを形成した後、更に該メタルポストの頂上部にバリヤメタル層を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 請求項1に記載された半導体装置の製造方法により製造された半導体装置。
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003393695A JP3929966B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体装置及びその製造方法 |
| US10/988,508 US7417311B2 (en) | 2003-11-25 | 2004-11-16 | Semiconductor device and method of fabricating the same |
| TW093135090A TWI371061B (en) | 2003-11-25 | 2004-11-16 | Semiconductor device and method of fabricating the same |
| KR1020040096894A KR101043313B1 (ko) | 2003-11-25 | 2004-11-24 | 반도체 장치 및 그 제조 방법 |
| CNB2004100960178A CN100375232C (zh) | 2003-11-25 | 2004-11-25 | 半导体器件及其制造方法 |
| US11/546,285 US7468292B2 (en) | 2003-11-25 | 2006-10-12 | Method of making wafer level package structure by grinding the backside thereof and then forming metal layer on the ground side |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003393695A JP3929966B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体装置及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005158929A JP2005158929A (ja) | 2005-06-16 |
| JP3929966B2 true JP3929966B2 (ja) | 2007-06-13 |
Family
ID=34587559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003393695A Expired - Fee Related JP3929966B2 (ja) | 2003-11-25 | 2003-11-25 | 半導体装置及びその製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7417311B2 (ja) |
| JP (1) | JP3929966B2 (ja) |
| KR (1) | KR101043313B1 (ja) |
| CN (1) | CN100375232C (ja) |
| TW (1) | TWI371061B (ja) |
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| JP2001053041A (ja) * | 1999-08-11 | 2001-02-23 | Nippon Sheet Glass Co Ltd | 半導体ウェハ裏面加工時の表面保護方法および半導体ウェハの保持方法 |
| JP3770007B2 (ja) | 1999-11-01 | 2006-04-26 | 凸版印刷株式会社 | 半導体装置の製造方法 |
| JP4376388B2 (ja) | 1999-12-13 | 2009-12-02 | パナソニック株式会社 | 半導体装置 |
| JP2001210761A (ja) * | 2000-01-24 | 2001-08-03 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US6392290B1 (en) * | 2000-04-07 | 2002-05-21 | Siliconix Incorporated | Vertical structure for semiconductor wafer-level chip scale packages |
| JP3459234B2 (ja) | 2001-02-01 | 2003-10-20 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
| JP2002270720A (ja) | 2001-03-09 | 2002-09-20 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| TWI249828B (en) * | 2001-08-07 | 2006-02-21 | Advanced Semiconductor Eng | Packaging structure for semiconductor chip and the manufacturing method thereof |
| US6794273B2 (en) * | 2002-05-24 | 2004-09-21 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
| US7358618B2 (en) * | 2002-07-15 | 2008-04-15 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20070032066A1 (en) | 2007-02-08 |
| CN1630029A (zh) | 2005-06-22 |
| JP2005158929A (ja) | 2005-06-16 |
| US7417311B2 (en) | 2008-08-26 |
| US20050112800A1 (en) | 2005-05-26 |
| TWI371061B (en) | 2012-08-21 |
| CN100375232C (zh) | 2008-03-12 |
| KR101043313B1 (ko) | 2011-06-22 |
| TW200524025A (en) | 2005-07-16 |
| US7468292B2 (en) | 2008-12-23 |
| KR20050050570A (ko) | 2005-05-31 |
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