JP3931805B2 - Silicon carbide semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device.
[0002]
[Prior art]
Silicon carbide (SiC) is a semiconductor material having a wide band gap and a maximum dielectric breakdown electric field that is an order of magnitude greater than that of silicon. The natural oxide of silicon carbide is SiO ₂ , and a thermal oxide film can be easily formed on the surface of silicon carbide using a method similar to the method of forming a thermal oxide film on the silicon surface. From this point of view, silicon carbide is expected to be a very excellent material when used as a high-speed / high-voltage switching element of an electric vehicle, particularly as a high-power uni / bipolar element. As a conventional silicon carbide planar MOSFET, one shown in the schematic cross-sectional view of FIG. 4 is known (for example, see Patent Document 1).
[0003]
As shown in FIG. 4, in silicon carbide planar MOSFET 100, n ⁻ type silicon carbide epitaxial layer 102 is formed on high concentration n ⁺ type silicon carbide substrate 101. Then, p-type base regions 103 a and 103 b and n ⁺ -type source regions 104 a and 104 b are formed in predetermined regions in the surface layer portion of the epitaxial layer 102. Note that the surface layer portions of the p-type base regions 103a and 103b function as channel regions 105a and 105b during device operation. A polysilicon gate 107 is arranged on n ⁻ type silicon carbide epitaxial layer 102 with a gate insulating film 106 interposed therebetween. The polysilicon gate 107 is covered with an insulating film 109. The source electrodes 110a and 110b are formed in contact with the n ⁺ type source regions 104a and 104b. In addition, the gate electrode 108 is formed in contact with the polysilicon gate 107. Further, a drain electrode 111 is formed on the back surface of the n ⁺ -type silicon carbide substrate 101. Note that the p-type base regions 103a and 103b are connected so as to have the same potential as the source electrodes 110a and 110b, not shown.
[0004]
Next, the operation of the planar MOSFET 100 having such a configuration will be described. First, when a positive voltage is applied to the gate electrode 108 with the source electrodes 110 a and 110 b grounded and a positive voltage applied to the drain electrode 111, a p-type base region facing the polysilicon gate 107. Inverted channels are formed in the channel regions 105 a and 105 b in the surface layer portions 103 a and 103 b, and electrons can flow from the source electrodes 110 a and 110 b to the drain electrode 111. In this state, when the voltage applied to the gate electrode 108 is set to zero, the source electrodes 110a and 110b and the drain electrode 111 are electrically insulated and are cut off. As described above, the source electrodes 110a and 110b and the drain electrode 111 are electrically switched between a conductive state and a cut-off state depending on whether or not a positive voltage is applied to the gate electrode 108.
[0005]
[Patent Document 1]
JP-A-10-233503 (first page, FIG. 1)
[0006]
[Problems to be solved by the invention]
However, silicon carbide planar MOSFET 100 as shown in FIG. 4 has a structure having a conductivity type different from that of silicon carbide epitaxial layer 102 or a region having a different impurity concentration at a predetermined position of silicon carbide epitaxial layer 102. Local impurity doping into silicon carbide epitaxial layer 102 is required during manufacturing. For such local impurity doping, an ion implantation method is mainly used. When impurity doping is performed by the ion implantation method, the crystal in the silicon carbide epitaxial layer 102 is damaged. In particular, silicon carbide, whose crystal structure is difficult to recover, requires high-temperature ion implantation in which implantation is performed while heating the silicon carbide substrate to a high temperature. In addition, activation of the doped impurities requires heat treatment (activation annealing) at a high temperature around 1500 ° C. This high-temperature heat treatment has a problem that the surface of the silicon carbide epitaxial layer 102 is deteriorated, which adversely affects device characteristics. Specifically, channel mobility and reliability of the gate insulating film 106 are decreased. Such a high-temperature heat process is unique to silicon carbide, and has a problem that the process becomes complicated in addition to the above-described adverse effects. Here, a MOSFET is used as a conventional example, but an element such as a junction FET or a bipolar transistor is also locally different in conductivity type from silicon carbide epitaxial layer 102 at a predetermined position of silicon carbide epitaxial layer 102. Alternatively, since the structure has regions with different impurity concentrations, the above problem is unavoidable.
[0007]
Further, although the gate insulating film 106 is mainly formed of SiO ₂ by thermal oxidation, when a high voltage is applied to the drain electrode 111 and a high electric field spreads in the silicon carbide epitaxial layer 102, the gate insulating film 106 is carbonized. Since it is in contact with silicon epitaxial layer 102, gate insulating film 106 may reach a breakdown electric field before silicon carbide epitaxial layer 102 reaches a critical electric field. Therefore, the breakdown voltage of the element is limited by the dielectric breakdown voltage of the gate insulating film 106, and there is a limit to improving the breakdown voltage of the element.
[0008]
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a silicon carbide semiconductor device having a high breakdown voltage and a structure that can be manufactured by a simple process.
[0009]
[Means for Solving the Problems]
The present invention is characterized in that a silicon carbide substrate in which a silicon carbide epitaxial layer of a first conductivity type is formed on the first main surface side of a silicon carbide substrate having a first conductivity type and a high impurity concentration, A source region made of a semiconductor having a band gap different from that of silicon carbide formed on the first main surface side, a gate region made of a second conductivity type semiconductor so as to be in contact with the source region, and in contact with the source region And a drain electrode formed on the second main surface side of the silicon carbide substrate. The source electrode is formed on the second main surface side of the silicon carbide substrate.
[0010]
【The invention's effect】
According to the present invention, since the silicon carbide epitaxial layer does not have a local doping region, a process specific to silicon carbide such as high-temperature ion implantation and high-temperature heat treatment associated therewith is unnecessary, and the silicon carbide epitaxial layer Therefore, a good switching element can be realized easily.
[0011]
Further, in the silicon carbide semiconductor device according to the present invention, when the source electrode is grounded, a high voltage is applied to the drain electrode, and the gate electrode is set to the same potential as the source electrode so as to be cut off, the source region and the silicon carbide Since electrons accumulated on the source region side of the interface with the epitaxial layer (hereinafter referred to as a heterojunction interface) shield the electric field, the electric field does not reach the source region. Therefore, according to the present invention, the breakdown voltage of the silicon carbide semiconductor device can be increased.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, details of a silicon carbide semiconductor device according to the present invention will be described based on embodiments shown in the drawings. However, it should be noted that the drawings are schematic, and the thicknesses and ratios of the layers are different from actual ones. Moreover, the part from which the relationship and ratio of a mutual dimension differ also in between drawings is contained.
[0013]
(First embodiment)
A silicon carbide semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment.
[0014]
In silicon carbide semiconductor device 10A of the present embodiment, n ⁻ type silicon carbide epitaxial layer 12 is formed on the first main surface side of n ⁺ type silicon carbide substrate 11 as the first conductivity type having a high impurity concentration. A silicon carbide substrate 13, a source region 14 made of n ⁻ -type polysilicon formed on the upper surface side (first main surface side) of the silicon carbide substrate 13, and a second region so as to be in contact with the source region 14. A gate region 15 made of p ⁺ type polysilicon as a conductivity type, a source electrode 16 formed in contact with the source region 14, a gate electrode 17 formed in contact with the gate region 15, and a silicon carbide substrate 13 and the drain electrode 18 formed on the lower surface side (second main surface side).
[0015]
Gate region 15 and silicon carbide epitaxial layer 12 are electrically insulated by n ⁻ -type source region 14 and interlayer insulating film 19A. The source region 14 in contact with the source electrode 16 is an n ⁺ type source contact region 14A so as to obtain ohmic contact. Source contact region 14A is formed on interlayer insulating film 19B so as not to be in direct contact with silicon carbide epitaxial layer 12. Further, the source electrode 16 and the gate electrode 17 are connected to the source contact region 14 </ b> A and the gate region 15 through contact holes 20 </ b> A and 20 </ b> B formed in the insulating film 20.
[0016]
In the present embodiment, gate region 15 and silicon carbide epitaxial layer 12 are electrically insulated from each other. However, gate region 15 and silicon carbide epitaxial layer 12 may be in contact with each other. .
[0017]
Next, a specific operation of silicon carbide semiconductor device 10A according to the present embodiment will be described.
[0018]
First, the band structure at the heterojunction interface (junction interface between the silicon carbide epitaxial layer and polysilicon) in a state where no voltage is applied to any of the source electrode 16, the drain electrode 18 and the gate electrode 17, that is, in a thermal equilibrium state is shown in FIG. It is as shown in (a).
[0019]
Next, when the source electrode 16 is grounded, a high voltage is applied to the drain electrode 18, and the gate electrode 17 is set to the same potential as the source potential, that is, grounded, the band structure at the heterojunction interface is as shown in FIG. To change. In this case, the electrons 50 are blocked by the barrier 51 generated at the heterojunction interface, and the blocked state is maintained. In addition, since the electric field is shielded by electrons 50 accumulated on the source region 14 side of the heterojunction interface, the electric field does not reach the source region 14 side, and a high voltage is applied only to the silicon carbide epitaxial layer 12. Therefore, even when the thickness of the source region 14 is as thin as several tens of nm, the source region 4 can maintain a high breakdown voltage without causing dielectric breakdown in the cutoff state. The breakdown voltage can be obtained by controlling the silicon carbide epitaxial layer 12 and the source region 14, that is, the impurity concentration of polysilicon.
[0020]
Next, when a voltage higher than the source potential is applied to the gate electrode 17 in order to shift from the cutoff state to the conductive state, an appropriate constant current flows from the gate electrode 17 to the source region 14, as shown in FIG. Thus, the holes 52 injected from the gate region 15 recombine with the electrons 50 accumulated on the source region 14 side of the heterojunction interface and disappear. For this reason, the electric field shielded by the electrons 50 accumulated on the source region 14 side of the heterojunction interface reaches the source region 14, and the electrons 50 flow from the source region 14 to the drain electrode 18 side and become conductive. Become.
[0021]
Thereafter, when the gate electrode 17 is set to the same potential as the source potential and the constant current flowing from the gate region 15 to the source region 14 is zero, the injection of the holes 52 from the gate region 15 to the source region 14 is eliminated. The electrons 50 are accumulated again on the source region 14 side of the heterojunction interface. Since the accumulated electrons 50 shield the electric field applied to the source region 14, the electric field does not reach the source region 14, and a cut-off state is established.
[0022]
As described above, in the switching operation of silicon carbide semiconductor device 10A according to the present embodiment, hole 52 injection from gate region 15 is caused by electrons 50 accumulated on the source region 14 side of the heterojunction interface. The purpose is to reduce the electric field shielding effect. Therefore, the exchange of electric charges at the heterojunction interface in the on state is only electrons, and silicon carbide semiconductor device 10A according to the present embodiment can be handled as a majority carrier device.
[0023]
In silicon carbide semiconductor device 10A according to the present embodiment, as shown in FIG. 1, the conductivity type of source contact region 14A in contact with source electrode 16 is an n ⁺ type, and source electrode 16 and source contact region The contact with 14A is an ohmic contact, and the contact resistance is low. For this reason, in silicon carbide semiconductor device 10A of the present embodiment, the on-resistance can be further reduced.
[0024]
Furthermore, in silicon carbide semiconductor device 10A of the present embodiment, as shown in FIG. 1, since the conductivity type of gate region 15 is p ⁺ type, the injection efficiency of holes 52 from gate region 15 is high. As a result, the electrons 50 accumulated on the source region 14 side of the heterojunction interface are efficiently recombined and become more conductive. That is, the conductive state can be achieved with a lower gate driving power.
[0025]
Further, as shown in FIG. 1, silicon carbide semiconductor device 10A in the present embodiment has a structure that does not have a local doping region in silicon carbide epitaxial layer 12, and therefore, high-temperature ion implantation and the accompanying steps. A process peculiar to silicon carbide such as high-temperature heat treatment is not required, and a high breakdown voltage switching element can be realized by a simple process without deteriorating the surface of the silicon carbide epitaxial layer 12.
[0026]
Furthermore, in silicon carbide semiconductor device 10A of the present embodiment, since polysilicon is used as a semiconductor having a band gap different from that of silicon carbide, the conductivity control and etching of the semiconductor layer can be easily performed, and the process is further improved. It can be simplified.
[0027]
(Second Embodiment)
Next, a second embodiment of the silicon carbide semiconductor device according to the present invention will be described with reference to FIG. FIG. 3 shows a cross-sectional view of silicon carbide semiconductor device 10B according to the second embodiment. In silicon carbide semiconductor device 10B of the present embodiment, the same parts as those of silicon carbide semiconductor device 10A according to the first embodiment described above are denoted by the same reference numerals, and description thereof is omitted.
[0028]
In silicon carbide semiconductor device 10B according to the present embodiment, electric field relaxation layer 21 having a predetermined depth is formed from the first main surface side of silicon carbide epitaxial layer 12. Electric field relaxation layer 21 is formed below gate region 15 and interlayer insulating film 19A and below source contact region 14A and interlayer insulating film 19B on the first main surface side of silicon carbide epitaxial layer 12. Electric field relaxation layer 21 is formed by locally doping impurities on the main surface side of silicon carbide epitaxial layer 12 so that the conductivity type is p-type. Other configurations in the present embodiment are the same as those of silicon carbide semiconductor device 10A according to the first embodiment described above.
[0029]
In addition to the operation of silicon carbide semiconductor device 10A according to the first embodiment described above, silicon carbide semiconductor device 10B according to the second embodiment grounds source electrode 16 and applies high voltage to drain electrode 18. When the gate electrode 17 is set to the same potential as the source potential, a reverse bias is also applied between the electric field relaxation layer 21 fixed to the same potential as the source electrode 16 and the silicon carbide epitaxial layer 12, and the junction Since the depletion layer extends from the interface and the electric field applied to the heterojunction interface is relaxed, it is easy to realize the cutoff state. That is, the off characteristics can be improved in silicon carbide semiconductor device 10B. The electric field relaxation layer 21 may be either a dielectric buried layer or a p ⁻ type silicon carbide layer.
[0030]
Here, as shown in FIG. 3, when the electric field relaxation layer 21 is formed of a p ⁻ type silicon carbide layer, it is necessary to use local impurity doping (such as high-temperature ion implantation) as described above. Although there is concern about the accompanying deterioration of the surface of silicon carbide epitaxial layer 12, interlayer insulating films 19 a and 19 b are formed on electric field relaxation layer 21 and are not in contact with silicon carbide epitaxial layer 12. Therefore, in this embodiment, even when the source electrode 16 is grounded, a high voltage is applied to the drain electrode 18, and the gate electrode 17 is set to the same potential as the source potential, the interlayer insulating films 19A and 19B break down. There is nothing.
[0031]
In addition, silicon carbide semiconductor device 10B according to the second embodiment has a structure in which channel region is not provided in silicon carbide epitaxial layer 12 as in a conventional silicon carbide planar MOSFET, and therefore, in a high temperature thermal process, Even if the surface of silicon carbide epitaxial layer 12 is deteriorated, there is an advantage that the problem of lowering channel mobility does not occur.
[0032]
(Other embodiments)
Although the embodiment of the present invention has been described above, it should not be understood that the description and drawings constituting a part of the disclosure of the above-described embodiment limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
[0033]
For example, in the first and second embodiments described above, the semiconductor layer serving as the source region is formed of polysilicon. However, the semiconductor layer is not limited to this as long as the semiconductor material has a narrower band gap than silicon carbide. .
[0034]
In the first and second embodiments described above, the first conductivity type is n-type, but the same effect can be obtained even when the first conductivity type is p-type. Although the source region is described as n-type and the gate region as p-type, the source region may be n-type and the gate region may be n-type.
[0035]
Furthermore, it goes without saying that modifications are included within the scope not departing from the gist of the present invention.
[Brief description of the drawings]
FIG. 1 is a cross sectional view showing a first embodiment of a silicon carbide semiconductor device according to the invention.
FIGS. 2A to 2C are diagrams showing a band structure at a heterojunction interface between polysilicon and silicon carbide. FIGS.
FIG. 3 is a cross sectional view showing a second embodiment of the silicon carbide semiconductor device according to the present invention.
FIG. 4 is a cross-sectional view showing a conventional silicon carbide planar MOSFET.
[Explanation of symbols]
10A, 10B Silicon carbide semiconductor device 11 Silicon carbide substrate 12 Silicon carbide epitaxial layer 13 Silicon carbide substrate 14 Source region 14A Source contact region 15 Gate region 16 Source electrode 17 Gate electrode 18 Drain electrode

Claims (5)

A silicon carbide substrate in which a first conductivity type silicon carbide epitaxial layer is formed on the first main surface side of a silicon carbide substrate having a first conductivity type and a high impurity concentration;
A source region formed of a semiconductor having a different band gap from silicon carbide, formed on the first main surface side of the silicon carbide substrate;
A gate region made of a second conductivity type semiconductor so as to be in contact with the source region;
A source electrode formed in contact with the source region;
A gate electrode formed in contact with the gate region;
A drain electrode formed on the second main surface side of the silicon carbide substrate;
A silicon carbide semiconductor device comprising: An electric field relaxation region is provided at a predetermined position on the first main surface side of the silicon carbide epitaxial layer in the vicinity immediately below the source region, and the electric potential of the electric field relaxation region is set to the same potential as the source region. The silicon carbide semiconductor device according to claim 1. The impurity concentration of the source region in contact with the source electrode is set to be higher than the impurity concentration in the source region portion other than this portion, and the source electrode is in ohmic contact with the source region. Item 3. A silicon carbide semiconductor device according to item 1 or item 2. The impurity concentration in the gate region is set higher than the impurity concentration in the source region in contact with the silicon carbide epitaxial layer. Silicon carbide semiconductor device. 5. The silicon carbide semiconductor device according to claim 1, wherein the source region is made of at least one of single crystal silicon, amorphous silicon, and polycrystalline silicon.

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