JP3934527B2 - Method for processing butt-supported shape and method for manufacturing semiconductor device using the processing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for processing an object having a specific shape in a manufacturing process of a semiconductor device, and in particular, a cross-sectional shape having a flange extending in a horizontal direction, a horizontal diagonally upward direction or a horizontal diagonally downward direction at a tip extending in a columnar shape. The present invention relates to a method of processing a buttock-supported shape.
[0002]
[Prior art]
In a semiconductor manufacturing process, CVD or the like is performed from above a heel-supported shape having a cross-sectional shape having a heel extending in a lateral direction, a laterally obliquely upward direction or a laterally obliquely downward direction at a tip portion extending in a columnar shape. It is known that when an interlayer insulating film is formed by sputtering, a film is not formed in the lower part of the collar part and a defect that becomes a cavity occurs.
[0003]
Such a butt-supported shape has an edge when the step coverage is poor in the formation of an interlayer insulating film by CVD or sputtering on a substrate having a surface with an uneven surface formed with wiring or the like. It is formed by overhanging (see, for example, Non-Patent Document 1).
[0004]
[Non-Patent Document 1]
Takashi Ito, Hajime Ishikawa, Hiroaki Nakamura “VLSI Thin Film Technology” Maruzen, September 30, 1886, p. 233-234
[0005]
In addition, there is a case where the collar support mold is not formed due to a defect but is intentionally formed in order to form an element having an LDD structure (for example, see Non-Patent Document 2). In order to protect the region to be the LDD with a mask formed on the gate electrode and to add an impurity for forming a source (or drain), a bowl-like shape having a horizontal length longer than that of the gate electrode is formed on the gate electrode. When the mask is formed, the shape of the cross section combined with the gate electrode is a heel support type.
[0006]
[Non-Patent Document 2]
SEIKI OGURA et.al., “Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor”, IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE, August 1980, p. 1359-1367
[0007]
As one of the methods for removing the buttock of the buttock-supported shape as described above, there is a method such as an etch back method (see, for example, Non-Patent Document 3). In the etch-back method, when an insulating film is originally formed by CVD or sputtering on a substrate with the above-described wiring and the like having an uneven surface, the edge protrudes due to a defect related to step coverage. This method was developed as a method for flattening an insulating film in the case where the heel portion is removed. However, since the flattening is realized by removing the heel portion, the heel portion supporting shape is processed here to remove the heel portion. This is taken as one of the removal methods.
[0008]
[Non-Patent Document 3]
Takashi Ito, Hajime Ishikawa, Hiroaki Nakamura “VLSI Thin Film Technology” Maruzen, September 30, 1886, p. 238-239
[0009]
In the etch back method, a liquid material such as a resist is applied on a film having an uneven surface (for example, an inorganic insulating film) to obtain a flat surface, and then the surface is uneven. In this method, the unevenness on the surface is removed by dry etching of the resist film and the resist film under conditions having no selectivity. This method can also be applied to removal of a mask formed to form an element having an LDD structure as described above.
[0010]
[Problems to be solved by the invention]
However, when the etch-back method as described above is used, the film thickness ratio between the film with the uneven surface and the resist changes depending on the size of the pattern and the density, so that the etching rate ratio is adjusted. However, there are problems such as being difficult to be damaged and being susceptible to damage from plasma due to exposure to long-time dry etching.
[0011]
In the present invention, in order to avoid defects caused by the cross-sectional shape being the buttock-supporting type by processing the buttock-supporting shape in particular by a method that can selectively remove the buttock. It is an object of the present invention to provide a method for processing a buttock-supported shape. It is another object of the present invention to provide a processing method for a buttock-supported shape that can avoid a process using plasma such as dry etching.
[0012]
[Means for Solving the Problems]
The processing method of the buttock-supporting shaped object of the present invention is a buttock-supporting shape having a cross-sectional shape having a heel portion extending in the lateral direction, horizontally obliquely upward direction, or horizontally obliquely downward direction at the tip portion extending in a columnar shape. A step of embedding an object in the first photosensitive resin film, and processing the first photosensitive resin film by exposure and development to form a second photosensitive resin film, and the second photosensitive resin film A step of exposing the buttock portion of the buttock-supporting shaped object from the surface, and a step of etching the buttock-supporting shape object using the second photosensitive resin film as a mask.
[0013]
FIG. 1 is a cross-sectional view showing a processing method for a buttock-supporting shaped object of the present invention.
[0014]
On the substrate (or film) 101, there is a heel-supporting shaped object 102 having a cross-sectional shape having a heel extending in a lateral direction, a laterally obliquely upward direction or a laterally obliquely downward direction at a tip portion extending in a columnar shape. A photosensitive resin is applied on the flange-supporting shaped article 102, and a first photosensitive resin film 103a is formed. At this time, a part or the whole of the buttocks support-type shaped object 102 is embedded in the first photosensitive resin film 103a. Since the photosensitive resin is a fluid liquid material, the photosensitive resin can be diffused also in the lower part of the buttock of the buttock-supporting shaped object 102 to cover the entire buttock-supporting shaped object 102. It becomes.
[0015]
Next, the first photosensitive resin film 103a is processed by exposure and development to form a second photosensitive resin film 103b. At this time, the collar part of the collar part supporting mold 102 is exposed from the surface of the second photosensitive resin film 103b. In other words, the constricted portion of the collar-supporting shape is protected by the second photosensitive resin film. Note that as the photosensitive resin, a resist, photosensitive acrylic, or the like can be used.
[0016]
Next, using the second photosensitive resin film 103b as a mask, the buttock support type shaped article 102 is etched to be processed into a shaped article 104 from which the ridge has been removed. While the collar portion is being etched, the other portions are protected by the second photosensitive resin film 103b and thus are not etched. In addition, after all of the heel portion has been etched, the etching also proceeds to the constricted portion, so that the etching is immediately stopped. For the etching, either a wet method or a dry method can be used, but by using the wet method, the effect of avoiding plasma damage can be obtained.
[0017]
As described above, the buttocks support shape is processed. Thereby, a collar part can be selectively removed. Therefore, even in the control of the etching rate, it is possible to select the optimum conditions for the etching of the ridges, and it is necessary to always etch the resist film and the ridges at the same etching rate as in the etch back method. The difficulty related to the control of the etching rate can be reduced as much as possible. After removing the buttock, the photosensitive resin film is removed using a stripping solution or acetone.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
In this embodiment, an LDD including a step of forming a bowl-shaped hard mask over a gate electrode, adding a high concentration impurity for forming a source (or drain) using the hard mask as a mask, and then removing the hard mask. A method for removing a hard mask in a method for manufacturing a semiconductor device using a method for forming an element having a structure is described. Here, the hard mask refers to a mask manufactured using a material other than a resist.
[0019]
Here, the hard mask must be removed in order to form an LDD by adding a low concentration impurity to a region masked by the hard mask when a high concentration impurity is added. In addition, the hard mask and the gate insulating film are formed using the same material, and when removing the hard mask, only the hard mask must be selectively removed so that the gate insulating film is not etched. To do. This is to prevent the gate insulating film below the gate electrode from being etched and a cavity from being formed under the gate electrode.
[0020]
An embodiment of the present invention will be described with reference to FIG. In FIG. 2, a gate insulating film 202 is formed on a semiconductor film 201, a gate electrode 203 is formed on the gate insulating film 202, and an insulating film mask (hereinafter referred to as a hard mask) is formed on the gate electrode 203. ) 204 is formed. A source (or drain) 207 is formed in the semiconductor film 201 by addition of a high concentration impurity. The horizontal length of the hard mask 204 is longer than the horizontal length of the gate electrode 203, and the cross-sectional shape when the hard mask 204 and the gate electrode 203 are combined is a heel support shape. Therefore, here, a combination of the hard mask 204 and the gate electrode 203 is used as the heel support shape object 205.
[0021]
The semiconductor film 201 is a crystalline silicon film, the gate insulating film 202 is a silicon oxide film, the gate electrode 203 is tungsten, and the hard mask 204 is a silicon oxide film. However, the present invention is not limited to the materials described above, and other materials may be used.
[0022]
First, a positive resist is applied to embed the entire collar support shape 205 in the resist film 206a. Since the resist is a liquid material having fluidity, the resist also flows under the hard mask 204, and the entire heel support shape object 205 can be embedded in the resist film 206a. Therefore, it is preferable to use a resist having a viscosity as low as possible.
[0023]
Next, the resist film 206a is exposed and developed, and the resist film 206a is processed to form a resist film 206b. At this time, the surface of the hard mask 204 and a part of the ridge are exposed from the resist film 206b. In addition, what is necessary is just to perform the exposure amount according to the following exposure method.
[0024]
Here, an exposure method of the resist film 206a will be described. FIG. 5 is a cross-sectional view of the buttock-supporting shaped object in the present embodiment. In FIG. 5, a region where the resist film is formed on the gate insulating film is a region A, and a region where the resist film is formed on the hard mask is a region B. The distance from the gate insulating film surface to the resist film surface (that is, the resist film thickness in the region A) is a, the gate electrode thickness is b, the hard mask thickness is c, and the hard mask surface to the resist film surface Let d be the distance to the surface (that is, the resist film thickness in region B).
[0025]
In the present embodiment, a part of the resist film in the region A is left, and the resist film in the region B is entirely removed. Therefore, the exposure conditions are such that the remaining film rate in the region A is y1 (= b / a × 100) to y2 (= (b + c) / a × 100)% and the remaining film rate in the region B is 0%. Expose the entire surface. The exposure does not require a mask for forming an optical pattern such as a reticle, and is performed by irradiating the entire surface with light. Therefore, alignment is not necessary.
[0026]
Here, the residual film ratio is expressed by the residual film ratio (%) = resist film thickness after development / resist film thickness after coating × 100. In addition, exposure (mJ / cm ² ) = Irradiation light intensity (mW / cm ² ) × exposure time (msec), and it is noted that the lower limit of the exposure amount when the remaining film rate is 0% is expressed as Eth. The remaining film ratio changes depending strongly on the film thickness of the resist film, the film quality of the film below the resist film, the coating conditions of the resist film, and the development conditions. Therefore, Eth also changes for each of these conditions.
[0027]
In general, Eth tends to increase as the resist film thickness increases (also referred to as a bulk effect). Eth also varies depending on the reflectance of the film below the resist film, and tends to decrease as the reflectance increases. The residual film ratio of the resist film tends to decrease as the amount of energy of light received by the resist increases, that is, as the amount of light increases. At the time of exposure, the resist film receives both the light irradiated from the exposure apparatus and the reflected light reflected by the film below the resist film. Therefore, the higher the reflectivity, the more the light received by the resist film. The amount of light increases and Eth tends to decrease. In the present invention, the dependence of Eth on the resist film thickness and the reflectance dependence on the film below the resist film are positively utilized.
[0028]
FIG. 6 schematically shows the relationship between the exposure amount and the remaining film ratio in the regions A and B. Since region A has a thicker resist film than region B, Eth in region A (hereinafter referred to as Eth) _(A) Is the Eth in the region B (hereinafter referred to as Eth) _(B) Than). In the region A, since it is desired to set the remaining film rate to y1 to y2%, x1 to x2 mJ / cm ² It is sufficient to irradiate light with the exposure amount. In the region B, since the remaining film ratio is desired to be 0%, Eth _(B) What is necessary is just to irradiate light with the above exposure amount. Therefore, Eth _(B) mJ / cm ² And x1 to x2 mJ / cm ² It can be seen that light may be irradiated with an exposure amount of.
[0029]
Therefore, Eth _(A) And Eth _(B) The larger the difference is, and the larger the difference between x1 and x2, the wider the margin of exposure conditions. Eth _(A) And Eth _(B) In order to increase the difference, the difference between the resist film thickness a in the region A and the resist film thickness d in the region B may be increased. If the film thickness c of the hard mask is large, the difference between the film thickness a and the film thickness d increases, and as a result, the difference between x1 and x2 also increases. In addition, the greater the light reflectance at the hard mask 204 or the gate electrode 203, the greater the Eth. _(B) Becomes smaller and the margin of the exposure condition widens. Further, by adjusting the resist film thickness at the time of application so that the resist film thickness d in the region B becomes as small as possible, Eth _(B) Becomes smaller and the resist film in the region B can be easily removed. As described above, a sufficient margin for exposure conditions can be secured by adjusting the resist film thickness and the hard mask film thickness.
[0030]
Thus, the residual film ratio can be controlled by the exposure amount, and the residual film amount of the resist can be adjusted according to the shape of the object to be exposed even when the entire surface is irradiated. The relationship between the amount of exposure and the remaining film ratio depends on the properties of the resist (such as viscosity and the type of solvent and light absorber), the shape and material of the object to which the resist is applied, and the baking conditions during application and development. Therefore, it is necessary to examine the relationship between the exposure amount and the remaining film ratio in advance for each object to be processed. These operations may be performed in the same manner as the normal patterning conditions.
[0031]
The resist film 206b is processed into a desired shape by exposure and development by the method described above.
[0032]
Next, using the resist film 206b as a mask, the hard mask 204 is etched using a hydrofluoric acid-containing solution. Since the gate electrode 203 is formed of tungsten, it remains without being etched with a hydrofluoric acid-containing solution.
[0033]
The hard mask 204 can be etched by a dry method such as dry etching in addition to the wet method as described above. However, the wet method is effective in avoiding plasma damage. Etching by a wet method cannot be done by an etch-back method, and is a means made possible by applying the present invention.
[0034]
Next, the resist film 206b is peeled off.
[0035]
As described above, the hard mask 204 serving as the buttock of the buttock supporting shape 205 can be removed. By using such a method, the hard mask 204 can be selectively removed without etching the gate insulating film 202 formed using the same material as the hard mask 204. That is, the gate insulating film 202 is etched simultaneously with the etching of the hard mask 204, and an etchant such as a hydrofluoric acid-containing solution is introduced below the gate electrode 203 to form an interlayer insulating film on the gate electrode 203. It is possible to avoid such a defect that a cavity is formed in the lower part of the substrate. In addition, a semiconductor device can be manufactured that avoids defects such as the formation of cavities caused by the buttocks supported shape.
[0036]
[Embodiment 2]
In this embodiment, when the interlayer insulating film is formed on the wiring in the manufacturing process of the semiconductor device, the step coverage of the interlayer insulating film is poor, the edge protrudes, and the collar portion is formed. A method for removing the buttocks will be described.
[0037]
In such a case, when a conductive film or an interlayer insulating film is formed on the interlayer insulating film by CVD or etching, a film is not formed in the lower part of the collar part and the cavity is not formed. There is a possibility that a failure will occur. In order to avoid such a defect, the buttocks are removed.
[0038]
An embodiment of the present invention will be described with reference to FIG. A wiring 302 is formed on the substrate (or film) 301, and an interlayer insulating film 303 a is formed on the wiring 302. The interlayer insulating film 303a has a step support type shape in which the step coverage is poor, the edges protrude, and wrinkles are formed. In the portion where the plurality of wirings 302 are adjacent, the flanges formed by the interlayer insulating film 303a formed on each wiring are adjacent, and the distance between the adjacent flanges is very narrow. It has become.
[0039]
The wiring 302 is formed of aluminum (Al), and the interlayer insulating film 303a is formed of a silicon oxide film. However, the present invention is not limited to the materials described here, and other materials may be used.
[0040]
A positive resist is applied on the interlayer insulating film 303a to form a resist film 304a. Thereby, the entire interlayer insulating film 303a is embedded in the resist film 304a. At this time, it is preferable to use a resist having a low viscosity so that the resist is easily diffused to the lower side of the adjacent ridges because the distance is narrowed.
[0041]
Next, the resist film 304a is processed by exposure and development to form a resist film 304b. At this time, the surface of the interlayer insulating film 303a and a part of the ridge are exposed from the resist film 304b. For the exposure, the exposure method described in Embodiment Mode 1 may be used.
[0042]
Next, using the resist film 304b as a mask, the interlayer insulating film 303a is etched using a hydrofluoric acid-containing solution to form an interlayer insulating film 303b from which the collar portion is removed. At this time, in the case where the wiring 304 (not illustrated) is formed over the interlayer insulating film 303b, it is necessary to control the thickness of the interlayer insulating film 303b so that the wiring 302 and the wiring 304 are not short-circuited. When an interlayer insulating film is further formed over the interlayer insulating film 303b, the wiring 302 may be exposed after etching, but aluminum or the like is used as the material of the wiring 302 as in this embodiment mode. When used, the wiring 302 is corroded by the hydrofluoric acid-containing solution, and therefore it is preferable that the wiring 302 is not exposed as much as possible. Alternatively, it is desirable to form a thin film (for example, a silicon nitride film) between the wiring 302 and the interlayer insulating film 303a so as to prevent the progress of etching into the wiring 302.
[0043]
For the etching of the interlayer insulating film 303a, a dry method such as dry etching can be used in addition to the wet method as described above. However, the wet method is preferable because damage due to plasma can be avoided. Etching by a wet method cannot be done by an etch-back method, and is a means made possible by applying the present invention.
[0044]
Next, the resist film 304b is peeled off.
[0045]
As described above, when the interlayer insulating film 303a is formed, the ridges that have been formed at the same time can be removed. Accordingly, when forming a conductive film for further forming the wiring 304 on the interlayer insulating film 303a or further when forming an interlayer insulating film 305 (not shown), it is under the collar. It is possible to avoid defects such as cavities. In addition, a semiconductor device can be manufactured that avoids defects such as the formation of cavities caused by the buttocks supported shape. Note that in this embodiment mode, a single drain structure, an LDD structure, or the like may be used as an element structure until the wiring 302 is formed, and a manufacturing method thereof is not limited.
[0046]
[Embodiment 3]
In the present embodiment, in the active region surrounded by the field oxide film, the antireflection for preventing the reflected light from the conductive film formed on the field oxide film during the exposure for forming the gate electrode. A method of removing the film (ARC: Anti-Reflection Cell) will be described.
[0047]
In a semiconductor device manufacturing process, in particular in an LSI manufacturing process, after patterning for forming a gate electrode after forming a conductive film on a field oxide film, the exposed light is exposed to the side surface of the field oxide film. Patterning may not be successful due to the influence of the reflected light reflected by the conductive film formed on the substrate. In order to prevent this, an ARC having a low reflectance is formed on the conductive film to be the gate electrode, and patterning is performed. ARC remains on the gate electrode formed by patterning and etching, and ARC is also used as part of the gate electrode. For example, when molybdenum (Mo) is used as a gate electrode material and titanium nitride (TiN) is used as ARC Depending on the etching rate difference between Mo and TiN, Mo may recede rather than TiN, resulting in a ridge of TiN. In such a case, there is a possibility of causing a defect that the interlayer insulating film is not well formed in the lower portion of the flange portion of TiN and becomes a cavity. For this reason, it is necessary to selectively remove only TiN by a method in which the dimension of the gate electrode (other than the film thickness direction) that affects the channel length (or channel width) of the element does not change.
[0048]
An embodiment of the present invention will be described with reference to FIG. An active region 401 is formed so as to be surrounded by the field oxide film 402, and is formed on the active region 401 with a gate insulating film 403 (however, since it is formed of the same material as the field oxide film 402, it is connected to the field oxide film). The gate electrode 404 is formed on the gate insulating film 403, and the ARC 405 is formed on the gate electrode 404. The ARC 405 has a cross-sectional shape that is a ridge with respect to the gate electrode 404, and the cross-sectional shape in which the gate electrode 404 and the ARC 405 are combined forms a heel support-type shape 406.
[0049]
The active region 401 is formed of single crystal silicon, the field oxide film 402 and the gate insulating film 403 (is a silicon oxide film, the gate electrode 404 is molybdenum, and the ARC 405 is titanium nitride. However, the material is not limited to the materials described here. Other materials may be used.
[0050]
A positive resist is applied on the heel support shape 406 to form a resist film 407a. As a result, the entire buttock supporting shape 406 is embedded in the resist film 407a. At this time, it is preferable to use a resist having a low viscosity so that the resist diffuses also below the buttock of the buttock supporting shape.
[0051]
Next, the resist film 407a is processed by exposure and development to form a resist film 407b. At this time, the surface of the ARC 405 and a part of the ridge are exposed from the resist film 304b. For the exposure, the exposure method described in Embodiment Mode 1 may be used.
[0052]
Next, the ARC 405 is etched using the resist film 407b as a mask. A wet method is preferably used for etching, but a dry method using a chlorine-based or fluorine-based gas or a mixed gas thereof may be used.
[0053]
Next, the resist film 407b is peeled off.
[0054]
As described above, the ARC 405 can be selectively removed. As a result, it is possible to avoid the defect that the interlayer insulating film is not well formed in the lower part of the ARC 405 and becomes a cavity. In addition, a semiconductor device can be manufactured that avoids defects such as the formation of cavities caused by the buttocks supported shape. Note that after removing the ARC, a high-concentration impurity is added using the gate electrode 404 as a mask to form a source (or a drain), whereby a single drain structure element can be formed. Not only a single drain structure element but also an LDD structure element may be formed, and the manufacturing method thereof is not limited.
[0055]
As described above, the ARC forms a wiring between the convex portions on the surface having irregularities, for example, in addition to preventing reflection from the conductive film formed on the surface of the field oxide film. In the case where the patterning is not successful due to the reflected light from the side wall of the convex portion. Even in such a case, it is effective to selectively remove ARC by the method described above.
[0056]
[Embodiment 4]
In this embodiment mode, a method for manufacturing a semiconductor device using the processing method for a hook-holding shaped object of the present invention will be described with reference to FIGS. In this embodiment mode, a method for manufacturing a TFT array substrate for driving a liquid crystal display device as a semiconductor device will be described. As a result, when the hard mask used to form the gate overlapped LDD portion and the LDD portion is removed, the gate insulating film below the gate electrode is etched, and a cavity is formed below the gate electrode. A TFT in which no defect occurs can be manufactured.
[0057]
The TFT array substrate includes an LDD (Light Doped Drain) structure TFT (hereinafter referred to as a pixel TFT) for driving a pixel electrode, and a GOLD structure TFT for a drive circuit (hereinafter referred to as a drive circuit TFT). An explanation will be given of a method of forming an LDD structure TFT for a logic operation circuit (hereinafter referred to as a logic operation circuit TFT) on the same substrate. As a result, a system-on-panel or the like in which a peripheral circuit in which a CPU (Central Processing Unit) is incorporated on the same substrate and a display can be manufactured.
[0058]
7 to 12 are sectional views showing a manufacturing process of a TFT array substrate to which the present invention is applied.
[0059]
An island-shaped semiconductor film 602 is formed over the glass substrate 601. Next, an insulating film is formed over the semiconductor film 602 to form a gate insulating film 603. Further, a conductive film 604a and a conductive film 604b are stacked over the gate insulating film 603, and a hard mask film 606 for forming a hard mask is formed over the conductive film 604b.
[0060]
The semiconductor film 602 is a crystalline silicon film, the gate insulating film 603 is a silicon oxide film, the conductive film 604a is titanium nitride (TiN), the conductive film 604b is tungsten (W), and the hard mask film 606 is oxidized. A silicon film is used. Moreover, you may use not only these materials but another material. The hard mask film 606 is not limited to an insulating film such as a silicon oxide film, and a conductive film may be used.
[0061]
Patterning is performed on the hard mask film 606 by patterning, the hard mask film 606 and the conductive film 604b are etched using the resist mask as a mask, and the hard mask 607a and the gate electrode 608a are formed in the portions to be the driver circuit TFT and the pixel TFT. Form. A portion to be a logical operation circuit TFT is masked with a resist, and the hard mask 607a and the gate electrode 608a are not formed.
[0062]
Next, the gate electrode 608a is selectively etched to form the gate electrode 608b. As a result, only the side wall not covered with the hard mask 607a is retracted by etching, and the hard mask 607a is formed as a collar on the gate electrode 608a (this process is referred to as first side etching). ). Etching of the gate electrode 608a may be performed by wet or dry isotropic etching, but in this embodiment, a mixed solution of an ammonia solution and a hydrogen peroxide solution (hereinafter referred to as an ammonia aqueous solution) is used. And etch.
[0063]
Next, by patterning and etching, the hard mask film 606 and the conductive film 604b on the gate electrode 608b to be the gate electrode of the logical operation circuit TFT are etched to form the hard mask 607b and the gate electrode 608c.
[0064]
Next, the gate electrodes 608b and 608c are selectively etched using the hard masks 607a and 607b as masks to form gate electrodes 608d and 608e, respectively. As a result, the hard mask 607b is formed as a collar on the gate electrode 608e. A gate electrode 608d is formed using the hard mask 607a as a mask, and a gate electrode 608e is formed using the hard mask 607b as a mask (this process is referred to as second side etching). Etching of the gate electrodes 608b and 608c may be performed by wet or dry isotropic etching in the same manner as the first side etching, but in this embodiment, etching is performed using an ammonia aqueous solution.
[0065]
Using the hard mask 607a as a mask, the gate electrode 608a is etched twice, and the sum of the amount of retraction of the gate electrode 608a by the first side etching and the amount of retraction of the gate electrode 608b by the second side etching is hard to the gate electrode 608d. This is the size of the ridge portion of the mask 607a. In other words, the size is the size of the Gate Overlapped LDD portion of the driving electrode TFT and the size of the LDD portion of the pixel TFT. Further, the retraction amount of the gate electrode 608c by the second side etching using the hard mask 607b as a mask is the size of the ridge portion of the hard mask 607b with respect to the gate electrode 608e. Become. As described above, in this embodiment, the size of the LDD portion or the gate overlapped LDD portion is controlled by performing the side etching once or a plurality of times.
[0066]
Further, in this embodiment, the size of the buttock is separately formed by making the hard mask into the hard mask 607a and the hard mask 607b. However, this dissolves the resist as an etching solution for the gate electrode 608b. This is because an ammonia aqueous solution having the function of If a solution that does not dissolve the resist is used as the etching solution for the gate electrode 608b, the presence or absence of side etching is controlled for each TFT using a resist mask, the number of side etchings, and the gate electrode by side etching. The amount of retraction may be controlled and the size of the buttocks may be created separately.
[0067]
Next, a portion to become a p-channel TFT is masked with a resist, and a high-concentration n-type impurity is added using the hard masks 607a and 607b as a mask to form a source (or drain) of the n-channel TFT. As the n-type impurity, phosphorus, arsenic, or the like may be used.
[0068]
Next, a portion to become an n-channel TFT is masked with a resist, and a high-concentration p-type impurity is added using the hard masks 607a and 607b as a mask to form a source (or drain) of the p-channel TFT. As the p-type impurity, boron or the like may be used.
[0069]
Next, the conductive film 604a is processed using the hard masks 607a and 607b as masks to form gate electrodes 611a.
[0070]
Next, a resist is applied so that the entire hard masks 607a and 607b are embedded in the resist film 612a, and the resist film 612a is further processed using the exposure method described in Embodiment 1, so that the hard mask 607a is processed. , 607b is formed so that a part of the resist film 612b is exposed from the resist film 612b.
[0071]
Next, the hard masks 607a and 607b are selectively etched and removed using the resist film 612b as a mask. In this embodiment mode, since the hard masks 607a and 607b are formed using a silicon oxide film, the hard masks 607a and 607b may be removed using a hydrofluoric acid-containing solution. At this time, since the gate insulating film 603 is protected by the resist film 612b, it is not etched by the hydrofluoric acid-containing solution. Therefore, it can be avoided that the lower portion of the gate electrode 611a becomes hollow.
[0072]
Next, the p-channel TFT, the pixel TFT, and the logical operation circuit TFT of the driving circuit TFT are masked with a resist, and further, the gate electrode 608d is used as a mask so as to penetrate the gate electrode 611a and the gate insulating film 603. A low concentration n-type impurity is added to 602 to form a gate overlapped LDD portion 613 (this is the first low concentration n-type impurity addition). Phosphorus or arsenic may be used as the low concentration n-type impurity.
[0073]
Next, the n-channel TFT, the pixel TFT, and the logical operation circuit TFT of the driving circuit TFT are masked with a resist, and further, the gate electrode 608d is used as a mask so as to penetrate the gate electrode 611a and the gate insulating film 603. A low concentration p-type impurity is added to 602 to form a gate overlapped LDD portion 613 (this is the first low concentration p-type impurity addition). As the low concentration p-type impurity, boron or the like may be used.
[0074]
Next, the gate electrode 611a is selectively etched and processed using the gate electrodes 608d and 608e as a mask to form the gate electrode 611b.
[0075]
Next, the portions of the driver circuit TFT and the logic operation circuit TFT that are to be p-channel TFTs are masked with a resist, and the gate electrodes 608d, 608e, and 611b are used as masks to penetrate the gate insulating film 603, and the pixel TFT and A low-concentration n-type impurity is added to the n-channel TFT semiconductor film 602 of the logic operation circuit TFT to form an LDD portion 615 (this is a second low-concentration n-type impurity addition). As the n-type impurity, phosphorus, arsenic, or the like may be used.
[0076]
Next, the portions of the driving circuit TFT, the pixel TFT, and the logic operation circuit TFT, which are n-channel TFTs, are masked with a resist, and the gate electrodes 608d, 608e, and 611b are used as a mask to penetrate the gate insulating film 603, A low-concentration p-type impurity is added to the semiconductor film 602 of the p-channel TFT of the logical operation circuit TFT to form an LDD portion 615 (this is a second low-concentration p-type impurity addition). As the p-type impurity, boron or the like may be used.
[0077]
The size and impurity concentration in the gate overlapped LDD part, LDD part, and source (or drain) part are intended to suppress the hot carrier deterioration in the driving circuit TFT and the logic operation circuit TFT. Since the pixel TFT varies depending on how much the off-leakage current is intended to be suppressed, the pixel TFT may be appropriately adjusted for each purpose. In the present embodiment, it is assumed that the addition amount in the first n-type impurity addition and the addition amount in the second n-type impurity addition are larger.
[0078]
Next, after the interlayer insulating film 617 is formed, the added impurity is activated and hydrogenated, and then acrylic is applied for the purpose of planarizing the surface of the interlayer insulating film. Form.
[0079]
Next, after opening a contact hole by patterning and etching, a wiring 619 is further formed.
[0080]
A pixel electrode 620 is formed on the wiring 619 using ITO (Indium Tin Oxide) which is a transparent conductive film. In this embodiment mode, a region in which the pixel electrode 620 and the wiring 619 are stacked is provided, and the pixel electrode 620 and the wiring 619 are directly electrically connected without forming a contact hole.
[0081]
Through the above process, a TFT array substrate having a logic circuit TFT, a pixel TFT, and a drive circuit TFT on the same substrate is manufactured. Although not described in this embodiment, cleaning and heat treatment steps are added as necessary. Further, as shown in this embodiment, multilayer wiring may be formed by repeatedly forming an interlayer insulating film and wiring.
[0082]
[Embodiment 5]
By using the TFT array substrate manufactured in Embodiment 4, a CPU (Central Processing Unit) is incorporated on the same substrate using a good TFT that does not have a defect such that a cavity is formed below the gate electrode. A liquid crystal display device in which the peripheral circuit and the display are integrated can be manufactured. As a result, the liquid crystal display device can be multifunctional and compact. Hereinafter, a description will be given with reference to FIGS.
[0083]
An alignment film 802a is formed on the TFT array substrate 801 manufactured according to Embodiment 4 on the side where the TFT is formed. The alignment film 802a is formed using an offset printing method. A polyimide resin is used as the material of the alignment film 802a, but a polyamic resin or the like may be used. Next, the alignment film 802a is rubbed so that the liquid crystal molecules are aligned with a certain pretilt angle.
[0084]
Next, the counter substrate 810 is manufactured. A light shielding film 812 is formed over the substrate 811. The light shielding film 812 is formed by depositing metallic chromium, photolithography and etching. A pixel electrode 813 is formed over the light shielding film 812. The pixel electrode 813 is formed by forming ITO, which is a transparent conductive film, by photolithography and etching. In the case where the color filter 814 is provided between the light-shielding film 812 and the pixel electrode 813, a colored resin of a target color is applied onto the light-shielding film 812 by a spin coat method, and is exposed and developed. The color filter forming process is repeated for each of the red, blue, and green color filters 814a to 814c (not shown here). A protective film 815 is formed to fill and flatten the step between the color filter 814 and the light shielding film 812. The protective film 815 is formed by applying acrylic on the color filter. In addition to acrylic, a flattenable material may be used. When no color filter is provided, the protective film 815 may be omitted.
[0085]
An alignment film 802b is formed on the counter substrate thus manufactured. As in the case of forming on the TFT array substrate, the alignment film 802b is formed using an offset printing method. A polyimide resin is used as the material of the alignment film 802b, but a polyamic resin or the like may be used. Next, the alignment film 802b is rubbed so that the liquid crystal molecules are aligned with a certain pretilt angle. Further, in order to bond the counter substrate and the TFT array, a sealant (not shown) is applied to the counter substrate side, and then the counter substrate 810 is heated in an oven to temporarily cure the sealant. After temporary curing, plastic sphere spacers 816 are dispersed on the side of the counter substrate where the pixel electrodes are formed.
[0086]
A liquid crystal panel 817 is manufactured by accurately bonding the two substrates so that the TFT forming side of the TFT array substrate 801 faces the side of the counter substrate 810 where the pixel electrodes are formed. A filler (not shown) is mixed in the sealant, and the two substrates can be bonded to each other with a uniform interval by the filler and the spacer.
[0087]
Unnecessary portions of the bonded substrates are sheared to form a liquid crystal panel 817 substrate having a desired size. A liquid crystal material 818 is injected into the liquid crystal panel 817. After filling the entire inside of the panel with the liquid crystal material 818, the panel is completely sealed with a sealant (not shown).
[0088]
FIG. 14 is a top view of the liquid crystal panel 817. A scanning signal driving circuit 902a and an image signal driving circuit 902b are provided around the pixel portion 901. Further, a logical operation circuit 902c such as a CPU or a memory is provided. The drive circuit is connected to the external input / output terminal group 904 by a connection wiring group 903. In the pixel portion 901, a gate wiring group extending from the scanning signal driving circuit 802a and a data wiring group extending from the image signal driving circuit 902b intersect to form a pixel, and each pixel holds a pixel TFT. A capacitor and a pixel electrode are provided. The sealant 905 is formed outside the pixel portion 901 and the scanning signal driving circuit 902a, the image signal driving circuit 902b, and the logic operation circuit 902c on the TFT array substrate 908 and inside the external input terminal 904. Outside the liquid crystal panel 817, a flexible printed circuit (FPC) 909 is connected to an external input / output terminal 904, and is connected to each drive circuit by a connection wiring group 903. The external input / output terminal 904 is formed of the same conductive film as the data wiring group. The flexible printed wiring board 906 has copper wiring formed on an organic resin film such as polyimide, and is connected to the external input / output terminal 904 with an anisotropic conductive adhesive.
[0089]
A polarizing plate and a retardation plate are attached so that linearly polarized light in the same direction as the director direction of the liquid crystal molecules of the liquid crystal layer closest to the counter substrate is incident on the counter substrate side of the liquid crystal panel 817. A polarizing plate and a retardation plate are attached to the TFT substrate side of the panel so that light in the same direction as the director direction of the liquid crystal molecules in the liquid crystal layer closest to the TFT substrate is emitted.
[0090]
By the above method, a liquid crystal display device in which a peripheral circuit in which a CPU (Central Processing Unit) is incorporated on the same substrate and a display are integrated is created. Although not described in this embodiment, cleaning and heat treatment steps are added as necessary.
[0091]
[Embodiment 6]
By using the method for manufacturing a semiconductor device of the present invention, a system-on-panel in which a display screen (display) and a peripheral circuit incorporating a CPU are integrated can be manufactured. As a result, the production and inspection process of the display can be shortened and the cost can be reduced. In addition, the display can be made multifunctional and compact.
[0092]
FIG. 15 illustrates an example of an electronic device on which a system-on-panel manufactured using the method for manufacturing a semiconductor device of the present invention is mounted.
[0093]
FIG. 15 is a diagram of a portable information terminal. A main body 1431 is provided with a system-on-panel (display unit) 1433, an external interface 1435, operation buttons 1434, and the like. There is a stylus 1432 as an accessory for operation. By mounting the system-on-panel 1433 in the portable information terminal in this way, the information processing function can be further multifunctional while maintaining compact functionality.
[0094]
【The invention's effect】
By selectively removing the buttock using the method for processing the buttock-supporting shaped article of the present invention, when a film is formed on the buttock-supporting shaped article by CVD or sputtering, It is possible to avoid defects such as cavities. Furthermore, the removal of the buttock can be performed by either a dry or wet etching method. In particular, if the wet method is used, it is possible to avoid damage caused by plasma, which is a problem when using the dry method. It is done. In addition, by manufacturing a semiconductor device using a method for manufacturing a semiconductor device using the processing method for a buttock-supported shape according to the present invention, a semiconductor device that avoids the above-described defects, or such a semiconductor An electronic device using the apparatus can be manufactured.
[0095]
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a processing method for a buttock-supporting shaped object according to the present invention.
FIG. 2 is a cross-sectional view of a processing method for a buttock-supported shape.
FIG. 3 is a cross-sectional view of a processing method for a buttocks-supported shape.
FIG. 4 is a cross-sectional view of a method for processing a buttock-supporting shape.
FIG. 5 is a cross-sectional view of a buttock-supporting shape.
FIG. 6 is a schematic diagram showing a relationship between an exposure amount and a residual film amount of a resist.
FIG. 7 is a process cross-sectional view of a method for manufacturing a semiconductor device using a processing method for a buttock-supporting shape.
FIG. 8 is a process cross-sectional view of a method for manufacturing a semiconductor device using a processing method for a buttock-supporting shape.
FIG. 9 is a process cross-sectional view of a method for manufacturing a semiconductor device using a processing method for a buttock-supporting shape.
FIG. 10 is a process cross-sectional view of a method for manufacturing a semiconductor device using a processing method for a buttock-supporting shape.
FIG. 11 is a process cross-sectional view of a method for manufacturing a semiconductor device using a processing method for a buttock-supporting shape.
FIG. 12 is a process cross-sectional view of a method for manufacturing a semiconductor device using a processing method for a buttock-supported shape.
FIG. 13 is a cross-sectional view of part of a liquid crystal display device.
FIG. 14 is a top view of the entire liquid crystal display device.
15A and 15B are electronic devices each including a liquid crystal display device using the method for manufacturing a semiconductor device of the present invention.

Claims (4)

Covering a heel-supporting shaped object having a heel extending in a lateral direction, a laterally obliquely upward direction or a laterally obliquely downward direction at a tip portion extending in a columnar shape with a first photosensitive resin film,
By exposing and developing the first photosensitive resin film, a second photosensitive resin film is obtained,
Exposing the surface of the collar part of the collar part supporting mold from the second photosensitive resin film,
A method for processing a buttock-supporting shaped object, wherein a part of the buttock-supporting shaped object is etched using the second photosensitive resin film as a mask. Cover the bowl-shaped hard mask formed on the gate electrode with the first photosensitive resin film,
By exposing and developing the first photosensitive resin film, a second photosensitive resin film is obtained,
Exposing the surface of the hard mask from the second photosensitive resin film;
A method for manufacturing a semiconductor device, wherein the hard mask is etched using the second photosensitive resin film as a mask. Covering an insulating film having a collar formed on a wiring group in which a plurality of wirings are formed with a first photosensitive resin film,
By exposing and developing the first photosensitive resin film, a second photosensitive resin film is obtained,
Exposing the surface of the insulating film from the second photosensitive resin film;
A method for manufacturing a semiconductor device, characterized in that a part of the insulating film is etched using the second photosensitive resin film as a mask. Covering the bowl-shaped antireflection film formed on the gate electrode with the first photosensitive resin film,
By exposing and developing the first photosensitive resin film, a second photosensitive resin film is obtained,
Exposing the surface of the antireflection film from the second photosensitive resin film;
A method for manufacturing a semiconductor device, wherein the antireflection film is etched using the second photosensitive resin film as a mask.

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