JP3943643B2 - Clock tree design method and apparatus for semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock tree design method and apparatus for a semiconductor integrated circuit, and to a clock tree design method and apparatus for a semiconductor integrated circuit that supplies a clock signal to each part of the semiconductor integrated circuit.
In recent years, with the shortening of the design period of large-scale and highly integrated semiconductor integrated circuits, clock tree design automation using synthesis tools and automatic layout tools is required to automate the design from logic description to layout. ing.
[0002]
[Prior art]
A conventional clock tree design method will be described with reference to FIG. First, as shown in FIG. 14A, consider a case in which a circuit that supplies a clock supplied from the clock input terminal 10 to the terminal flip-flops 12, 13, and 14 through the input clock buffer 11 is configured as design data. .
[0003]
FIG. 13 shows a conventional system flowchart. In step S10, a clock tree is generated for the design data by a synthesis tool that automatically inserts clock driver cells. In this step, the delay time from the input clock buffer 11 to the terminal flip-flops 12 to 14 is minimized, and the delay time is obtained from the temporary wiring capacity. As a result, as shown in FIG. 14B, a clock tree is obtained in which clock driver cells 15, 16, and 17 are inserted corresponding to the terminal flip-flops 12, 13, and 14, respectively. In this case, the wiring capacities from the input clock buffer 11 to the terminal flip-flops 12, 13, and 14 are all considered to be the same.
[0004]
Further, the above clock tree is laid out by an automatic layout tool.
In this step, the wiring is performed so that the wiring from each of the clock driver cells 15 to 17 to the terminal flip-flops 12 to 14 has the same length. Thereby, a chip layout as shown in FIG. 14C is obtained. Note that a plurality of flip-flops are generally connected to each of the clock driver cells 15 to 17.
[0005]
[Problems to be solved by the invention]
In large-scale and large-scale semiconductor integrated circuits, if flip-flops are arranged so that all the wires from the clock driver cell to the terminal flip-flops have the same wiring length, the degree of freedom of arrangement of circuit elements is reduced. In other words, there is a problem that an automatic layout method that enables high integration by adjusting all the inter-element wirings in the integrated circuit to the shortest is not effective.
[0006]
The present invention has been made in view of the above points, and provides a clock tree design method and apparatus for a semiconductor integrated circuit that can be highly integrated by adjusting all the inter-element wirings in the integrated circuit to be the shortest. For the purpose.
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a clock tree design method for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit.
Pre-layout is performed to increase the degree of integration of the semiconductor integrated circuit,
Based on the preliminary layout result, the input clock buffer supplied with the clock from the outside and the Manhattan length , which is the shortest distance between the wirings of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit , are investigated. And
Based on the Manhattan length, insert a clock driver to keep the delay time from the input clock buffer to each terminal flip-flop small,
A clock tree is synthesized so that the delay time from the input clock buffer estimated from the Manhattan length to each terminal flip-flop is substantially the same,
Based on the synthesized clock tree, the wiring is performed so that the wiring length from each clock driver cell to each terminal flip-flop is the shortest.
[0008]
In this way, the device is arranged so as to increase the degree of integration by the prior layout, and then the clock capacity is estimated from the Manhattan length to each terminal flip-flop so that the delay time to each terminal flip-flop is reduced. Synthesize the clock tree so that the delay time from the input clock buffer estimated from the Manhattan length to each terminal flip-flop is substantially the same, and the wiring length from each clock driver to each terminal flip-flop is the shortest Therefore, the delay time from the clock input terminal to each terminal flip-flop can be made substantially the same, and the degree of integration of the semiconductor integrated circuit can be increased.
[0009]
According to a second aspect of the present invention, there is provided a clock tree design method for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit.
Pre-layout is performed to increase the degree of integration of the semiconductor integrated circuit,
Based on the preliminary layout result, the input clock buffer supplied with the clock from the outside and the Manhattan length , which is the shortest distance between the wirings of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit , are investigated. And
Based on the Manhattan length of each of the plurality of terminal flip-flops, a PLL circuit that outputs a plurality of clocks having different delay amounts according to each terminal flip-flop is designed so that the phase of each terminal flip-flop is substantially the same. ,
The clock output from the input clock buffer is supplied to the PLL circuit, and a plurality of clocks with different delay amounts output from the PLL circuit are connected to corresponding terminal flip-flops to synthesize a clock tree. And
Based on the synthesized clock tree, the wiring is performed so that the wiring length from the PLL circuit to each terminal flip-flop is the shortest.
[0010]
In this way, element layout is performed so as to increase the degree of integration by pre-layout, and then the delay amount is estimated from the Manhattan length to each terminal flip-flop so that the clock phase is substantially the same in each terminal flip-flop. Since the PLL circuit is designed with a plurality of clocks with different delay amounts, and the PLL circuit is connected between the input clock buffer and the terminal flip-flop for layout, the phase of the clock at each terminal flip-flop is omitted. Can be the same.
[0011]
According to a third aspect of the present invention, there is provided a clock tree design apparatus for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit.
Pre-layout means for performing pre-layout so as to increase the degree of integration of the semiconductor integrated circuit;
Based on the preliminary layout result, the input clock buffer supplied with the clock from the outside and the Manhattan length , which is the shortest distance between the wirings of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit , are investigated. Investigation means to perform,
Based on the Manhattan length, a clock driver is inserted so as to suppress a delay time from the input clock buffer to each terminal flip-flop, and from the input clock buffer estimated from the Manhattan length to each terminal flip-flop. Synthesizing means for synthesizing the clock tree so that the delay times of
Layout means for performing layout by wiring so as to minimize the wiring length from each clock driver cell to each terminal flip-flop based on the synthesized clock tree.
[0012]
Thus, by providing the pre-layout means, the investigation means, the synthesizing means, and the layout means, the method of claim 1 can be realized, and a highly integrated semiconductor integrated circuit can be designed.
According to a fourth aspect of the present invention, there is provided a clock tree design apparatus for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit.
Pre-layout means for performing pre-layout so as to increase the degree of integration of the semiconductor integrated circuit;
Based on the preliminary layout result, the input clock buffer supplied with the clock from the outside and the Manhattan length , which is the shortest distance between the wirings of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit , are investigated. Investigation means to perform,
Based on the Manhattan length of each of the plurality of terminal flip-flops, a PLL circuit that outputs a plurality of clocks having different delay amounts according to each of the terminal flip-flops is designed so that the phase of each terminal flip-flop is substantially the same. PLL design means;
The clock output from the input clock buffer is supplied to the PLL circuit, and a plurality of clocks with different delay amounts output from the PLL circuit are connected to corresponding terminal flip-flops to synthesize a clock tree. A synthesis means to
Based on the synthesized clock tree, the wiring is performed so that the wiring length from the PLL circuit to each terminal flip-flop is the shortest.
[0013]
Thus, by providing the pre-layout means, the investigation means, the PLL design means, the synthesis means, and the layout means, the method of claim 2 can be realized, and a highly integrated semiconductor integrated circuit can be designed. It becomes.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 shows a system configuration diagram of the present invention. In the figure, a computer main body 1 executes various processes described later, and is connected to a hard disk device 2, a keyboard and other input device 3, a display device 4, and a printing device 5 for storing design data of a semiconductor integrated circuit. Yes. The hard disk device 2 includes basic data 2a before layout, pre-layout data 2b obtained by pre-layout processing, Manhattan length data 2c obtained by survey processing, synthetic data 2d obtained by synthesis processing, and layout obtained by layout processing. The design data of the semiconductor integrated circuit such as data 2e and PLL design data 2f obtained by the PLL design processing is stored.
[0015]
FIG. 1 shows a system flowchart of an embodiment of the present invention. In the figure, in the pre-layout process in step S30, the basic data 2a is made conscious of the clock tree so that the wiring length between all elements is minimized so as to increase the degree of integration of circuit elements including flip-flops. Layout is performed to obtain pre-layout data 2b. FIG. 3 shows the clock input terminal 20, the input clock buffer 21, the terminal flip-flops 22, 23, 24, and the wiring between them, which are laid out by the pre-layout process. This semiconductor integrated circuit is a logic circuit, and is composed of a sequential circuit such as a flip-flop and various combinational circuits such as an AND circuit and an OR circuit. Various kinds of circuits are provided around the terminal flip-flops 22 to 24. The combinational circuit is arranged.
[0016]
In the next step S40, the pre-layout data 2b is checked to obtain Manhattan length data 2c. Here, in the pre-layout shown in FIG. 3 , the Manhattan length , which is the shortest distance of the wiring from the input clock buffer 21 to each of the terminal flip-flops 22, 23, 24 , is calculated. The Manhattan length is used to approximate the wiring capacity. The Manhattan length from the input clock buffer 21 to the terminal flip-flops 22 and 24 is α, and the Manhattan length from the input clock buffer 21 to the terminal flip-flop 23 is 2α. It is.
[0017]
In the synthesizing process of step S50, the pre-layout data 2b and the Manhattan length data 2c are used, and clock driver cells are automatically inserted so as to minimize the delay time from the input clock buffer 21 to the terminal flip-flops 22 to 24, and the clock tree. Are combined to obtain composite data 2d. The delay time at this time corresponds to the wiring capacity approximated by the Manhattan length. FIG. 4 shows a clock tree obtained by this synthesis process. Here, flip-flops 22 and 24 having a Manhattan length of α are connected to the output terminal of the inserted clock driver cell 25, and a terminal flip-flop 23 having a Manhattan length of 2α is connected to the output terminal of the inserted clock driver cell 26. It is connected.
[0018]
In other words, the clock driver cell 25 has a wiring capacity corresponding to the wiring length 2α (= α + α) of the wiring connected to each of the terminal flip-flops 22 and 24. The clock driver 26 has a wiring capacity corresponding to the wiring length 2α of the wiring connected to the terminal flip-flop 23. For this reason, the delay time from the input clock buffer 21 to each of the terminal flip-flops 22 to 24 is the same.
[0019]
In the next step S50, layout processing is performed using the composite data 2d to obtain layout data 2e. Here, the layout in advance layout processing is the basic, and the clock tree configuration obtained by the synthesis processing is used so that the wiring lengths from the clock driver cells 25 and 26 to the terminal flip-flops 22 to 23 are minimized. I do.
[0020]
As a result, the layout shown in FIG. 5 is obtained. In FIG. 5, the output terminal of the clock driver cell 25 is connected to a substantially middle position of the wiring connecting the terminal flip-flops 22 and 24 in the shortest time, and the output terminal of the input clock buffer 21 is connected to the input terminal of the clock driver cell 25. At the same time, it is connected to an input terminal of a clock driver cell 26 arranged adjacent to the clock driver cell 25. The output terminal of the clock driver cell 26 and the flip-flop 23 are connected by a wiring that connects the shortest.
[0021]
Step S30 corresponds to the pre-layout means, step S40 corresponds to the investigation means, step S50 corresponds to the synthesis means, and step S60 corresponds to the layout means.
FIG. 6 shows an embodiment of the circuit arrangement of the semiconductor integrated circuit according to the first embodiment of the present invention. This semiconductor integrated circuit has a very high degree of integration, and disposing the combinational circuit element related to each of the terminal flip-flops FF1 to FF10 close to the corresponding flip-flop increases the wiring length, so that the entire chip is between the elements. When the wiring length is made shorter, the flip-flop itself cannot be arranged preferentially.
[0022]
In the clock tree of this semiconductor integrated circuit, all the wirings from the input clock buffer 30 through the clock driver cell 31 and the clock driver cells 32 to 36 to the terminal flip-flops FF1 to FF10 are not of equal wiring length. However, since the clock driver cells 32 to 36 are arranged based on the Manhattan length when the terminal flip-flops FF1 to FF10 are pre-laid out, the delay time from the input clock buffer 30 to each of the terminal flip-flops FF1 to FF10 is Substantially the same, that is, the delay time difference can be kept small. A broken line in the figure indicates a position where the delay time from the clock driver cell 31 is substantially the same.
[0023]
On the other hand, FIG. 7 shows an example of a circuit arrangement of a semiconductor integrated circuit according to a conventional method. In FIG. 7, clock driver cells 42 to 45 are arranged on a broken line where the delay time from the clock driver cell 41 is substantially the same. The wiring lengths from the clock driver cells 42 to 45 to the terminal flip-flops FF11 to FF18 are substantially the same.
[0024]
In this case, since each of the terminal flip-flops FF11 to FF18 is arranged at some distance, a combinational circuit related to these is arranged in the vicinity of each of the terminal flip-flops FF11 to FF18. Terminal flip-flops FF4 to FF6 as shown in FIG. 6 cannot be arranged between the FF 17 and the degree of integration of the semiconductor integrated circuit cannot be increased.
[0025]
FIG. 8 shows a system flowchart of the second embodiment of the present invention. In the figure, in the pre-layout process in step S70, the basic data 2a is made conscious of the clock tree so that the wiring length between all elements is minimized so as to increase the degree of integration of circuit elements including flip-flops. Layout is performed to obtain pre-layout data 2b. FIG. 9 shows the clock input terminal 50, the input clock buffer 51, the terminal flip-flops 52, 53, 54, and the wiring between them, which are laid out by the pre-layout process. This semiconductor integrated circuit is a logic circuit, and is composed of a sequential circuit such as a flip-flop and various combinational circuits such as an AND circuit and an OR circuit. Various kinds of circuits are provided around each of the terminal flip-flops 52 to 54. The combinational circuit is arranged.
[0026]
In the next step S80, the pre-layout data 2b is checked to obtain Manhattan length data 2c. Here, in the prior layout shown in FIG. 9 , the Manhattan length , which is the shortest distance of the wiring from the input clock buffer 51 to each of the terminal flip-flops 52, 53, 54 , is calculated. This Manhattan length is used to approximate the delay amount, and the Manhattan lengths from the input clock buffer 51 to the terminal flip-flops 52 to 54 are α, 2α, and 3α, respectively.
[0027]
In step S90, PLL (phase locked loop) circuit design processing is performed using the above-described Manhattan length data 2c to obtain PLL design data 2f. Here, as shown in FIG. 10, a PLL circuit 60 that outputs a plurality of clocks with different delay amounts is designed. The PLL circuit 60 includes a PLL cell 61 and clock delay cells 62 and 63. The PLL cell 61 compares the phase of the clock supplied from the input clock buffer 51 with the feedback clock supplied from the terminal 64, and outputs a clock having the same phase as the feedback clock. The clock output from the PLL cell 61 is output from the terminal X 3 and supplied to the clock delay cell 62.
[0028]
The clock delay cell 62 delays the supplied clock by a delay amount corresponding to the Manhattan length α, outputs it from the terminal X 2, and supplies it to the clock delay cell 63. The clock delay cell 63 delays the supplied clock by a delay amount corresponding to the Manhattan length α and outputs it from the terminal X1. Thus, the clock output from the terminal X2 is advanced by the Manhattan length α with respect to the clock output from the terminal X1, and the clock output from the terminal X3 is further advanced by the Manhattan length α with respect to the terminal X2. It is out.
[0029]
In step S100, the preliminary layout data 2b, the Manhattan length data 2c, and the PLL design data 2f are used to connect the terminal X1 of the PLL circuit 60 to the clock input terminal of the terminal flip-flop 52 and connect the terminal X2 to the terminal flip-flop 53. The clock data is connected to the clock input terminal, and the terminal X3 is connected to the clock input terminal of the terminal flip-flop 54 to obtain the synthesized data 2d from the clock tree as shown in FIG. Further, here, wiring is performed so that the clock supplied to the terminal flip-flop 54 having the maximum Manhattan length of 3α is fed back to the terminal 64 of the PLL circuit 60.
[0030]
In the next step S110, layout processing is performed using the composite data 2d to obtain layout data 2e. Here, the PLL circuit 60 is disposed in the vicinity of the input clock buffer 51, and the terminal flip-flops 52 to 54 are disposed in advance layout processing, and the Manhattan length from the PLL circuit 60 is approximately α, 2α, and 3α, respectively. Therefore, wiring is performed so that the wiring length from the PLL circuit 60 to each of the terminal flip-flops 52 to 54 is the shortest.
[0031]
FIG. 12 shows an embodiment of a circuit arrangement of a semiconductor integrated circuit according to the second embodiment of the present invention. This semiconductor integrated circuit has a very high degree of integration, and disposing the combinational circuit elements related to the terminal flip-flops FF20 to FF29 close to the corresponding flip-flops increases the wiring length, and the wiring length of the entire chip. If the length is shortened, the flip-flop itself cannot be arranged preferentially.
[0032]
In the clock tree of this semiconductor integrated circuit, the wiring lengths from the input clock buffer 70 to the terminal flip-flops FF20 to FF29 are different. However, since the delay amount of the clock output from the PLL circuit 71 is adjusted based on the Manhattan length investigated in advance, the phases of the clocks in the terminal flip-flops FF20 to FF29 are substantially the same.
[0033]
Also, since the clock supplied to the terminal flip-flop FF22 having the longest Manhattan length is fed back to the PLL circuit 71, the delay time difference between the clock input to the PLL circuit 71 and the clock supplied to the terminal flip-flop FF22 is calculated. It can be kept small.
[0034]
【The invention's effect】
As described above, the invention according to claim 1 is a clock tree design method for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit.
Pre-layout is performed to increase the degree of integration of the semiconductor integrated circuit,
Based on the preliminary layout result, the input clock buffer supplied with the clock from the outside and the Manhattan length , which is the shortest distance between the wirings of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit , are investigated. And
Based on the Manhattan length, insert a clock driver to keep the delay time from the input clock buffer to each terminal flip-flop small,
A clock tree is synthesized so that the delay time from the input clock buffer estimated from the Manhattan length to each terminal flip-flop is substantially the same,
Based on the synthesized clock tree, the wiring is performed so that the wiring length from each clock driver cell to each terminal flip-flop is the shortest.
[0035]
In this way, the device is arranged so as to increase the degree of integration by the prior layout, and then the clock capacity is estimated from the Manhattan length to each terminal flip-flop so that the delay time to each terminal flip-flop is reduced. Synthesize the clock tree so that the delay time from the input clock buffer estimated from the Manhattan length to each terminal flip-flop is substantially the same, and the wiring length from each clock driver to each terminal flip-flop is the shortest Therefore, the delay time from the clock input terminal to each terminal flip-flop can be made substantially the same, and the degree of integration of the semiconductor integrated circuit can be increased.
[0036]
According to a second aspect of the present invention, there is provided a clock tree design method for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit.
Pre-layout is performed to increase the degree of integration of the semiconductor integrated circuit,
Based on the preliminary layout result, the input clock buffer supplied with the clock from the outside and the Manhattan length , which is the shortest distance between the wirings of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit , are investigated. And
Based on the Manhattan length of each of the plurality of terminal flip-flops, a PLL circuit that outputs a plurality of clocks having different delay amounts according to each terminal flip-flop is designed so that the phase of each terminal flip-flop is substantially the same. ,
The clock output from the input clock buffer is supplied to the PLL circuit, and a plurality of clocks with different delay amounts output from the PLL circuit are connected to corresponding terminal flip-flops to synthesize a clock tree. And
Based on the synthesized clock tree, the wiring is performed so that the wiring length from the PLL circuit to each terminal flip-flop is the shortest.
[0037]
In this way, element layout is performed so as to increase the degree of integration by pre-layout, and then the delay amount is estimated from the Manhattan length to each terminal flip-flop so that the clock phase is substantially the same in each terminal flip-flop. Since the PLL circuit is designed with a plurality of clocks with different delay amounts, and the PLL circuit is connected between the input clock buffer and the terminal flip-flop for layout, the phase of the clock at each terminal flip-flop is omitted. Can be the same.
[0038]
According to a third aspect of the present invention, there is provided a clock tree design apparatus for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit.
Pre-layout means for performing pre-layout so as to increase the degree of integration of the semiconductor integrated circuit;
Based on the preliminary layout result, the input clock buffer supplied with the clock from the outside and the Manhattan length , which is the shortest distance between the wirings of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit , are investigated. Investigation means to perform,
Based on the Manhattan length, a clock driver is inserted so as to reduce the delay time from the input clock buffer to each terminal flip-flop, and the input clock buffer estimated from the Manhattan length to each terminal flip-flop A synthesis means for synthesizing the clock tree so that the delay times are substantially the same;
Layout means for performing layout by wiring so as to minimize the wiring length from each clock driver cell to each terminal flip-flop based on the synthesized clock tree.
[0039]
Thus, by providing the pre-layout means, the investigation means, the synthesizing means, and the layout means, the method of claim 1 can be realized, and a highly integrated semiconductor integrated circuit can be designed.
According to a fourth aspect of the present invention, there is provided a clock tree design apparatus for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit.
Pre-layout means for performing pre-layout so as to increase the degree of integration of the semiconductor integrated circuit;
Based on the preliminary layout result, the input clock buffer supplied with the clock from the outside and the Manhattan length , which is the shortest distance between the wirings of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit , are investigated. Investigation means to perform,
Based on the Manhattan length of each of the plurality of terminal flip-flops, a PLL circuit that outputs a plurality of clocks having different delay amounts according to each of the terminal flip-flops is designed so that the phase of each terminal flip-flop is substantially the same. PLL design means;
The clock output from the input clock buffer is supplied to the PLL circuit, and a plurality of clocks with different delay amounts output from the PLL circuit are connected to corresponding terminal flip-flops to synthesize a clock tree. A synthesis means to
Based on the synthesized clock tree, the wiring is performed so that the wiring length from the PLL circuit to each terminal flip-flop is the shortest.
[0040]
Thus, by providing the pre-layout means, the investigation means, the PLL design means, the synthesis means, and the layout means, the method of claim 2 can be realized, and a highly integrated semiconductor integrated circuit can be designed. It becomes.
[Brief description of the drawings]
FIG. 1 is a system flowchart of the present invention.
FIG. 2 is a system configuration diagram of the present invention.
FIG. 3 is a diagram for explaining the present invention.
FIG. 4 is a diagram for explaining the present invention.
FIG. 5 is a diagram for explaining the present invention.
FIG. 6 is a diagram showing an embodiment of a circuit arrangement according to the method of the present invention.
FIG. 7 is a diagram illustrating an example of a circuit arrangement according to a conventional method.
FIG. 8 is a system flowchart of the present invention.
FIG. 9 is a diagram for explaining the present invention.
FIG. 10 is a diagram for explaining the present invention.
FIG. 11 is a diagram for explaining the present invention.
FIG. 12 is a diagram for explaining the present invention.
FIG. 13 is a conventional system flowchart.
FIG. 14 is a diagram for explaining a conventional technique.
[Explanation of symbols]
20 clock input terminals 21, 40 input clock buffers 22-24, FF1-FF10 terminal flip-flops 25, 26, 31-36 clock driver cells S30, S70 pre-layout processing S40, S80 investigation processing S50, S100 synthesis processing S60, S110 layout Process S90 PLL design process

Claims (4)

In a clock tree design method of a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit,
Pre-layout is performed to increase the degree of integration of the semiconductor integrated circuit,
Based on the result of the previous layout, the input clock buffer supplied with the clock from the outside and the Manhattan length of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit are calculated and investigated,
Based on the Manhattan length, insert a clock driver to keep the delay time from the input clock buffer to each terminal flip-flop small,
A clock tree is synthesized so that the delay time from the input clock buffer estimated from the Manhattan length to each terminal flip-flop is substantially the same,
A clock tree design method for a semiconductor integrated circuit, wherein wiring is performed so as to minimize the wiring length from each clock driver cell to each terminal flip-flop based on the synthesized clock tree. In a clock tree design method of a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit,
Pre-layout is performed to increase the degree of integration of the semiconductor integrated circuit,
Based on the result of the previous layout, the input clock buffer supplied with the clock from the outside and the Manhattan length of each of the plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit are calculated and investigated,
Based on the Manhattan length of each of the plurality of terminal flip-flops, a PLL circuit that outputs a plurality of clocks having different delay amounts according to each terminal flip-flop is designed so that the phase of each terminal flip-flop is substantially the same. ,
The clock output from the input clock buffer is supplied to the PLL circuit, and a plurality of clocks with different delay amounts output from the PLL circuit are connected to corresponding terminal flip-flops to synthesize a clock tree. And
A clock tree design method for a semiconductor integrated circuit, wherein wiring is performed so as to minimize the wiring length from the PLL circuit to each terminal flip-flop based on the synthesized clock tree. In a clock tree design apparatus for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit,
Pre-layout means for performing pre-layout so as to increase the degree of integration of the semiconductor integrated circuit;
Based on the preliminary layout result, an investigation means for conducting an investigation by calculating a Manhattan length of each of the input clock buffer supplied with the clock from the outside and a plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit;
Based on the Manhattan length, a clock driver is inserted so as to reduce the delay time from the input clock buffer to each terminal flip-flop, and the input clock buffer estimated from the Manhattan length to each terminal flip-flop A synthesis means for synthesizing the clock tree so that the delay times are substantially the same;
A clock tree design for a semiconductor integrated circuit, comprising: layout means for performing layout by wiring the wiring length from each clock driver cell to each terminal flip-flop to be the shortest based on the synthesized clock tree. apparatus. In a clock tree design apparatus for a semiconductor integrated circuit for designing a clock tree for supplying a clock supplied from the outside of the semiconductor integrated circuit to each part in the semiconductor integrated circuit,
Pre-layout means for performing pre-layout so as to increase the degree of integration of the semiconductor integrated circuit;
Based on the preliminary layout result, an investigation means for conducting an investigation by calculating a Manhattan length of each of the input clock buffer supplied with the clock from the outside and a plurality of terminal flip-flops supplying the clock to each part of the semiconductor integrated circuit;
Based on the Manhattan length of each of the plurality of terminal flip-flops, a PLL circuit that outputs a plurality of clocks having different delay amounts according to each of the terminal flip-flops is designed so that the phase of each terminal flip-flop is substantially the same. PLL design means;
The clock output from the input clock buffer is supplied to the PLL circuit, and a plurality of clocks with different delay amounts output from the PLL circuit are connected to corresponding terminal flip-flops to synthesize a clock tree. A synthesis means to
A clock tree design apparatus for a semiconductor integrated circuit, comprising: layout means for performing layout by wiring the shortest wiring length from the PLL circuit to each terminal flip-flop based on the synthesized clock tree. .

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