JP3948874B2 - Nonvolatile ferroelectric memory device drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a drive circuit for a nonvolatile ferroelectric memory device.
[0002]
In general, nonvolatile ferroelectric memory (FRAM) has a data processing speed comparable to that of DRAM (Dynamic Random Access Memory) and can store data even when the power is turned off. It is attracting attention as an element.
The FRAM is a memory element having almost the same structure as that of a DRAM, and uses a ferroelectric as a capacitor material and uses a high remanent polarization which is a characteristic of the ferroelectric.
Because of such remanent polarization characteristics, data is preserved even if the electric field is removed.
[0003]
FIG. 1 is a characteristic diagram showing a hysteresis loop of a general ferroelectric.
As shown in FIG. 1, it can be seen that the polarization induced by the electric field does not disappear due to the presence of remanent polarization (or spontaneous polarization) even if the electric field is removed, and maintains a constant amount (d, a state).
The nonvolatile ferroelectric memory cell is applied as a memory element by making the d and a states correspond to 1 and 0, respectively.
[0004]
Hereinafter, a conventional driving circuit for a nonvolatile ferroelectric memory device will be described with reference to the accompanying drawings.
FIG. 2 shows a unit cell of a conventional nonvolatile ferroelectric memory.
As shown in FIG. 2, a bit line (B / L) formed in one direction, a word line (W / L) formed in a direction intersecting with the bit line, and a certain interval between the word lines. A plate line (P / L) formed in the same direction as the word line, a transistor T1 whose gate is connected to the word line and whose source is connected to the bit line, and the first terminal of the two terminals is the drain of the transistor T1. The second terminal is composed of a ferroelectric capacitor (FC1) connected to the plate line (P / L). The transistor T1 and the capacitor FC1 constitute one storage cell, that is, a unit cell. Needless to say, a large number of lines are arranged in parallel, and a large number of cells are connected to each line to constitute a memory element. ,
[0005]
A driving circuit for such a conventional nonvolatile ferroelectric memory device is shown in FIGS. 3a and 3b.
The figure shows a driving circuit for driving a conventional ferroelectric memory having a 1T / 1C (one transistor and one ferroelectric capacitor) structure. This circuit has a reference voltage generator 1 for generating a reference voltage, and its output is connected to a reference voltage stabilizer 2. The stabilization unit 2 includes a plurality of transistors Q1 to Q4, a capacitor C1, and the like. Since the reference voltage output from the reference voltage generation unit 1 cannot be immediately supplied to the sense amplifier, the reference voltage of two adjacent bit lines can be obtained. It is for stabilization. The stabilization unit 2 includes a first equalization unit 4, a first reference voltage storage unit 3, a first main cell array unit 5, a first sense amplifier unit 6, a second main cell array unit 7, and a second reference voltage storage unit 8. And the second sense amplifier section 9 are sequentially connected. The first equalization unit 4 includes a transistor Q5, and turns on the transistor Q5 to equalize the voltages of two adjacent bit lines. The first reference voltage storage unit 3 includes a plurality of transistors Q6 and Q7 connected to the bit lines B1 and B2 together with the capacitors C2 and C3, respectively, and logic values “1” and “1” are respectively connected to the connected bit lines. The reference voltage of “0” is stored. Similarly, the first main cell array unit 5 includes a plurality of transistors Q8 and Q9 connected to the bit lines together with the capacitors C5 and C6, and is connected to different word lines and plate lines to store data. In the figure, only one cell is shown in each line for illustration, but many cells are connected. The first sense amplifier unit 6 includes a plurality of transistors Q10 to Q15, a P-sense amplifier (PSA), and the like, and senses data of a cell selected by a word line among a plurality of cells of the first main cell array unit 5. . The second main cell array unit 7 includes a plurality of capacitors C7 and C8 and a plurality of transistors Q26 and Q27. The second main cell array unit 7 has the same configuration as that of the first main cell unit 5, and similarly, the second reference voltage storage unit 8 is also substantially the first. The configuration is the same as that of the reference voltage storage unit 3. The second sense amplifier unit 9 includes a plurality of transistors Q16 to Q25, an N-sense amplifier (NSA), and the like, and senses and outputs data of the second main cell array unit 7.
[0006]
The data input / output operation of the conventional nonvolatile ferroelectric memory device configured as described above will be described below.
FIG. 4 is a timing diagram showing an operation in a write mode of a conventional nonvolatile ferroelectric memory device, and FIG. 5 is a timing diagram showing an operation in a read mode.
First, in the write mode, the chip enable signal (CSBpad) applied from the outside is activated from high to low, and at the same time, the write enable signal (WEBpad) is applied from high to low to start the write mode.
Next, when the address in the write mode is decoded, the pulse applied to the word line corresponding to the address is changed from “low” to “high” to select the cell.
[0007]
In this way, while the word line is maintained in the “high” state, a signal that is initially “high” and then “low” is applied to the plate line.
Then, in order to write a logic value “1” or “0” to the selected cell, a “high” or “low” signal is applied to the selected bit line in synchronization with the write enable signal (WEBpad). That is, when the signal applied to the word line is “high” and the signal applied to the plate line is “low”, if the “high” signal is applied to the bit line, the ferroelectric capacitor Is recorded with a logic value “1”. When a “low” signal is applied to the bit line while the signal applied to the plate line is “high”, a logic value “0” is recorded in the ferroelectric capacitor (FIG. 2). reference).
[0008]
An operation for reading data stored in the cell by the operation in the write mode will be described below.
First, when the chip enable signal (CSBpad) is activated from “high” to “low” from the outside, first, all the bit lines are temporarily set to the “low” voltage by the equalization signal before the word line is selected. To do.
That is, a “high” signal is applied to the equalization unit 4 of FIG. 3 and a “high” signal is applied to the transistors Q16 to Q19. Therefore, these transistors Q5, Q16 to Q19 are turned on, both the bit lines are short-circuited and grounded via the transistor Q19, so that both the bit lines are equipotential to a low voltage (Vss). .
[0009]
Next, these transistors Q5, Q16 to Q19 are turned off to inactivate each bit line, and then the address is decoded. The word line selected by the decoded address changes from “low” to “high”. Select a cell. A “high” signal is applied to the plate line of the selected cell to destroy the data corresponding to the logic value “1” stored in the ferroelectric memory.
If a logic value “0” is stored in the ferroelectric memory, the corresponding data is not destroyed.
[0010]
As described above, the destroyed data and the undestructed data output different values based on the above-described hysteresis loop principle, and the sense amplifier senses the logic value “1” or “0”. That is, when data is destroyed, it is a case where it is changed from d to f shown in the hysteresis loop of FIG. 1, and when data is not destroyed, it is a case where it is changed from a to f. Therefore, when the sense amplifier is enabled after a predetermined time has elapsed, when data is destroyed, it is amplified and outputs a logic value “1”, and when data is not destroyed, it outputs a logic value “0”. At that time, the reference cell is referred to for each reading for comparison.
As described above, after data is output from the sense amplifier, the original data must be restored, so that the plate line is inactivated from “high” to “low” with the “high” signal applied to the word line. .
[0011]
[Problems to be solved by the invention]
However, the conventional nonvolatile ferroelectric memory device as described above has the following problems.
The characteristics of the ferroelectric film described above are still not perfect. Therefore, in the prior art, one reference cell is configured to be used for a read operation of a main cell that is approximately several hundred times more, so the reference cell must operate more than the main cell. The deterioration characteristic of the reference cell is abruptly deteriorated, and the reference voltage becomes unstable.
This becomes a factor of deteriorating the operation characteristics of the element and shortening the lifetime.
There is also a problem that the configuration of the drive circuit is complicated.
[0012]
The present invention has been made in order to solve the above-described problems of the prior art, and by simplifying the configuration of the word line driving unit, the boosted voltage is applied to the word line without losing the threshold voltage. An object of the present invention is to provide a driving circuit for a nonvolatile ferroelectric memory element that can be applied well, improve the current driving capability, and can efficiently use the layout area.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a driving circuit for a nonvolatile ferroelectric memory device according to a first embodiment of the present invention includes a plurality of split word lines in which a first split word line and a second split word line are paired. A cell array unit comprising a unit cell in which a pair is arranged, a plurality of bit lines are arranged in a direction crossing the split word line pair, and a switching transistor and a ferroelectric capacitor are arranged between the split word line pair and the bit line A non-volatile ferroelectric memory device comprising: an X address signal output unit comprising a plurality of transistors connected in series to a global word line controlled by a global X decoder unit, and controlled by an output voltage of each transistor. Drive the first and second split word line pairs A split word line drive signal output unit composed of a plurality of transistors for outputting a drive signal for output and a global word line and first and second split word lines, respectively, to bypass the floating voltage of the split word line And a bypass unit composed of a plurality of transistors.
[0014]
In the driving circuit for the nonvolatile ferroelectric memory device according to the second embodiment of the present invention, the first split word line and the second split word line are paired to form a plurality of split word line pairs. A plurality of bit lines are arranged in a direction crossing the word line pair, and a non-volatile strong memory having a cell array unit composed of a unit cell composed of a switching transistor and a ferroelectric capacitor between the split word line pair and the bit line. A dielectric memory device, controlled by an X address signal output unit composed of a plurality of transistors connected in series to a global word line controlled by a global X decoder unit, and an output voltage of each transistor. Drive signal for driving split word line pair A split word line drive signal output unit composed of a plurality of transistors for outputting a plurality of transistors, and a plurality of transistors for bypassing the floating voltage of the split word line, each being formed between the global word line and the first and second split word lines. And a bypass section made up of transistors.
[0015]
Next, in the driving circuit of the nonvolatile ferroelectric memory device according to the third embodiment of the present invention, a plurality of split word line pairs are arranged such that the first split word line and the second split word line are paired, and the split word line is split. A plurality of bit lines are arranged in a direction crossing the word line pair, and a non-volatile strong memory having a cell array unit composed of a unit cell composed of a switching transistor and a ferroelectric capacitor between the split word line pair and the bit line. A dielectric memory device, which is controlled by an X address signal output unit composed of a plurality of transistors connected in series to a global word line controlled by a global X decoder unit, and an output voltage of each transistor. Drive signal for driving split word line pair A split word line drive signal output unit composed of a plurality of transistors for outputting a plurality of transistors, and a plurality of transistors for bypassing the floating voltage of the split word line, each being formed between the global word line and the first and second split word lines. And a bypass section made up of transistors.
[0016]
In the nonvolatile ferroelectric memory device driving circuit according to the fourth embodiment of the present invention, a plurality of transistors are connected in series to a bit line, and a word line is connected to the gate of each transistor. A non-volatile ferroelectric memory device having a cell array unit composed of multi-NAND cells, which is connected to a global word line controlled by a global X decoder unit and is composed of a plurality of transistors connected in series to each other A signal output unit; and a plurality of transistors that are controlled by the output terminals of the transistors constituting the X address signal output unit and apply a plurality of word line drive signals output from the local X decoder unit to the respective word lines. Word line drive signal output unit and word line drive signal output unit Are respectively formed between the output terminal and the global word line of the transistors constituting, characterized in that it comprises a bypass portion for bypassing a floating voltage of the word line.
[0017]
Next, the nonvolatile ferroelectric memory device driving circuit according to the fifth embodiment of the present invention includes a plurality of transistors connected in series to a bit line and a word line connected to the gate of each transistor. A non-volatile ferroelectric memory device having a cell array section composed of multi-NAND cells, and an X address signal output comprising a plurality of transistors connected in parallel to a global word line controlled by a global X decoder section And a word composed of a plurality of transistors which are controlled by the output terminals of the respective transistors constituting the X address signal output unit and sequentially apply a plurality of word line drive signals output from the local X decoder unit to the word lines. Each of the line drive signal output unit and the word line drive signal output unit Configured respectively between the output terminal and the global word line of the transistor, characterized in that it comprises a bypass portion for bypassing a floating voltage of the word line.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a driving circuit for a nonvolatile ferroelectric memory device according to the present invention will be described with reference to the accompanying drawings. It should be noted that the first and second in this specification are used only to distinguish the same thing so as not to be confused when it is necessary to distinguish by the difference in the arrangement position thereof, and the absolute name is used. It doesn't mean. Therefore, if it is known, only a reference symbol is attached, and it may not be distinguished from the first and second. In addition, the upper, lower, left, and right directions indicating directions are merely on the drawing and do not indicate absolute directions.
FIG. 6 is a configuration diagram of a cell array for explaining a driving circuit of the nonvolatile ferroelectric memory device according to the first embodiment of the present invention.
As shown in FIG. 6, a main cell array unit 61 composed of a plurality of sub-cell arrays, a global X decoder unit 63 formed on one side of the main cell array unit 61, and a main cell array unit 61 on the other side. The split word line driving unit 65 formed, the bit line control unit 67 formed below the main cell array unit 61, and the LC1 formed below the split word line driving unit 65 and applied to the split word line , LC2 signal is output from the local control unit 69. Here, the main cell array unit 61 includes a large number of unit cells including a reference cell array unit.
[0019]
FIG. 7 shows unit cells arranged in the main cell array unit 61 of the present embodiment.
As shown in FIG. 7, this embodiment does not have the configuration of the word line and the plate line, but two word lines in which one word line is arranged in parallel, that is, the first split word line SWL1, and the second The split word line SWL2 is formed. These two word lines are formed side by side at a certain distance. A number of bit lines are arranged so as to be orthogonal to the first and second split word lines SWL1 and SWL2. In the figure, only the first bit line Bit_n and the second bit line Bit_n + 1 are shown. Needless to say, in the case of a cell array, a large number of these word lines and bit lines are arranged in parallel. A switching transistor (referred to as a first transistor) of one of the two unit cells has a gate terminal connected to SWL1, a source terminal connected to the first bit line Bit_n, and a drain terminal connected to the ferroelectric capacitor FC1. Connected to one side. The other terminal of the ferroelectric capacitor FC1 is connected to the second split word line SWL2. Meanwhile, the switching transistor T2 of the other unit cell has a gate terminal connected to the second split word line SWL2, a source connected to the second bit line Bit_n + 1, and a drain terminal connected to one terminal of the ferroelectric capacitor FC2. Has been. The other terminal of the ferroelectric capacitor FC2 is connected to the first split word line SWL1.
[0020]
On the other hand, FIGS. 8a to 8b show the structure shown in FIG. 7 separated into unit cells. When FIGS. 8a and 8b are combined, a memory cell having a pair of two unit cells is formed. .
As shown in FIG. 8a, one unit cell C111 constituting a pair of memory cells includes a first split word line SWL1 and a second split word formed side by side with a certain distance from the first split word line SWL1. The word line SWL2, the first bit line BL11 formed in a direction crossing the word lines SWL1 and SWL2, the gate terminal is connected to the first split word line SWL1, and the source terminal is connected to the first bit line BL11. And a ferroelectric capacitor FC1 formed between the drain terminal of the first switching transistor T1 and the second split word line SWL2.
[0021]
As shown in FIG. 8b, the other unit cell C121 includes a first split word line SWL1, a second split word line SWL2, a second bit line BL12 formed in a direction crossing those word lines, and a gate terminal. Is connected to the second split word line SWL2, and the source terminal is connected to the second bit line BL12, the switching transistor T2, and the ferroelectric formed between the drain of the second switching transistor T2 and the first split word line SWL1. Consists of body capacitor FC2.
[0022]
The memory device of this embodiment is configured by repeating the configuration of FIG. 6 including the main cell array 61 composed of unit cells shown in FIG. 7, but the repetition simply arranges the configuration of the cell array of FIG. 6 as it is. Instead, the global X decoder is arranged to be used in common in the adjacent cell array of FIG. The specific arrangement is shown in FIG.
As shown in FIG. 9, a first main cell array unit 61 is arranged on the right side of the global X decoder unit 63, and a first split word line driving unit 65 is arranged on the right side thereof. A second split word line driving unit 65a is arranged adjacent to the right side of the first split word line driving unit 65, and further to the right side of the second main cell array unit 61a. Although not shown in the figure, a global X decoder unit is arranged on the right side.
Bit line controllers 67 and 67a are arranged under the main cell arrays, and local controllers 69 and 69a are arranged under the split word line drivers.
With this configuration, it can be seen that one global X decoder unit 63 is shared by two main cell array units 61 and 61a and two split word line driving units 65 and 65a.
[0023]
FIG. 10 is a partial detail view of FIG. 9, showing the split word line driver shown in FIG. 6 in more detail.
As shown in the drawing, two split word line driving units 65 and 65a are formed adjacent to each other. As shown in the figure, the first and second split word line drivers 65 and 65a are composed of a plurality of sub-drivers (SD). The drive circuit for the nonvolatile ferroelectric memory element of the present invention relates to this sub drive unit.
The global X decoder unit 63 includes a plurality of global word lines GWL1, GWL2,. . . Each GWLn is controlled. The sub driver SD is connected to each global word line. Each of the split word line driving units 65 and 65a includes sub driving units SD corresponding to the number of global word lines. The global word lines GWL1 to GWLn are commonly connected to the sub drive unit of the first split word line drive unit 65 and the sub drive unit of the second split word line drive unit 65a.
[0024]
FIG. 11 shows the relationship between the signals LC1 and LC2 output from the local control unit of FIG. 9 and the sub driving unit.
As shown in FIG. 11, each of the first and second split word line driving units 65 and 65a has a sub driving unit SD connected to a global word line GWL output from a global X decoder unit (not shown). Operates by signal. The signals LC1 and LC2 output from the local control units 69 and 69a are applied to the first and second split word lines SWL1 and SWL2 of the main cell array units 61 and 61a, respectively.
[0025]
Hereinafter, the driving circuit for the nonvolatile ferroelectric memory device according to the first embodiment of the present invention will be described in more detail.
FIG. 12 shows the “A” portion of FIG. 11 in more detail, and illustrates a driving circuit of the nonvolatile ferroelectric memory device according to the first embodiment of the present invention.
The driving circuit shown in FIG. 12 shows one of a plurality of driving circuits constituting a split word line driving unit.
As shown in FIG. 12, the X address signal output unit 120 including first and second transistors T1 and T2 connected in series to the global word line GWLn output from the global X decoder unit 63, and the drain voltage of each transistor The second control signals LC1 and LC2 that are sequentially controlled by the second local control unit 69a are sequentially applied to the first split word line SWL1 and the second split word line SWL2 of the second main cell array unit 61a. A split word line drive signal output unit 121 including third and fourth transistors T3 and T4, and a fifth transistor T5 and a second split word line SWL2 connected between the first split word line SWL1 and the global word line GWL and the global Between word lines GWL And a bypass portion 123 and a sixth transistor T6 is connected.
Here, the power supply voltage PWR is applied to the gates of the first and second transistors T1 and T2 and the fifth and sixth transistors T5 and T6, and each transistor is composed of an NMOS transistor.
[0026]
The operation of the driving circuit of the nonvolatile ferroelectric memory device according to the first embodiment of the present invention configured as described above is as follows.
When the global word line GWL is “high” and the signals LC1 and LC2 output from the second local control unit 69a are “high”, when the source node N1 of the first transistor T1 becomes “high”, the third Transistor T3 is turned on. Accordingly, the high level LC1 signal is transmitted to the first split word line SWL1 through the third transistor T3.
[0027]
Thereafter, when the drain node N2 of the second transistor T2 becomes high level, the fourth transistor T4 is turned on, and the LC2 signal is transmitted to the second split word line SWL2.
At this time, the bypass unit 123 including the fifth transistor T5 and the sixth transistor T6 serves to bypass the floating voltage of the first split word line SWL1 and the second split word line SWL1.
That is, when the global word line GWL and LC1, LC2 signals are all at a low level, the first split word line SWL1 and the second split word line SWL2 are in a floating state, but at this time, the first and second split word lines The floating voltage induced in is bypassed to the global word line GWL through the fifth transistor T5 and the sixth transistor T6. The fifth and sixth transistors T5 and T6 are composed of NMOS transistors having a very small driving current and always maintain the turn-on state.
In this way, the first and second split word lines SWL1 and SWL2 are not brought into a floating state so that cell data is not unnecessarily selected. This is because cell elements selected unnecessarily remove in advance elements that act as noise on the actual data.
[0028]
FIG. 13 is a timing chart showing the operation of the driving circuit for the nonvolatile ferroelectric memory device according to the first embodiment of the present invention shown in FIG.
Assume that the global word line signal GWL output from the global X decoder unit 63 is activated to a high level between t1 and t5. Since the first and second transistors T1 and T2 constituting the X address signal output unit 120 are on, a high level signal is transmitted to the source nodes N1 and N2 of the first and second transistors T1 and T2. Is done. At this time, since the LC1 and LC2 signals are in a low state during t1, the source node N1 of the first transistor T1 and the source node N2 of the second transistor T2 are not affected.
When the LC1 and LC2 signals transition to a high level during t2, the third and fourth transistors T3 and T4 are turned on by the source nodes N1 and N2 of the first and second transistors T1 and T2, so that the high level The LC1 and LC2 signals are transmitted to the first split word line SWL1 and the second split word line SWL2 through the third and fourth transistors T3 and T4.
At this time, capacitance components exist between the drains of the third and fourth transistors T3 and T4 constituting the split word line drive signal output unit 121 and the source nodes N1 and N2 of the first transistors T1 and T2. Therefore, the voltage at the source nodes N1 and N2 also rises due to the voltage rise at the LC1, LC2, first and second split word lines SWL1, SWL2.
[0029]
When the source node N1 and N2 voltages rise, the first transistor T1 and the second transistor T2 are in the off state with respect to the rising voltages of the source nodes N1 and N2, so that the raised voltages are maintained as they are. Therefore, if the increased voltage is the Vboost voltage, the third and fourth transistors T3 and T4 can transmit the voltage of Vboost−Vtn. Here, Vtn is a threshold voltage of the NMOS transistor. Eventually, the LC1 signal and the LC2 signal can be transmitted to the first and second split word lines SWL1 and SWL2 regardless of the voltages of LC1 and LC2 and without losing Vtn.
[0030]
Next, when only the LC1 signal transitions to the low level at the start of t3, the level of the first split word line SWL1 also transitions to the low level, and the voltage of the source node N1 of the first transistor T1 returns to the state between t1.
Even in this state, the second transistor T2 keeps the off state with respect to the source node N2 voltage, so that the increased voltage (Vboost) is maintained as it is, and the LC2 signal is transmitted to the second split word line SWL2 without any loss of voltage. Is done.
[0031]
Next, at the start of t4, the LC1 signal transitions to the high level again, and the LC2 signal transitions to the low level. When LC2 changes to low level, the voltage of the second split word line SWL2 also changes to low level.
[0032]
On the other hand, when the LC1 signal transitions to the high level, the voltage of the first split word line SWL1 also transitions from the low level to the high level again. Therefore, the source node N1 of the first transistor T1 is again at the raised voltage (Vboost) level. Since the voltage of the source node N1 having the increased voltage level is blocked by the first and second transistors N1 and N2, the LC1 signal is transmitted to the first split word line SWL1 without losing the voltage.
[0033]
Next, LC1 transitions to a low level at the start of t5, and LC1 and LC2 are at a low level during t5.
Accordingly, the first and second split word lines SWL1 and SWL2 are also changed to low and inactivated. When the LC1 and LC2 signals transition to a low level, the voltages of the source nodes N1 and N2 again transition to a level that is controlled by the global word line GWL.
[0034]
Next, during t6, the selected global word line transitions to the low level and is inactivated.
[0035]
On the other hand, a configuration as shown in FIG. 12 is repeated as shown in FIG.
FIG. 14 shows a drive circuit of a nonvolatile ferroelectric memory device having a plurality of split word line pairs, using FIG.
As shown in FIG. 14, a plurality of NMOS transistors T1, T2,. . . , Tn and an X address signal output unit 120 and NMOS transistors T1, T2,. . . , Tn and control signals (LC1_1, LC2_1, LC1_2, LC2_2,... LC1_n, LC2_n) output from the local control unit are supplied to a plurality of pairs of first and second split word lines (SWL1_1, SWL2_1). , SWL1_2, SWL2_2, ... SWL1_n, SWL2_n), a split word line drive signal output unit 121 composed of a plurality of NMOS transistors, and each NMOS transistor constituting the split word line drive signal output unit 121 And a bypass unit 122 composed of a plurality of NMOS transistors for bypassing a floating voltage floating in each split word line. Made.
[0036]
Next, FIG. 15 shows a driving circuit for a nonvolatile ferroelectric memory device according to a second embodiment of the present invention. In the first embodiment, the first transistor T1 and the second transistor T2 are connected in series to the global word line GWL. However, in the second embodiment, it is understood that they are connected in parallel.
Since the following configuration excluding the first and second transistors T1 and T2 is the same as that of the first embodiment, a description thereof will be omitted.
By configuring the first and second transistors T1 and T2 in parallel in this way, the source node N2 of the second transistor T2 has a voltage sufficient to turn on the fourth transistor T4. This is because, if the drain node N2 does not become a sufficiently high level by the second transistor T2, the fourth transistor T4 is not sufficiently opened, and the LC2 signal is not sufficiently transmitted to the second split word line SWL2.
Here, the driving circuit of the nonvolatile ferroelectric memory device according to the second embodiment of the present invention is not shown in the drawing, but as shown in FIG. 14, the nonvolatile ferroelectric memory having a plurality of split word line pairs. It can also be applied to a body memory device.
[0037]
The driving circuit of the nonvolatile ferroelectric memory device according to the first and second embodiments of the present invention described above separately includes the first split word line driving unit 65 and the second split word line driving unit 65a in FIG. It is a thing when it is made to comprise independently.
Here, the first and second split word line driving units 65 and 65a shown in FIG. 11 are not independently configured, and the split main word line 61a and the second main cell array unit 61a are shared. It is also possible to configure the drive unit. In this case, the sub drive unit may be configured as shown in FIG. 16 described below.
That is, FIG. 16 shows a driving circuit for a nonvolatile ferroelectric memory device according to the third embodiment of the present invention. Here, SWL1_L and SWL2_L are split word lines connected to the first main cell array unit 61 in the configuration of FIG. 11, and SWL1_R and SWL2_R are split word lines connected to the second main cell array unit 61a. LC1_L and LC2_L are control signals output from the first local control unit 69, and LC1_R and LC2_R are control signals output from the second local control unit 69a.
[0038]
In the driving circuit of the nonvolatile ferroelectric memory device according to the third embodiment, the global word line GWL connected to the global X decoder unit 63 is formed in one direction, and the X address signal output unit 120 is configured on the global word line GWL. The first transistor T1 and the second transistor T2 connected in series are controlled by the voltage of the source node N1 of the first transistor T1, and transmit the LC1_L signal to the SWL1_L. The third transistor T3 and the source node of the second transistor T2 The first split word line drive signal output unit 121a including the fourth transistor T4 that is controlled by the voltage of N2 and transmits the LC2_L signal to SWL2_L, and the LC1_R signal that is controlled by the voltage of the source node N1 of the first transistor T1 is transmitted to SWL1_R. 5th The second split word line drive signal output unit 121b including the sixth transistor T6 controlled by the source node N2 voltage of the transistor T5 and the second transistor T2 and transmitting the LC2_R signal to SWL2_R, and between the global word lines GWL and SWL1_L. A first bypass unit 122a including a seventh transistor T7 and an eighth transistor T8 connected between the global word line and SWL2_L; a ninth transistor T9 connected between the global word line and SWL_1R; A second bypass unit 122b including a tenth transistor T10 connected between the global word line and SWL2_R.
Here, the first and second bypass units 122a and 122b are formed of NMOS transistors having a very small driving current in order to bypass the floating voltage of each split word line.
[0039]
Since the driving circuit of the nonvolatile ferroelectric memory device according to the third embodiment configured as described above can be used for both main cell array units (first main cell array unit and second main cell array unit), the layout can be made more efficient. Can be used.
Here, since LC1_L, LC2_L and LC1_R, LC2_R do not become the high level at the same time, the high level signals are not simultaneously applied to SWL1_L, SWL2_L and SWL1_R, SWL2_R.
Such a third embodiment of the present invention is also applicable to a nonvolatile ferroelectric memory device having a plurality of split word line pairs as shown in FIG.
[0040]
The drive circuit for the nonvolatile ferroelectric memory device according to the first, second, and third embodiments of the present invention described above is applied to a nonvolatile ferroelectric memory device having split word lines. .
[0041]
On the other hand, FIG. 17 is a configuration diagram of a NAND type nonvolatile ferroelectric memory cell for explaining a driving circuit of the nonvolatile ferroelectric memory device according to the fourth embodiment of the present invention.
The driving circuit for the nonvolatile ferroelectric memory element according to the first, second and third embodiments is applied to a nonvolatile ferroelectric memory element having a split word line, and the fourth embodiment of the present invention described below. The drive circuit for the nonvolatile ferroelectric memory element according to the embodiment is applied to the nonvolatile ferroelectric memory element having this NAND type cell.
[0042]
FIG. 17 is a configuration diagram of a NAND-type nonvolatile ferroelectric memory cell. As an example, a 4-NAND-type nonvolatile ferroelectric memory cell is illustrated.
As shown in FIG. 17, NMOS transistors (T1, T2,... T5) are connected in series, and a bit line (B / L) is formed along the direction in which the transistors are formed. Of the transistors, the drain of the first transistor T1 and the source of the last transistor T5 are connected to the bit line (B / L). A word line (W / L) is connected to the gate of each transistor, and a WEC signal line is connected to the gate of the last transistor T5.
Here, the WEC signal is a signal that maintains the inactivated state in the read mode and maintains the activated state only in the write mode. Between the word lines (W / L1,... W / L4) connected to the gates of the transistors (T1, T2, T3, T4) and the sources of these transistors, ferroelectric capacitors (FC1,. .FC4) are connected and the last transistor T5 does not have a ferroelectric capacitor.
Such a 4-NAND nonvolatile memory cell is repeatedly configured to implement one memory cell array. Further, in addition to the 4-NAND type illustrated in FIG. 17, a 2-NAND, 3-NAND, and n-NAND type may be used.
[0043]
The driving circuit of the nonvolatile ferroelectric memory device according to the fourth embodiment of the present invention will be described by taking a 4-NAND nonvolatile ferroelectric memory device as an example.
First, in order to describe the driving circuit of the nonvolatile ferroelectric memory device according to the fourth embodiment of the present invention, the configuration of the cell array portion of the 4-NAND nonvolatile ferroelectric memory device will be examined.
[0044]
FIG. 18 is a configuration diagram of a cell array portion of a 4-NAND nonvolatile ferroelectric memory element.
That is, as shown in FIG. 18, the global X decoder unit 81, the first main cell array unit 83 formed on the right side of the global X decoder unit 81, and the first word formed on the right side of the first main cell array unit 83. A line driver 85; a second word line driver 85a formed on the right side of the first word line driver 85; a second main cell array unit 83a formed on the right side of the second word line driver 85a; A first bit line driving unit 87 formed below one main cell array unit 83, and a first local X formed on the right side of the first bit line driving unit 87 and below the first word line driving unit 85; On the right side of the decoder unit 89, the second local X decoder unit 89a formed on the right side of the first local X decoder unit 89, and the second local X decoder unit 89a And a second bit line control unit 87a is formed on the lower side of the second main cell array portion 83a.
[0045]
This configuration is repetitively configured, and the first and second main cell array units 83 and 83a are each composed of a main cell array unit and a reference cell array unit, and each cell array unit is composed of a plurality of unit cells.
The unit cell is the NAND type nonvolatile ferroelectric memory cell already mentioned, and is a 4-NAND type or multi-NAND type nonvolatile ferroelectric memory cell.
Then, the global X decoder unit 81 controls a plurality of global word lines GWL. The first and second local X decoder units 89 and 89a output activation signals LXDEC1 to LXDECn and WEC signals for sequentially activating the word lines of the NAND cells.
The first and second word line driving units 85 and 85a are composed of a plurality of sub driving units, and each sub driving unit is connected to each global word line.
[0046]
FIG. 19 is a partial detail view of FIG. 18, showing the word line driver in more detail.
As shown in FIG. 19, a first word line driving unit 85 and a second word line driving unit 85a are arranged, and a first main cell array unit 83 is arranged on the left side and a second main cell array unit 83a is arranged on the right side. ing. This is to use the layout more efficiently.
As shown in the drawing, the first and second word line drivers 85 and 85a are composed of a plurality of sub-drivers. The global X decoder unit 81 includes a plurality of global word lines GWL1, GWL2,. . . , GWLn are connected. The sub driver SD is connected to each global word line. Each of the first and second word line driving units 85 and 85a includes sub driving units corresponding to the number of global word lines. Each global word line is commonly connected to a sub driving unit of the first word line driving unit 85 and a sub driving unit of the second word line driving unit 85a.
[0047]
FIG. 20 is a detailed view of the “B” portion of FIG. 19 and shows the connection relationship between the signal output from the local X decoder and the sub-driving unit of the fourth embodiment of the present invention.
As shown in FIG. 20, the sub driving unit according to the fourth embodiment of the present invention operates according to the signal of the global word line GWL output from the global X decoder unit, and the signals LXDEC1 to LXDEC4 output from the local X decoder unit. WEC is sequentially applied to the word lines WL1 to WL4. At this time, the WEC signal is a signal that is activated only in the write mode or the storage mode.
[0048]
FIG. 21 shows a driving circuit for a nonvolatile ferroelectric memory device according to a fourth embodiment of the present invention.
The drive circuit shown in FIG. 21 is a detailed configuration diagram of the sub drive unit of FIG.
That is, an X address signal output unit 210 including four NMOS transistors T1, T2, T3, and T4 connected in series to a global word line GWL connected to a global X decoder unit (not shown), and a source voltage of each transistor And a local X decoder unit (a word line drive signal output unit 211 including NMOS transistors T5, T6, T7, and T8 that sequentially apply output signals LXDEC1 to LXDEC4 (not shown) to the word lines WL1 to WL4, and A bypass unit 2 comprising NMOS transistors T9, T10, T11, T12 connected between the source terminals of the NMOS transistors T5, T6, T7, T8 and the global word line GWL and bypassing the floating voltage of each word line. 2 and more composed.
[0049]
Here, the local X decoder unit sequentially outputs WEC signals together with the LXDEC1 to LXDEC4 signals. The first switching transistor TS1 is connected to D of the NMOS transistor T4 of the X address signal output unit 210, and a second switching transistor TS2 that is controlled by the source voltage of the first switching transistor TS1 and switches the WEC signal is further configured. The
[0050]
In the driving circuit of the nonvolatile ferroelectric memory device according to the fourth embodiment of the present invention, the NMOS transistors T1 to T4 of the X address signal output unit 210 are turned on to output the word line driving signal output connected to each source. The NMOS transistors T5 to T8 of the part 211 are turned on.
Accordingly, the output signals LXDEC1 to LXDEC4 of the local X decoder unit are sequentially applied to the word lines WL1 to WL4, and finally the WEC signal is applied.
[0051]
Meanwhile, a bypass unit 212 including NMOS transistors T9 to T12 connected between the global word line GWL and each of the word lines WL1 to WL4 serves to bypass the floating voltage of the word lines WL1 to WL4. That is, when all the global word lines GWL and LXDEC1 to LXDEC4 signals are at a low level, the word lines WL1 to WL4 are in a floating state. At this time, the floating voltages induced on the word lines are applied to the NMOS transistors T9, T10, T11. , T12 to the global word line GWL. The NMOS transistors T9 to T12 have a very small drive current and always maintain a turn-on state.
In this way, the word lines WL1 to WL4 are prevented from being in a floating state so that cell data is not unnecessarily selected. This is because the cell data selected unnecessarily removes in advance elements that act as noise on the actual data.
[0052]
FIG. 21 shows a case where the unit cell is a 4-NAND type. If the unit cell is an n-NAND type, the local X decoder unit outputs LXDEC1 to LXDECn together with the WEC signal. In addition, n NMOS transistors connected in series to the global word line GWL and constituting the X address signal output unit 210 are also composed of n transistors, and NMOS transistors connected to the respective sources of the transistors and constituting the word line drive signal output unit 211 are also included. It consists of n pieces.
[0053]
Hereinafter, the operation of the driving circuit of the nonvolatile ferroelectric memory device according to the fourth embodiment of the present invention will be described.
Since the transistor T1 is turned on, the source of the transistor T1 becomes a high level as the global word line GWL is activated, and the transistor T5 is turned on. Therefore, the LXDEC1 signal output from the local X decoder unit is applied to the word line WL1 via the transistor T5, and the word line WL1 is activated. Therefore, the word line WL1 is activated and the data stored in the ferroelectric capacitor FC1 is transmitted to the bit line via the NMOS transistor T1 of FIG. At the same time, since the transistors T2, T3, and T4 in FIG. 21 are on, similarly, LXDEC2 to LXDEC4 output from the local X decoder unit are activated, and the respective word lines WL2 to WL4 are activated. Then, the data stored in the ferroelectric capacitors FC2, FC3, FC4 is read.
[0054]
Meanwhile, FIG. 22 illustrates the relationship between the driving circuit and the cell array unit according to the fourth embodiment of the present invention in more detail.
As shown in FIG. 22, a global word line GWL is arranged in the horizontal direction, and a plurality of bit lines (..., B / L_n−1, B / L_n) are arranged in a direction crossing the global word line. Needless to say, a large number of global word lines are arranged in parallel, but only one is shown in the figure. A 4-NAND cell is connected to each bit line, and an X address signal output unit 210 including four NMOS transistors T1 to T4 is connected to the global word line GWL.
The source of each NMOS transistor T1 to T4 has a word line drive signal output unit 211 composed of four NMOS transistors T5 to T8 for applying a control signal output from the local X decoder unit to the word lines WL1 to WL4 of the main cell array unit. Connected. Then, four NMOS transistors T9 for bypassing the floating voltages of the word lines WL1 to WL4 between D of the NMOS transistors T5 to T8 constituting the global word line GWL and the word line drive signal output unit 211. A bypass section 212 consisting of T12 is connected.
[0055]
As shown in the figure, the WEC signal that maintains the inactivated state in the read mode and changes to the activated state when the write mode starts is output together with LXDEC1 to LXDEC4 in the local X decoder unit. The first switching transistor TS1 is connected to the source of the fourth NMOS transistor T4 of the X address signal output unit 210, and is controlled by the source voltage of the first switching transistor to apply the WEC signal to the WEC line of the main cell array unit. Two switching transistors TS2 are further connected.
[0056]
Meanwhile, FIG. 23 illustrates a driving circuit for a nonvolatile ferroelectric memory device according to a fifth embodiment of the present invention. The fifth embodiment of the present invention will also be described by taking a 4-NAND cell as an example.
As shown in FIG. 23, according to the fifth embodiment of the present invention, an X address comprising a global word line GWL and four NMOS transistors T1 to T4 connected in parallel to the global word line GWL and sequentially turned on. A gate is connected to the signal output unit 210 and D of each of the NMOS transistors T1 to T4, and four NMOS transistors for transmitting the LXDEC1 to LXDEC4 signals output from the local X decoder unit according to the source voltage to the word lines WL1 to WL4. A word line drive signal output unit 211 including T5, T6, T7, and T8, and four NMOS transistors T9 to T12 that are configured between each word line and the global word line GWL and bypass the floating voltage of the word line. Vipa Part 212, a first switching transistor TS1 connected to the global word line GWL together with four NMOS transistors T1 to T4, and a second switching transistor TS2 that is controlled by the source voltage of the first switching transistor TS2 and switches the WEC signal. Including. The NMOS transistors T1 to T4, T9 to T12, TS1, and TS2 are always kept turned on.
[0057]
In the fifth embodiment of the present invention, it can be seen that the NMOS transistors T1 to T4 are configured in parallel to the global word line GWL as compared to the fourth embodiment described above. By configuring in parallel in this way, the D node N4 of the transistor T4 has a voltage sufficient to turn on the transistor T8. This is because if the source node N2 does not become a sufficiently high level by the transistor T4, the transistor T8 is not sufficiently opened and the LXDEC4 signal is not sufficiently transmitted to the word line WL4.
[0058]
【The invention's effect】
The drive circuit for the nonvolatile ferroelectric memory element of the present invention as described above has the following effects.
The first and second split word lines, the bit line formed in a direction crossing the first and second split word lines, the first split word line and the bit line, and the second split word line and the bit line In the non-volatile ferroelectric memory device comprising a non-volatile ferroelectric memory cell each comprising a switching transistor and a ferroelectric capacitor, the entire row direction address signal is coated in a global X decoder section. The word line of each cell array unit is selected by the local control unit and the local X decoder unit so that the cell array unit in the row direction can be shared, and the control signal and X address signal of the local control unit and local X decoder unit are selected. Since the cell is selected by using, the configuration of the word line driving unit Not only it can be simplified, the effect of reducing the area of the layout.
[0059]
In the present invention, since the drive circuit is composed of only NMOS transistors, the current drive capability can be improved with the same size as the PMOS. Further, by bypassing the floating voltage of the first and second split word lines, the floating voltage prevents the first and second split word lines from being shaken and the unnecessary cells being selected. Generation of noise due to sensing can be prevented in advance.
[0060]
In addition, since a plurality of transistors are connected in series to the word line in parallel, the drive signal is applied to the first and second split word lines without losing the threshold voltage. can do.
[0061]
In order to use the layout efficiently, one split word line driving circuit can share two cell array sections, and split word line driving signals are provided on the left and right sides of the respective output terminals of the plurality of transistors constituting the X address signal output section. Since the output unit is configured to share the X address signal output unit and the drive signal can be selectively applied to the left and right first and second split word lines, the layout area can be further reduced. Can do.
[0062]
Even when the present invention is applied to a case where the unit cell is a multi-NAND cell, it can be expected that the configuration of the word line driving circuit can be simplified and the layout can be used efficiently.
[Brief description of the drawings]
FIG. 1 is a characteristic diagram showing a hysteresis loop of a general ferroelectric substance.
FIG. 2 is a configuration diagram of a stage cell of a conventional nonvolatile ferroelectric memory.
FIG. 3 is a configuration diagram of a driving circuit of a conventional nonvolatile ferroelectric memory element.
FIG. 4 is a timing diagram showing an operation in a write mode of a conventional nonvolatile ferroelectric memory device.
FIG. 5 is a timing diagram showing an operation in a read mode of a conventional nonvolatile ferroelectric memory device.
FIG. 6 is a configuration diagram of a cell array for explaining a driving circuit of the nonvolatile ferroelectric memory device according to the first embodiment of the present invention;
7 is a configuration diagram of a unit cell constituting the main cell array unit of FIG. 6;
8 is a diagram illustrating a unit cell having a 2T / 2C structure illustrated in FIG. 7 separated into unit cells having a 1T / 1C structure. FIG.
FIG. 9 is a configuration diagram for more efficiently using a layout based on the configuration of FIG. 6;
FIG. 10 is a partial detail view of FIG. 9, showing the split word line driver shown in FIG. 6 in more detail.
11 is a diagram illustrating a relationship between signals LC1 and LC2 output from the local control unit of FIG. 9 and a sub-driving unit.
12 is a more detailed view of the portion “A” of FIG. 11, and is a driving circuit of the nonvolatile ferroelectric memory device according to the first embodiment of the present invention.
FIG. 13 is a timing diagram illustrating an operation of the driving circuit for the nonvolatile ferroelectric memory device according to the first embodiment of the present invention illustrated in FIG. 12;
14 is a diagram illustrating a driving circuit for a nonvolatile ferroelectric memory device having a plurality of split word line pairs, using FIG.
FIG. 15 is a driving circuit of a nonvolatile ferroelectric memory device according to a second embodiment of the present invention.
FIG. 16 is a driving circuit of a nonvolatile ferroelectric memory device according to a third embodiment of the present invention.
FIG. 17 is a configuration diagram of a normal 4-NAND cell.
FIG. 18 is a configuration diagram of a cell array portion of a nonvolatile ferroelectric memory element using 4-NAND cells.
FIG. 19 is a partial detail view of FIG. 18 showing the word line driver in more detail.
FIG. 20 is a detailed view of a “B” part of FIG. 19, showing a connection relationship between a signal output from a local X decoder unit and a sub driving unit according to the fourth embodiment of the present invention;
FIG. 21 is a driving circuit of a nonvolatile ferroelectric memory device according to a fourth embodiment of the present invention.
FIG. 22 is a diagram illustrating in detail a relationship between a driving circuit and a cell array according to a fourth embodiment of the present invention.
FIG. 23 is a driving circuit of a nonvolatile ferroelectric memory device according to a fifth embodiment of the present invention.
[Explanation of symbols]
61, 83: first main cell array section
61a, 83a: second main cell array section
63, 81: Global X decoder section
65, 65a: first and second split word line driving units
67, 87: first bit line control unit
67a, 87a: second bit line control unit
69, 69a: first and second local control units
85, 85a: first and second word line control units
89, 89a: first and second local X decoder units
120, 210: X address signal output section
121: Split word line drive signal output unit
211: Word line drive signal output unit
122, 212: Bypass unit

Claims (17)

A first split word line and a second split word line are paired to form a plurality of split word line pairs, and a plurality of bit lines are formed across the split word line pair, The cell array unit includes a unit cell including a switching transistor and a ferroelectric capacitor between the bit line, the cell array unit having a gate terminal connected to the first split word line and a source terminal connected to the first bit line. A first unit cell having a first switching transistor connected to one side of a ferroelectric capacitor FC1 having a drain terminal connected to the second split word line on the other side, and a gate terminal connected to the second split word line . Connected to split word line, source end There is connected to the second bit line, a drain terminal, and a second unit cell having a second switching transistor having the other side is connected to one terminal of the ferroelectric capacitor connected to the first split wordline In a nonvolatile ferroelectric memory device comprising:
An X address signal output unit comprising a plurality of transistors connected in series to a global word line controlled by a global X decoder unit;
A split word line driving signal output unit comprising a plurality of transistors controlled by an output voltage of each transistor and outputting a driving signal for driving the first and second split word line pairs;
Each of the global word line and the first and second split word lines is configured to bypass the floating voltage of the split word line, and the power supply voltage is constantly applied to the gate. A bypass section composed of a plurality of transistors composed of extremely small NMOS transistors ;
A drive circuit for a nonvolatile ferroelectric memory device, comprising: first and second local control units for outputting drive signals for driving the first and second split word lines.   2. The drive circuit for a nonvolatile ferroelectric memory device according to claim 1, wherein the transistor is an NMOS transistor.   2. The driving circuit for a nonvolatile ferroelectric memory device according to claim 1, wherein a driving signal for driving the first and second split word lines is output from a local control unit.   2. The driving circuit for a nonvolatile ferroelectric memory device according to claim 1, wherein the plurality of transistors constituting the X address signal output unit and the bypass unit always maintain a turn-on state.   5. The drive circuit for a nonvolatile ferroelectric memory device according to claim 4, wherein the plurality of transistors constituting the bypass unit are NMOS transistors having a small drive current.   2. The driving circuit for a nonvolatile ferroelectric memory device according to claim 1, wherein the output terminals of the plurality of transistors constituting the split word line driving signal output unit are connected to the split word line.   2. The driving circuit for a nonvolatile ferroelectric memory device according to claim 1, wherein the plurality of transistors constituting the X address signal output unit are configured in parallel to the global word line.   The split word line drive signal output unit for outputting a drive signal for driving the first and second split word line pairs has output terminals of a plurality of transistors constituting the X address signal output unit. 2. The non-volatile ferroelectric device according to claim 1, wherein a drive signal is output to the first and second split word lines on the left side and the first and second split word lines on the right side. Drive circuit for a body memory element.   A split word line drive signal output unit for applying a drive signal to the left first and second split word lines and a split word line drive signal for applying a drive signal to the right first and second split word lines 9. The driving circuit of a nonvolatile ferroelectric memory device according to claim 8, wherein the output unit shares the X address signal output unit. The cell array unit includes a multi-NAND cell composed of a plurality of transistors that are branched and connected to a bit line and connected in series to each other, and each gate is connected to a word line. Are formed along the direction in which the transistors are formed, the drain terminals of the first transistors and the source terminals of the last transistors of the plurality of transistors connected in series are connected to the bit line, and the last transistor Are connected to the WEC signal line without being connected to the word line, and a dielectric capacitor is connected between each of the word lines and the source of the transistor to which each word line is connected. In the connected nonvolatile ferroelectric memory device,
An X address signal output unit comprising a plurality of transistors connected in series to each other and connected to a global word line controlled by a global X decoder unit;
A word line drive signal composed of a plurality of transistors which is controlled by the output voltage of each transistor constituting the X address signal output unit and applies a plurality of word line drive signals output from the local X decoder unit to the respective word lines. An output section;
A non-volatile ferroelectric comprising a bypass unit configured between an output terminal of each transistor constituting the word line drive signal output unit and the global word line and bypassing a floating voltage of the word line A drive circuit for a memory element.   11. The global X decoder unit further outputs a signal WEC that maintains an inactive state in a read mode and maintains an active state only in a write mode together with the plurality of word line driving signals. A drive circuit for the nonvolatile ferroelectric memory element as described.   At the final end of the plurality of transistors constituting the word line drive signal output unit, a signal WEC that maintains the active state only in the write mode is applied to the WEC signal line configured with the plurality of word lines. 11. The driving circuit of a nonvolatile ferroelectric memory device according to claim 10, further comprising a switching transistor for selectively transmitting.   Of the plurality of transistors constituting the X address signal output unit, another switching transistor for removing the switching transistor that transmits a WEC signal to the WEC signal line is further configured at the final end. The drive circuit for a nonvolatile ferroelectric memory element according to claim 10.   11. The drive circuit for a nonvolatile ferroelectric memory device according to claim 10, wherein the transistor is an NMOS transistor.   11. The driving circuit of a nonvolatile ferroelectric memory device according to claim 10, wherein the plurality of transistors constituting the X address signal output unit and the bypass unit always maintain a turn-on state.   16. The drive circuit for a nonvolatile ferroelectric memory device according to claim 15, wherein the plurality of transistors constituting the bypass unit are NMOS transistors having a small drive current.   11. The driving circuit for a nonvolatile ferroelectric memory device according to claim 10, wherein the plurality of transistors constituting the X address signal output unit are configured in parallel to the global word line.

Images