JP3950488B2 - Under-etching correction method and under-etching correction mask - Google Patents

Description

となる。一方、マスク２１内部に進行する面のエッチングレートは、｛１００｝面のエッチングレートに比較して2.３倍程度大きく、つまりアンダーエッチング量ｙはエッチング深さの2.３倍程度となるため、ｙ＝2.３ｔとすると、補正に必要な溝２５の幅ｘ₂ は、

となる。従って、ｘ₂ ＞ｘ₁ となり、溝幅をアンダーエッチング補正のために、本来のエッチング形状を作成するために必要な大きさより大きくしなければならず、このことは例えば溝２５を介して方形台状部２６を有する枠体を作成する上で、その外形を小さくしようとする時の妨げになっていた。
【０００８】
また、方形台状部２６の大きさを小さくする時、エッチングマスク２１の方形パターン２２の幅ａが、（√２）ｙより小さくなると、図８に示したように補正パターン２８同士が重なってしまい、この場合エッチングするとマスク下部に破線で示したような形状の残渣２９ができてしまうため、所望のエッチング形状が得られず、よって方形パターン２２の幅ａは、
ａ≧（√２）ｙ
即ち、ａ≧√２×2.３ｔ
にする必要があった。
【０００９】
この発明の目的はアンダーエッチングの補正を行いながら、方形枠状の溝に囲まれた方形台状部を作成する場合に、従来より溝幅を狭くすることができ、かつ方形台状部の大きさを小さくすることができるアンダーエッチングの補正方法及びそれに使用する補正マスクを提供することにある。
【００１０】
【課題を解決するための手段】
請求項１の発明は、ホトエッチングにより、シリコンウェハの｛１００｝面に各辺がそのシリコンウェハの｛１１０｝面と平行な方形枠状の溝を形成し、その溝で囲まれた方形台状部を作成する方法におけるアンダーエッチングの補正方法であって、シリコンウェハに方形台状部と対応する方形パターンを有し、かつその方形パターンの各頂点にその頂点を中心とし、一辺の長さが上記溝の深さの２倍とされ、各辺がシリコンウェハの｛１００｝面と平行とされた正方形パターンが付加されたエッチングマスクが形成され、そのエッチングマスクによってシリコンウェハが選択エッチングされる。
【００１１】
請求項２の発明は、シリコンウェハの｛１００｝面に各辺がそのシリコンウェハの｛１１０｝面と平行な方形枠状の溝を形成し、その溝で囲まれた方形台状部を作成するホトエッチングに用いる露光用のマスクであって、方形台状部に対応する方形パターンの各頂点に、その頂点を中心とし、一辺の長さが上記溝の深さの２倍とされ、各辺がシリコンウェハの｛１００｝面と平行とされた正方形状のパターンが付加される。
【００１２】
【実施例】
この発明の実施例を図１を参照して説明する。なお、図５と対応する部分には同一符号を付してある。
この例ではアンダーエッチングを補正するために、エッチングマスク２１の方形パターン２２の各頂点に、補正パターンとして図１に示すように正方形パターン３１が付加される。正方形パターン３１は方形パターン２２の頂点を中心とし、各辺がシリコンウェハ２４の｛１００｝面と平行とされており、その一辺の長さＨは以下のように設定される。
【００１３】
正方形パターン３１は｛１００｝面で囲まれた形状をもつので、｛１００｝面と同一のエッチングレートで、この正方形パターン３１内部にアンダーエッチングが進行していく。従って、溝２５のエッチング深さをｔとすると、
Ｈ＝２ｔ
とすることにより、アンダーエッチングが補正された所望の方形台状部２６を作成することができる。
【００１４】
一方、この正方形パターン３１による補正に必要な溝２５の幅ｘ₃ は、

となり、即ち深さｔの溝２５をエッチングするために最低限必要な溝幅ｘ₁ ≒1.４１ｔとほぼ等しい値となる。従って、この例によればアンダーエッチングの補正を行いながら、最小の溝幅を実現できる。
【００１５】
また、方形パターン２２の幅ａの最小値は、この正方形パターン３１同士が重ならなければよいので、

となり、即ち従来の補正パターン２８における幅ａの最小値（√２×2.３ｔ）より小さくすることができ、言い換えれば補正用のパターンがない時のアンダーエッチング量をｙとする時、幅ａを（√２）ｙより小さくすることができる。
【００１６】
エッチングマスクはホトリソグラフィー技術を用いて形成されるものであり、ウェハ上に例えばスピンコーティング等によって一様に塗布したホトレジストに露光用のマスクを通して光を選択的に照射することにより、所要のパターンを有するエッチングマスクが形成される。
従って、上述したようなエッチングマスク２１を形成するためには、その正方形パターン３１が付加された方形パターン２２と同様のパターンを有する露光用マスクが用いられる。
【００１７】
図２はこの発明の好適な用途として、シリコンウェハより形成される加速度センサチップを示したものである。図中、４１は枠体、４２は質量体、４３は質量体４２を枠体４１に支持するヒンジを示す。この発明によれば、このような加速度センサチップを作成する場合に、アンダーエッチングによる質量体４２の体積減少を防止でき、かつ全体として小さくすることができ、よって小型高性能な加速度センサを得ることができる。
【００１８】
【発明の効果】
以上説明したように、この発明によればホトエッチングにより、シリコンウェハの｛１００｝面に各辺がそのシリコンウェハの｛１１０｝面と平行な方形枠状の溝を形成して、その溝で囲まれた方形台状部を作成する場合に、方形台状部のアンダーエッチングを補正することができ、かつ溝幅を所要のエッチング深さを得るために最低限必要な幅とすることができ、つまりアンダーエッチングの補正を行いながら、最小の溝幅を実現することができる。
【００１９】
また、方形台状部の幅を従来の補正パターンを用いる方法に比し、小さくすることができる。
【図面の簡単な説明】
【図１】この発明の実施例を説明するための図。
【図２】Ａはこの発明の実施に好適な加速度センサチップを示す平面図、Ｂはその断面図。
【図３】Ａは長方形の穴（幅小）のマスクによるエッチング形状を示す平面図、Ｂはその断面図。
【図４】Ａは長方形の穴（幅大）のマスクによるエッチング形状を示す平面図、Ｂはその断面図。
【図５】Ａはマスクパターンを示す平面図、Ｂは作成したいエッチング形状を示す平面図、ＣはＢの断面図。
【図６】Ａは方形台状部の頂点部分におけるアンダーエッチングを説明するための図、Ｂは従来の補正パターンを説明するための図。
【図７】補正パターンが方形枠状の穴を塞いだ状態を示す図。
【図８】方形台状部の幅が狭く、補正パターン同士が重なった状態及びその時のエッチング形状を説明するための図。
【符号の説明】
２１ エッチングマスク
２２ 方形パターン
２４ シリコンウェハ
２５ 溝
２６ 方形台状部
３１ 正方形パターン[0001]
[Industrial application fields]
The present invention relates to anisotropic etching of a silicon wafer, and more particularly to a method for correcting under-etching (undercut) when a square trapezoidal shape is formed on a silicon wafer by anisotropic etching.
[0002]
[Prior art]
First, anisotropic etching using the {100} surface of a silicon wafer will be described.
For example, when a rectangular hole is created on the {100} plane as an etching mask so that each side is parallel to the {110} plane, the etched shape using the mask is a hole as shown in FIG. Each surface is formed in a shape surrounded by {111} surfaces. This is because the etching rate of the {111} plane is slower than the etching rate of other crystal planes. At this time, if the width of the mask hole (the width of the etched hole) is x, the etching is automatically stopped when the etching depth (hole depth) t becomes a value represented by the following equation.
[0003]
t = (x / 2) tan 54.74 °
When the etching depth t is smaller than this value, a groove having a cross-sectional shape as shown in FIG. 4 is formed.
On the other hand, as shown in FIG. 5A as an etching mask 21 on the {100} plane, a rectangular frame-shaped hole 23 surrounding the square pattern 22 is created so that each side is parallel to the {110} plane. At this time, it is expected that the shape of the silicon wafer 24 after etching is as shown in FIGS. 5B and 5C, but in actuality, each vertex of the rectangular trapezoidal portion 26 surrounded by the rectangular frame-like groove 25 is used. In the portion, as shown in FIG. 6A, the ridge line 27 advances into the rectangular pattern 22 of the etching mask 21 as the etching progresses, that is, under-etching occurs.
[0004]
As shown in FIG. 6A, this under-etching occurs because a shape in which straight lines are combined appears on the surface having the etching mask 21, so that the etching rate of a specific crystal surface is compared with the etching rate of other crystal surfaces. It is believed that this is due to slowness.
In order to correct this under-etching, that is, to prevent the volume of the rectangular trapezoidal portion 26 from decreasing, conventionally, when forming the rectangular trapezoidal portion 26 surrounded by the rectangular frame-shaped groove 25, the rectangular trapezoidal shape is formed. A correction pattern 28 as shown in FIG. 6B is arranged at each vertex of the rectangular pattern 22 of the etching mask 21 corresponding to the portion 26.
[0005]
The correction pattern 28 has a square shape centered on the apex of the square pattern 22 and each side is parallel to the {110} plane, and ½ of the diagonal length is a predetermined value in the absence of the correction pattern 28. The amount of receding of the apex of the rectangular trapezoidal portion 26 generated when etching is performed to the depth, that is, the amount of under etching y (see FIG. 6B) is made equal.
[0006]
[Problems to be solved by the invention]
When the correction pattern 28 as described above is used, for example, as shown in FIG. 7, when the correction pattern 28 is large enough to close the groove 25 to be created, the rectangular frame-shaped hole 23 of the etching mask 21 is rectangular. Since the etching is performed by the rectangular hole, the etching shape as described in FIG. 3 is obtained, and the etching stops when reaching a certain depth, and as shown in FIGS. 5B and 5C. It becomes impossible to create a square trapezoidal shape. Therefore, the width of the groove 25 needs to be a size that is not blocked by the correction pattern 28.
[0007]
Here, the width of the groove 25 necessary when the rectangular trapezoidal portion 26 surrounded by the rectangular frame-shaped groove 25 as shown in FIGS. 5B and 5C is formed while correcting the under-etching will be considered.
When the required depth (etching depth) of the groove 25 is t, the minimum width x ₁ of the hole 23 of the etching mask 21 required at this time is

It becomes. On the other hand, the etching rate of the surface proceeding inside the mask 21 is about 2.3 times larger than the etching rate of the {100} surface, that is, the under-etching amount y is about 2.3 times the etching depth. , Y = 2.3t, the width x _{2 of the} groove 25 necessary for correction is

It becomes. Therefore, x ₂ > x ₁ , and the groove width must be made larger than the size necessary for creating the original etching shape for under-etching correction. When creating a frame having the shape portion 26, it has been an obstacle when trying to reduce its outer shape.
[0008]
Further, when the square trapezoidal portion 26 is reduced in size, if the width a of the square pattern 22 of the etching mask 21 is smaller than (√2) y, the correction patterns 28 overlap each other as shown in FIG. In this case, if etching is performed, a residue 29 having a shape as shown by a broken line is formed below the mask, so that a desired etching shape cannot be obtained. Therefore, the width a of the rectangular pattern 22 is
a ≧ (√2) y
That is, a ≧ √2 × 2.3t
It was necessary to be.
[0009]
An object of the present invention is to create a rectangular trapezoidal portion surrounded by a rectangular frame-shaped groove while correcting under-etching, so that the groove width can be made narrower than before and the size of the rectangular trapezoidal portion is increased. An object of the present invention is to provide an under-etching correction method capable of reducing the thickness and a correction mask used therefor.
[0010]
[Means for Solving the Problems]
According to the first aspect of the present invention, a rectangular frame-shaped groove in which each side is parallel to the {110} plane of the silicon wafer is formed on the {100} plane of the silicon wafer by photoetching, and the rectangular trapezoid surrounded by the groove. A method for correcting under-etching in a method for creating a shape portion, wherein a silicon wafer has a square pattern corresponding to a square trapezoidal portion, and each vertex of the square pattern is centered on the vertex, and the length of one side Is formed to be twice the depth of the groove, and an etching mask to which each side is parallel to the {100} plane of the silicon wafer is added, and the silicon wafer is selectively etched by the etching mask. .
[0011]
In the invention of claim 2, a rectangular frame-like groove is formed on the {100} plane of the silicon wafer, each side being parallel to the {110} plane of the silicon wafer, and a rectangular trapezoidal portion surrounded by the groove is created. A mask for exposure used for photoetching, wherein each vertex of a rectangular pattern corresponding to the rectangular trapezoidal portion is centered on the vertex, the length of one side being twice the depth of the groove, A square pattern whose side is parallel to the {100} plane of the silicon wafer is added.
[0012]
【Example】
An embodiment of the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the part corresponding to FIG.
In this example, in order to correct under-etching, a square pattern 31 is added as a correction pattern to each vertex of the rectangular pattern 22 of the etching mask 21 as shown in FIG. The square pattern 31 is centered on the apex of the square pattern 22, and each side is parallel to the {100} plane of the silicon wafer 24. The length H of one side is set as follows.
[0013]
Since the square pattern 31 has a shape surrounded by the {100} plane, under-etching proceeds inside the square pattern 31 at the same etching rate as the {100} plane. Therefore, if the etching depth of the groove 25 is t,
H = 2t
By doing so, a desired rectangular trapezoidal portion 26 in which under-etching is corrected can be created.
[0014]
On the other hand, the width x _{3 of the} groove 25 necessary for correction by the square pattern 31 is

That is, the minimum required groove width x ₁ ≈1.41 t for etching the groove 25 having the depth t is substantially equal to the value. Therefore, according to this example, the minimum groove width can be realized while correcting the under-etching.
[0015]
Further, the minimum value of the width a of the square pattern 22 is not required if the square patterns 31 do not overlap each other.

That is, the width a can be made smaller than the minimum value (√2 × 2.3t) of the width a in the conventional correction pattern 28. In other words, when the amount of underetching when there is no correction pattern is y, the width a Can be made smaller than (√2) y.
[0016]
The etching mask is formed by using a photolithography technique, and a desired pattern is formed by selectively irradiating light through a mask for exposure onto a photoresist uniformly applied on a wafer by, for example, spin coating. An etching mask is formed.
Therefore, in order to form the etching mask 21 as described above, an exposure mask having a pattern similar to the square pattern 22 to which the square pattern 31 is added is used.
[0017]
FIG. 2 shows an acceleration sensor chip formed from a silicon wafer as a preferred application of the present invention. In the figure, 41 is a frame body, 42 is a mass body, and 43 is a hinge that supports the mass body 42 on the frame body 41. According to the present invention, when producing such an acceleration sensor chip, it is possible to prevent the volume of the mass body 42 from being reduced due to under-etching, and to reduce the volume as a whole, thereby obtaining a small high-performance acceleration sensor. Can do.
[0018]
【The invention's effect】
As described above, according to the present invention, a rectangular frame-shaped groove whose sides are parallel to the {110} plane of the silicon wafer is formed on the {100} plane of the silicon wafer by photoetching. When creating an enclosed square trapezoidal part, the underetching of the square trapezoidal part can be corrected, and the groove width can be set to the minimum necessary width to obtain the required etching depth. That is, the minimum groove width can be realized while correcting the under-etching.
[0019]
In addition, the width of the rectangular trapezoidal portion can be reduced as compared with the conventional method using the correction pattern.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an embodiment of the present invention.
FIG. 2A is a plan view showing an acceleration sensor chip suitable for carrying out the present invention, and B is a cross-sectional view thereof.
FIG. 3A is a plan view showing an etching shape with a rectangular hole (small width) mask, and B is a cross-sectional view thereof.
4A is a plan view showing an etching shape with a mask of a rectangular hole (wide), and FIG. 4B is a cross-sectional view thereof.
5A is a plan view showing a mask pattern, B is a plan view showing an etching shape to be created, and C is a cross-sectional view of B. FIG.
6A is a diagram for explaining under-etching at the apex portion of a rectangular trapezoidal portion, and FIG. 6B is a diagram for explaining a conventional correction pattern.
FIG. 7 is a diagram showing a state in which a correction pattern blocks a rectangular frame-shaped hole.
FIG. 8 is a diagram for explaining a state in which the width of a rectangular trapezoidal portion is narrow and correction patterns overlap each other and an etching shape at that time.
[Explanation of symbols]
21 Etching mask 22 Square pattern 24 Silicon wafer 25 Groove 26 Square trapezoidal portion 31 Square pattern

Claims (2)

By anisotropic photoetching, a rectangular frame-like groove is formed on the {100} plane of the silicon wafer, each side being parallel to the {110} plane corresponding to each side of the silicon wafer, and the square surrounded by the groove. A method for correcting under-etching in a method of creating a trapezoidal portion,
The silicon wafer has a rectangular pattern corresponding to the rectangular trapezoidal portion, and each vertex of the rectangular pattern is centered on the vertex, and the length of one side is twice the depth of the groove to be etched , An under-etching correction method comprising: forming an etching mask to which a square pattern is added with each side inclined by 45 degrees from each side of the rectangular frame, and selectively etching the silicon wafer with the etching mask. Each side the {100} plane of the silicon wafer corresponding to the respective sides of the silicon wafer (110) to form a plane parallel to the rectangular frame-shaped grooves, to create a square frustum portion surrounded by the groove different An exposure mask used for isotropic photoetching,
Each vertex of the rectangular pattern corresponding to the rectangular trapezoidal portion is centered on the vertex, the length of one side is twice the depth of the groove to be etched , and each side is 45 degrees from each side of the rectangular frame. An under-etching correction mask characterized by an inclined square pattern added.

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