JP3953934B2 - Code conversion circuit and optical transmission circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides an optical duobinary signal or an RZ (Return to Zero) optical duobinary signal that enables high-speed transmission by reducing the driving speed of a necessary electric circuit, and realizes large-capacity optical transmission. The present invention relates to a conversion circuit and an optical transmission circuit.
[0002]
[Prior art]
In optical transmission using an optical fiber, the optical waveform is distorted due to the nonlinear optical effect and wavelength dispersion characteristics of the optical fiber. This distortion becomes a factor that limits the optical transmission distance and the optical transmission speed.
[0003]
In order to suppress this distortion, researches such as narrowband coding technology and distributed equalization technology have been conducted. In contrast to fractional equalization technology that requires the addition of devices for dispersion equalization according to the amount of dispersion, narrowband coding technology that can be realized by changing the transmission line code is attracting attention as an inexpensive and highly flexible transmission technology Has been.
[0004]
An optical duobinary signal (see, for example, Non-Patent Document 1), which is one of the narrowband encoding techniques, can compress the occupied band of an optical signal to about half of the NRZ signal of the same transmission speed, and can receive the NRZ signal. The mechanism is attracting attention because it can be applied as it is. An optical duobinary signal is one of partial response codes, and a duobinary signal known as an electrical ternary code is applied to binary optical transmission. In the duobinary signal, three values of “+1”, “0”, and “−1” are used to send a binary signal of “0” and “1”, and “1” is changed to “+1” or “−1”. It will be expressed as'. The determination of “+1” or “−1” follows the rule “invert the sign of“ 1 ”with an odd number of“ 0 ”in between”, thereby suppressing interference at the identification point of adjacent bits. Both of this and the narrowing of the generated signal are realized.
In the optical duobinary signal, the phase ('0' or 'π') of the optical carrier is used, and these three values are converted into '1' (phase '0'), '0', '-1' (phase) of the optical signal. π ′). However, as shown in FIG. 10, the optical duobinary signal generation circuit includes a 1-bit feedback circuit (duobinary precoder 901) and an analog filter (optical duobinary filter 902) in the electrical stage. It has become an issue of crystallization.
[0005]
In response to this problem, by multiplexing the signal immediately before the optical modulator (for example, see Non-Patent Document 2) or final optical modulation (for example, see Patent Document 1), a low-speed electric circuit is used. A method for generating a high-speed optical signal has been proposed. However, the method of “Non-Patent Document 2” has a limit of 2 multiplexing, and the method of “Patent Document 1” requires the same operating speed as the optical signal for the multiplexing circuit at the final stage. An RZ optical duobinary signal obtained by converting an optical duobinary signal into RZ has also been studied. In high-speed or long-distance WDM (Wavelength Division Multiplexing) transmission systems, the effects of FWM (Four Wave Mixing) can be reduced by using RZ codes. There is an advantage that a certain narrow bandwidth can be obtained simultaneously.
[0006]
In addition, as a method for realizing high-speed optical transmission by a low-speed electric circuit, there is a bit multiplexing technique by OTDM (Optical Time Division Multiplexing). In order to generate an optical duobinary signal by OTDM, first, an optical signal after OTDM is used. It is necessary to generate an optical signal such that the phase change of the optical carrier in the optical signal coincides with the phase change of the optical duobinary signal. It is impossible to apply OTDM directly to the scheme.
[0007]
Further, as a method for generating an optical duobinary signal by OTDM, a method in which optical modulators are connected in series by the number of multiplexing is proposed (for example, see Patent Document 2). However, since this method cannot be applied to the increase in transmission speed by optical pulse compression often used in OTDM, an electric circuit having the same band as the transmission speed is required, and the electric circuit is also a limiting factor for increasing the speed. .
[0008]
Therefore, in the optical duobinary signal generation according to the prior art, the speed of the multiplexed electric circuit, or about twice that is the upper limit of the transmission speed.
[0009]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 11-122205 “Binary Signal Multiplexer with Code Conversion Function and Binary Signal Separation Device with Code Conversion Function”
[Patent Document 2]
Japanese Patent Laid-Open No. 2001-326609 “Optical RZ Signal Generation Device, Optical RZ Signal Generation Method, Optical Time Division Multiplexing Device, and Optical Time Division Multiplexing Method”
[Non-Patent Document 1]
K. Yonenaga and S. Kuwano, "Dispersion-tolerant optical transmission system using duobinary transmitter and binary receiver," J. Lightwave Technol., LT-15, pp. 1530-1537, 1997.
[Non-Patent Document 2]
Matsuura Yasuhiko, Kataoka Tomoyoshi, Miyamoto Hiroshi, "Proposal of optical duobinary transmission circuit using MZ modulator multiplexing", IEICE General Conference 2002, B-10-90, 2002.
[0010]
[Problems to be solved by the invention]
As a method for realizing high-speed optical transmission by a low-speed electric circuit, there is the above-described bit multiplexing technique using OTDM. However, since it is impossible to directly apply OTDM to the conventional method, an optical signal applicable to OTDM can be used. The realization of a duobinary signal multiplexing system has been a problem.
[0011]
The present invention has been made to solve such a problem. The present invention reduces the driving speed of an electric circuit required for generating an optical duobinary signal and enables high-speed transmission. An object is to provide a transmission circuit.
[0013]
[Means for Solving the Problems]
The present invention has been made to solve the above problems, and a code conversion circuit according to the present invention receives n parallel two logical data signals having the same signal speed as an input, and has a signal speed equal to the signal speed. A code conversion circuit that outputs three parallel logic data signals, the first electric signal (two logic data) obtained by time division multiplexing the n parallel input signals every one time slot and the n parallel signals In order to determine the output logic of the second electrical signal (3 logic data) in the second electrical signal (3 logic data) obtained by time-division multiplexing of the output signal for each time slot, Means for outputting the first logic (0) as the second electric signal (three logic data) when the first logic (0) is inputted as the one electric signal (two logic data); 1 electrical signal (2 logic signals) When the second logic (+1) is input as the second electrical signal (3 logic data), the second electrical signal (3 logic data) corresponding to the first electrical signal (2 logic data) is input. At the time point 1 that is the logic output time point of the logic data), the second logic (+1) or the third logic value determined by the logic output pattern of the second electric signal (3 logic data) before the time point 1 is determined. When the output logic is determined by the output logic determination means of logic (+2) and the output logic determination means, there is no output logic of the second electric signal (3 logic data) one time slot before the time point 1, That is, when the time point 1 is the start time of the output of the second electric signal (three logic data), the output logic is set by the means for outputting the second logic (+1) at the time point 1 and the output logic determining means. When determining, time 1 Means for outputting the second logic (+1) at the time point 1 when the output logic of the second electrical signal (three logic data) one time slot before is the second logic (+1); When the output logic is determined by the output logic determining means, if the output logic of the second electrical signal (3 logic data) one time slot before the time 1 is the third logic (+2), 1, when the output logic is determined by the means for outputting the third logic (+2) and the output logic determination means, the output of the second electric signal (three logic data) one time slot before the time point 1 When the logic is the first logic (0), the output logic of the second electric signal (three logic data) is examined retroactively from the time point 1, and the output logic of the second electric signal is the second for the first time. Logic (+1) or third logic (+2) At time point 2, the time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic based on the counting result of the time slot counting means. When the consecutive time slots of (0) are an even number, a means for outputting the same logic as the output logic at the time point 2 at the time point 1 and a count result of the time slot counting means, the first logic (0) If the consecutive time slots are odd and the output logic at time 2 is the second logic (+1), the third logic (+2) is output at time 1 and the first logic (0) continues. Means for outputting a second logic (+1) at time 1 if the time slot is odd and the output logic at time 2 is the third logic (+2),The parallel number n of the code conversion circuit is 2, and a three logic data signal is expressed by two binary signals, in which the first logic (0) and the second logic of the two binary signals are expressed. (+1) represents the first logic (0) of the three logic data signal, and the third logic (+2) of the two binary signals represents the second logic (+1) of the three logic data signal, The second logic (+3) of the two binary signals represents the third logic (+2) of the three logic data signal, and the code conversion circuit has a first delay that gives a delay of one time slot. A first delay circuit that inputs a circuit, a second delay circuit that gives a delay of one time slot, a first two logic data input signal, and an output of the first delay circuit, and outputs an exclusive OR of both of them. Exclusive OR circuit, a second two-logic data input signal, and the first A second exclusive OR circuit that receives the output of the exclusive OR circuit as an input and outputs the exclusive OR of both to the first delay circuit and the second delay circuit; In the above, one three logic data signal is expressed by a pair of a binary signal output from the first exclusive OR circuit and a binary signal output from the second exclusive OR circuit, One binary logic data signal is expressed by a pair of a binary signal output from the first exclusive OR circuit and a binary signal output from the second delay circuit.
As a result, an optical transmission circuit in which the optical signal after optical time division multiplexing becomes an RZ optical duobinary signal or an optical duobinary signal can be configured, and the operation speed of the electric circuit used in the optical transmission circuit is It can be 1 / n of the optical signal speed.
Also,As a result, the code conversion circuit can have a simple circuit configuration, and the electrical circuit can be easily increased in speed. Also, commercially available parts can be used. Furthermore, an n-multiplex code conversion circuit can be easily configured by arranging a plurality of 2-multiplex code conversion circuits.
[0014]
  Further, the code conversion circuit of the present invention includes:An n-parallel 2-logic data signal having an equal signal speed as an input, and a code conversion circuit for outputting an n-parallel 3-logic data signal having a signal speed equal to the signal speed, the n-parallel input signal being A first electric signal (two logic data) obtained by time division multiplexing for each time slot and a second electric signal (three logic signals) obtained by time division multiplexing the n parallel output signals for each time slot. When the first logic (0) is input as the first electric signal (two logic data) to determine the output logic of the second electric signal (three logic data) in the data) When means for outputting the first logic (0) as the second electric signal (three logic data) and the second logic (+1) as the first electric signal (two logic data) are input, Second electrical signal (3 logic data ) At the time point 1 which is the logic output time point of the second electric signal (three logic data) corresponding to the first electric signal (two logic data), the second electric signal (3 before the time point 1) When determining the output logic of the second logic (+1) or the third logic (+2) for determining by the logic output pattern of the logic data) and the output logic by the output logic determining means, If there is no output logic of the second electrical signal (3 logic data) one time slot before the time 1, that is, if the time 1 is the start time of the output of the second electrical signal (3 logic data) When the output logic is determined by the means for outputting the second logic (+1) at 1 and the output logic determination means, the output logic of the second electric signal (3 logic data) one time slot before time 1 Is the second logic If the output logic is determined by the means for outputting the second logic (+1) at the time point 1 and the output logic determining means, the second time one time slot before the time point 1 When the output logic of the electrical signal (3 logic data) is the third logic (+2), the output logic is determined by means for outputting the third logic (+2) at the time point 1 and the output logic determining means. When the output logic of the second electrical signal (3 logic data) one time slot before the time point 1 is the first logic (0), the second time is moved back from the time point 1 From the time point 1 to the time point 2 at the time point 2 when the output logic of the electric signal (three logic data) is checked and the output logic of the second electric signal becomes the second logic (+1) or the third logic (+2) for the first time. The first logic (0) between If the number of consecutive time slots of the first logic (0) is an even number based on the counting result of the time slot counting means and the time slot counting means, the same logic as the output logic at time 2 is 1 and the counting result of the time slot counting means, the continuous time slot of the first logic (0) is an odd number, and the output logic at the time point 2 is the second logic (+1). For example, if the third logic (+2) is output at time point 1 and the continuous time slot of the first logic (0) is odd and the output logic at time point 2 is the third logic (+2), 1 and a means for outputting a second logic (+1).The parallel number n of the code conversion circuit is 2, and a three logic data signal is expressed by two binary signals, in which the first logic (0) and the second logic of the two binary signals are expressed. (+1) represents the first logic (0) of the three logic data signal, and the third logic (+2) of the two binary signals represents the second logic (+1) of the three logic data signal. The fourth logic (+3) of the two binary signals represents the third logic (+2) of the three logic data signal, and the sign conversion circuit receives the first two logic data input signal and inverts it. A first logic inverting circuit that outputs logic; a second logic inverting circuit that receives the second two logic data input signals and outputs inverted logic; a delay circuit that provides a delay of one time slot; The output of the logic inversion circuit 1 and the output of the delay circuit are input, A first exclusive OR circuit that outputs another logical sum, an output from the second logical inversion circuit, and an output from the first exclusive OR circuit are input, and an exclusive logical sum of the two is obtained. A first exclusive OR circuit to be output to the delay circuit, a first two logic data input signal, and an output of the first exclusive OR circuit are input, and a first logical product of both is output. AND circuit, a third logic inversion circuit that outputs the inverted logic by using the output of the first exclusive OR circuit, the first two logic data input signal, and the third logic An inverting circuit is input, and a second logical product circuit that outputs a logical product of the two, the second two logical data input signal, and the output of the second exclusive OR circuit are input, A third AND circuit that outputs a logical product, and the second exclusive OR circuit; A fourth logic inverting circuit that receives the input and outputs the inverted logic; and a fourth logic inverting circuit that receives the second two-logic data input signal and the fourth logic inverting circuit and outputs a logical product of both. Further, in the code conversion circuit, one pair of binary signals output from the first AND circuit and a binary signal output from the second AND circuit is provided. A logical data signal is represented, and a single three logical data signal is represented by a pair of a binary signal output from the third logical product circuit and a binary signal output from the fourth logical product circuit. And
As a result, an optical transmission circuit in which the optical signal after optical time division multiplexing becomes an RZ optical duobinary signal or an optical duobinary signal can be configured, and the operation speed of the electric circuit used in the optical transmission circuit is It can be 1 / n of the optical signal speed.
  Also,As a result, the code conversion circuit can have a simple circuit configuration, and the electrical circuit can be easily increased in speed. Also, commercially available parts can be used. Furthermore, an n-multiplex code conversion circuit can be easily configured by arranging a plurality of 2-multiplex code conversion circuits.
[0015]
  The optical transmission circuit according to the present invention multiplexes n parallel optical pulse data signals having the same transmission rate by optical time division multiplexing, and has an RZ light having a transmission rate n times that of each optical pulse data signal before multiplexing. An optical transmission circuit that generates a duobinary signal, the optical transmission circuit includes:A code conversion circuit which receives an n-parallel 2-logic data signal having an equal signal speed as an input and outputs an n-parallel 3-logic data signal having a signal speed equal to the signal speed;A pulse light source that outputs an optical pulse train; an optical branch circuit that receives the optical pulse train as an input; an optical branch circuit that outputs an input light by n-branching; and each of the n-branched optical outputs as an input The kth optical modulation circuit includes: an optical modulation circuit that modulates input light according to a predetermined optical modulation rule by the kth three logic data signal of the code conversion circuit; WithThe code conversion circuit time-divisions the first electric signal (two logical data) obtained by time-division multiplexing the n-parallel input signals for each time slot and the n-parallel output signal for each time slot. In order to determine the output logic of the second electric signal (three logic data) in the second electric signal (three logic data) obtained by multiplexing, the first electric signal (two logic data) is used as the first electric signal (two logic data). When a logic (0) of 1 is input, a means for outputting a first logic (0) as a second electrical signal (3 logic data) and a first as a first electrical signal (2 logic data) When the logic (+1) of 2 is input, the second electrical signal (3 logic data) is converted into the second electrical signal (3 logic data) corresponding to the first electrical signal (2 logic data). At time point 1, which is a logic output time point, Output logic determining means of the second logic (+1) or third logic (+2) for determining by the logic output pattern of the second electric signal (3 logic data), and output by the output logic determining means When determining the logic, there is no output logic of the second electrical signal (3 logic data) one time slot before the time point 1, that is, the start of the output of the second electrical signal (3 logic data) at the time point 1 If it is time, when the output logic is determined by means for outputting the second logic (+1) at time 1 and the output logic determination means, the second electric signal one time slot before time 1 When the output logic of (3 logic data) is the second logic (+1), the output logic is determined by means for outputting the second logic (+1) at time 1 and the output logic determination means And said Means for outputting the third logic (+2) at the time point 1 when the output logic of the second electric signal (three logic data) one time slot before the point 1 is the third logic (+2); When the output logic is determined by the output logic determining means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the first logic (0) The output logic of the second electrical signal (3 logic data) is examined retroactively from the time point 1, and the output logic of the second electrical signal is the first logic (+1) or the third logic (+2) for the first time. At time point 2, the time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic based on the counting result of the time slot counting means. (0) consecutive time slots In the case where the first logic (0) is an odd number, the time logic of the first logic (0) is an odd number based on the counting result of the time slot counting means. If the output logic at the time 2 is the second logic (+1), the third logic (+2) is output at the time 1 and the continuous time slot of the first logic (0) is an odd number. Means for outputting the second logic (+1) at the time point 1 when the output logic at the time point 2 is the third logic (+2).The light modulation rules are such that the light intensity is minimized for the first logic (0), the light intensity is maximized for the second logic (+1) and the third logic (+2), and the second The optical phases with respect to the logic (+1) and the third logic (+2) have a phase difference of π, and the outputs of the n light modulation circuits are input to combine the input lights. Output optical coupling timesThe roadIt is characterized by providing.
  This makes it possible to configure an n-multiplexed RZ optical duobinary signal transmission circuit in which the optical signal after optical time division multiplexing becomes an RZ optical duobinary signal, and the operation speed of the electric circuit used in the transmission circuit can It can be 1 / n of the signal speed.
[0016]
Furthermore, the optical transmission circuit of the present invention is an optical bandpass filter that receives the output of the optical coupling circuit, and the passband has a transmission rate that is n times that of each optical pulse data signal before multiplexing. An optical duobinary signal is generated by providing an optical bandpass filter equal to the band occupied by the fundamental wave component of the optical duobinary signal having the above.
As a result, the n-multiplexed RZ optical duobinary signal can be converted to NRZ, and an n-multiplexed optical duobinary signal with a more occupied band can be generated.
[0017]
  The optical transmission circuit of the present invention multiplexes two parallel optical pulse data signals having the same transmission rate by optical time division multiplexing, and has an RZ light having a transmission rate twice that of each optical pulse data signal before multiplexing. An optical transmission circuit that generates a duobinary signal, the optical transmission circuit includes:A code conversion circuit which receives an n-parallel 2-logic data signal having an equal signal speed as an input and outputs an n-parallel 3-logic data signal having a signal speed equal to the signal speed;A pulse light source that outputs an optical pulse train; an optical branch circuit that receives the optical pulse train as input; a first optical branch circuit that outputs the input light by bifurcating it; and each of the two branched optical outputs. Two optical modulation circuits each of which is an input, and the kth optical modulation circuit modulates input light according to a predetermined optical modulation rule by the kth three logic data signal of the code conversion circuit. A modulation circuit,The code conversion circuit time-divisions the first electric signal (two logical data) obtained by time-division multiplexing the n-parallel input signals for each time slot and the n-parallel output signal for each time slot. In order to determine the output logic of the second electric signal (three logic data) in the second electric signal (three logic data) obtained by multiplexing, the first electric signal (two logic data) is used as the first electric signal (two logic data). When a logic (0) of 1 is input, a means for outputting a first logic (0) as a second electrical signal (3 logic data) and a first as a first electrical signal (2 logic data) When the logic (+1) of 2 is input, the second electrical signal (3 logic data) is converted into the second electrical signal (3 logic data) corresponding to the first electrical signal (2 logic data). At time point 1, which is a logic output time point, Output logic determining means of the second logic (+1) or third logic (+2) for determining by the logic output pattern of the second electric signal (3 logic data), and output by the output logic determining means When determining the logic, there is no output logic of the second electrical signal (3 logic data) one time slot before the time point 1, that is, the start of the output of the second electrical signal (3 logic data) at the time point 1 If it is time, when the output logic is determined by means for outputting the second logic (+1) at time 1 and the output logic determination means, the second electric signal one time slot before time 1 When the output logic of (3 logic data) is the second logic (+1), the output logic is determined by means for outputting the second logic (+1) at time 1 and the output logic determination means And said Means for outputting the third logic (+2) at the time point 1 when the output logic of the second electric signal (three logic data) one time slot before the point 1 is the third logic (+2); When the output logic is determined by the output logic determining means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the first logic (0) The output logic of the second electrical signal (3 logic data) is examined retroactively from the time point 1, and the output logic of the second electrical signal is the first logic (+1) or the third logic (+2) for the first time. At time point 2, the time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic based on the counting result of the time slot counting means. (0) consecutive time slots In the case where the first logic (0) is an odd number, the time logic of the first logic (0) is an odd number based on the counting result of the time slot counting means. If the output logic at the time 2 is the second logic (+1), the third logic (+2) is output at the time 1 and the continuous time slot of the first logic (0) is an odd number. Means for outputting the second logic (+1) at the time point 1 when the output logic at the time point 2 is the third logic (+2), the optical transmission circuit comprising:The light modulation rule is such that the light intensity is minimized for the first logic (0), the light intensity is maximized for the second logic (+1) and the third logic (+2), and the second The optical phases for the logic (+1) and the third logic (+2) of FIG. 5 have a phase difference of π from each other. Further, each optical modulation signal is input to each, and a delay is given according to the delay control signal to output. Two delay adjustment circuits to be performed; an output of each of the two delay adjustment circuits as an input; an optical coupling circuit that combines and outputs the input light; and an output of the optical coupling circuit as an input; A second optical branching circuit for branching a part to an optical spectrum observation circuit; and the optical spectrum observation circuit, wherein the two delay adjustment circuits are arranged such that the input optical spectrum becomes the spectrum of an RZ optical duobinary signal. Optical spectrum observation to adjust delay amount In addition, in order to adjust the delay amount, in the initial state, the delay amount is adjusted so that the optical spectrum becomes the spectrum of the RZ optical duobinary signal, thereby generating the RZ optical duobinary signal. In the normal state, when the power at the maximum value of the optical spectrum, the intensity of the frequency component at the maximum value, and the optical transmission rate are R [bit / s], the carrier frequency is (2 / 3) Observe the intensity of the frequency component on the high frequency side and the low frequency side by xR, and set the delay amount so that the intensity of both frequency components is not more than a predetermined value with respect to the frequency component intensity at the maximum value And means for adjusting.
  As a result, a two-multiplex RZ optical duobinary signal transmission circuit in which the optical signal after optical time division multiplexing becomes an RZ optical duobinary signal can be configured, and the operation speed of the electric circuit used in the transmission circuit can be The optical signal speed can be ½.
[0018]
  The optical transmission circuit of the present invention multiplexes two parallel optical pulse data signals having the same transmission rate by optical time division multiplexing, and has an optical duo having a transmission rate twice that of each optical pulse data signal before multiplexing. An optical transmission circuit for generating a binary signal, wherein the optical transmission circuit includes:A code conversion circuit which receives an n-parallel 2-logic data signal having an equal signal speed as an input and outputs an n-parallel 3-logic data signal having a signal speed equal to the signal speed;A pulse light source that outputs an optical pulse train; an optical branch circuit that receives the optical pulse train as input; a first optical branch circuit that outputs the input light by bifurcating it; and each of the two branched optical outputs. Two optical modulation circuits each of which is an input, and the kth optical modulation circuit modulates input light according to a predetermined optical modulation rule by the kth three logic data signal of the code conversion circuit. A modulation circuit,The code conversion circuit time-divisions the first electric signal (two logical data) obtained by time-division multiplexing the n-parallel input signals for each time slot and the n-parallel output signal for each time slot. In order to determine the output logic of the second electric signal (three logic data) in the second electric signal (three logic data) obtained by multiplexing, the first electric signal (two logic data) is used as the first electric signal (two logic data). When a logic (0) of 1 is input, a means for outputting a first logic (0) as a second electrical signal (3 logic data) and a first as a first electrical signal (2 logic data) When the logic (+1) of 2 is input, the second electrical signal (3 logic data) is converted into the second electrical signal (3 logic data) corresponding to the first electrical signal (2 logic data). At time point 1, which is a logic output time point, Output logic determining means of the second logic (+1) or third logic (+2) for determining by the logic output pattern of the second electric signal (3 logic data), and output by the output logic determining means When determining the logic, there is no output logic of the second electrical signal (3 logic data) one time slot before the time point 1, that is, the start of the output of the second electrical signal (3 logic data) at the time point 1 If it is time, when the output logic is determined by means for outputting the second logic (+1) at time 1 and the output logic determination means, the second electric signal one time slot before time 1 When the output logic of (3 logic data) is the second logic (+1), the output logic is determined by means for outputting the second logic (+1) at time 1 and the output logic determination means And said Means for outputting the third logic (+2) at the time point 1 when the output logic of the second electric signal (three logic data) one time slot before the point 1 is the third logic (+2); When the output logic is determined by the output logic determining means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the first logic (0) The output logic of the second electrical signal (3 logic data) is examined retroactively from the time point 1, and the output logic of the second electrical signal is the first logic (+1) or the third logic (+2) for the first time. At time point 2, the time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic based on the counting result of the time slot counting means. (0) consecutive time slots In the case where the first logic (0) is an odd number, the time logic of the first logic (0) is an odd number based on the counting result of the time slot counting means. If the output logic at the time 2 is the second logic (+1), the third logic (+2) is output at the time 1 and the continuous time slot of the first logic (0) is an odd number. Means for outputting the second logic (+1) at the time point 1 when the output logic at the time point 2 is the third logic (+2), the optical transmission circuit comprising:The light modulation rule is such that the light intensity is minimized for the first logic (0), the light intensity is maximized for the second logic (+1) and the third logic (+2), and the second The optical phases for the logic (+1) and the third logic (+2) of FIG. 5 have a phase difference of π from each other. Further, each optical modulation signal is input to each, and a delay is given according to the delay control signal to output. Two delay adjustment circuits to be performed, an optical coupling circuit that inputs the outputs of the two delay adjustment circuits as inputs, and combines and outputs the input light; and an optical bandpass that receives the outputs of the optical coupling circuits as inputs An optical bandpass filter having a passband equal to a band occupied by a fundamental component of an optical duobinary signal having a transmission rate twice that of each optical pulse data signal before multiplexing; The output of the pass filter is the input and the input light A second optical branch circuit for branching a part to an optical spectrum observation circuit; and the optical spectrum observation circuit, wherein the delay of the two delay adjustment circuits is such that the input optical spectrum becomes the spectrum of an optical duobinary signal. An optical spectrum observation circuit that adjusts the amount of light, and further, in order to adjust the delay amount, in the initial state, the delay amount is adjusted so that the optical spectrum becomes the spectrum of the optical duobinary signal. Means for confirming the generation of the binary signal, and the carrier frequency when the power at the maximum value of the optical spectrum, the intensity of the frequency component at the maximum value, and the optical transmission rate are set to R [bit / s] Further, the intensity of the frequency component on the high frequency side and the low frequency side is observed by (1/2) × R, and the intensity of both frequency components is the frequency at the maximum value. To min strength, characterized in that it comprises a means for adjusting the delay amount to be equal to or less than a predetermined value.
  As a result, the two-multiplexed RZ optical duobinary signal is converted to NRZ, and a two-multiplexed optical duobinary signal with a more occupied band can be generated.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram for explaining an n-multiplex code conversion circuit according to the present invention. In the code conversion circuit 101 shown in FIG. 1A, the first two logical data 1 (for example, “0”, “0”, “ The 2nd logical data n from the first to the nth is input in parallel, and the nth data from the first three logical data 1 (for example, the values “0”, “+1”, “+2”) are input. Three logical data n is output, and n parallel data is transmitted in a time-division multiplexed manner one bit at a time in the order of 1 to n (see FIG. 1B). Note that the ternary logic data signal in FIG. 1A does not necessarily have to be transmitted through a single conductor. That is, as shown in the example of FIG. 2 or FIG. 3 described below, a configuration in which a three logic data signal is transmitted using two conductors that transmit a binary logic signal can be employed.
[0020]
In addition, in the n multiple code conversion circuit 101 shown in FIG. 1A, code conversion is performed as follows when converting a 2-logic data signal into 3-logic data.
[0021]
(1) When the first logic (for example, “0”) is input as the two logic data, the first logic (for example, “0”) is output as the three logic data.
(2) When the second logic (for example, “+1”) is input as the two logic data, the three logic data corresponding to the second logic (for example, “+1”) of the two logic data At time t1, which is the logic output time, the second logic (for example, “+1”) or the third logic (for example, “+2”) is selectively output according to the logic output pattern of the three logic data before time t1.
If there is no output logic of the 3 logic data one time slot before the time t1, and the time t1 is the start time of the output of the slot signal of 3 logic data, the second logic (for example, “+1”) is set. Output.
When the output logic of the three logic data one time slot before time t1 is the second logic (for example, “+1”), the second logic (for example, “+1”) is output.
When the output logic of the three logic data one time slot before time t1 is the third logic (for example, “+2”), the third logic (for example, “+2”) is output.
If the output logic of the three logical data one time slot before the time point t1 is the first logic (for example, “0”), the output logic of the slot signal of the three logical data goes back from the time point t1. The first logic between time t1 and time t2 at time t2 when the output logic becomes the second logic (eg, “+1”) or the third logic (eg, “+2”) for the first time. The number of time slots (for example, “0”) is counted.
When the consecutive time slots of the first logic (for example, “0”) are an even number, the same logic as the output logic at the time t2 is output at the time t1.
If the consecutive time slots of the first logic (eg “0”) are odd and the output logic at time t2 is the second logic (eg “+1”), the third logic at time t1 Output logic (for example, “+2”).
If the consecutive time slots of the first logic (for example, “0”) are odd and the output logic at the time t2 is the third logic (for example, “+2”), the second logic at the time t1 Output logic (eg, “+1”).
[0022]
FIG. 9 shows an example of generating a “three logical data slot signal”.
In FIG. 9, since the input signal of 2 logic data is “1” and the 3 logic data before 1 time slot is “0” at time t1, “3 logic” is traced back from time t1. Check the output logic of the “data slot signal” and count the number of time slots in which “0” continues from time t1 to time t2 at time t2 when the output logic is “+1” or “+2” for the first time. To do. In this case, since continuous time slots are even (two), the same logic “+1” as the output logic at time t2 is output at time t1.
At time t3, since the input signal of 2 logic data is “1” and the 3 logic data before 1 time slot is “0”, the “3 logic data slot signal goes back from time t3. , And at the time t4 when the output logic becomes “+1” or “+2” for the first time, the number of time slots in which “0” between time t3 and time t4 continues is counted. In this case, since the number of consecutive time slots is odd (three) and the output logic at time t4 is “+1”, “+2” is output at time t3.
[0023]
[Second Embodiment]
FIG. 2 is a diagram illustrating a first configuration example of the two-multiplex code conversion circuit.
2A, reference numerals 201 and 202 denote exclusive OR (EXOR) circuits, reference numerals 203 and 204 denote delay circuits, and the code conversion circuit shown in FIG. 2A is configured as follows. The
The delay circuit 203 and the delay circuit 204 are delay circuits that give a delay of one time slot.
The exclusive OR circuit 201 receives the two logic data input signal a (data 1) and the output c of the delay circuit 203 as inputs, and outputs an exclusive OR of both.
The exclusive OR circuit 202 receives the 2-logical data input signal b (data 2) and the output d of the exclusive OR circuit 201 and outputs the exclusive OR of both to the delay circuit 203 and the delay circuit 204. To do.
[0024]
In the example shown in FIG. 2, the parallel number n is 2, and the three logical data signals can be expressed by the following two binary signals.
The first logic (eg, “0”) of the two binary signals and the second logic (eg, “+1”) represent the first logic (eg, “0”) of the three logic data signal. . The second logic (eg, “+1”) of the three logic data signal is represented by the third logic (eg, “+2”) of the two binary signals.
The fourth logic (eg “+3”) of the two binary signals represents the third logic (eg “+2”) of the three logic data signal.
[0025]
The output signals at the points a to h in the multiple code conversion circuit are represented by logical expressions in the table of FIG. In FIG. 2B, the symbol “+” indicates exclusive OR (EXOR), and the symbol “r” indicates the initial value of the delay circuit. Each signal indicated by r, a1, a2, b1, b2 is data having a value of “0” or “1”.
[0026]
As shown in FIG. 2B, when the input bits at a certain time t1 are a1 and b1, the input bits at the next time t2 are a2 and b2, and between data1_1 and data1_2 and between data2_1 and data2_2 If the exclusive OR operation is performed, it is understood that a1 and a2 and b1 and b2 are obtained and the value of the input data is output as it is. Further, it is possible to expand to n multiple code conversion circuits with n = 2 or more by increasing the parallel number. As the exclusive OR circuits (EXOR) 201 and 202 in the figure, those that can operate up to several tens of GHz are commercially available, and they may be used. For the delay circuits 203 and 204, there is a method of adjusting the delay amount according to the cable length.
[0027]
[Third Embodiment]
FIG. 3 is a diagram illustrating a second configuration example of the two-multiplex code conversion circuit.
[0028]
The two-multiplex code conversion circuit shown in FIG. 3A is configured as follows.
The logic inversion circuit 301 receives the two logic data input signal a (data 1) and outputs an inversion logic signal c. The logic inversion circuit 302 receives the two logic data input signal b (data 2) and outputs an inversion logic signal d.
The delay circuit 303 is a delay circuit that gives a delay of one time slot.
The exclusive OR circuit 304 receives the output c of the logic inverting circuit 301 and the output e of the delay circuit 303 as inputs, and outputs an exclusive OR of both.
The exclusive OR circuit 305 receives the output d of the logic inversion circuit 302 and the output f of the exclusive OR circuit 304 and outputs the exclusive OR of both to the delay circuit 303.
The logical product circuit 306 receives the two logical data input signal a and the output f of the exclusive logical sum circuit 304, and outputs a logical product of the two.
The AND circuit 307 is an AND circuit that receives the inverted output h of the exclusive OR circuit 304 by the logic inversion circuit 308 and the two logic data input signal a and outputs a logical product of the two.
The logical product circuit 309 receives the two logical data input signal b and the output g of the exclusive logical sum circuit 305 as inputs, and outputs the logical product of the same party.
The logical product circuit 310 receives the two logical data input signal b and the inverted output i of the exclusive logical sum circuit 305 by the logical inverting circuit 311 and outputs a logical product of the two.
[0029]
In the example shown in FIG. 3, the parallel number n is 2, and the three logical data signals are expressed by two binary signals as follows.
The first logic (eg, “0”) of the two binary signals and the second logic (eg, “+1”) represent the first logic (eg, “0”) of the three logic data signal. . The second logic (eg, “+1”) of the three logic data signal is represented by the third logic (eg, “+2”) of the two binary signals.
The fourth logic (eg “+3”) of the two binary signals represents the third logic (eg “+2”) of the three logic data signal.
[0030]
Further, the output signals at the points a to 0 of the multiplex code conversion circuit are shown by logical expressions in the table of FIG. In FIG. 3B, the sign “+” indicates an exclusive OR (EXOR), the sign “•” indicates a logical product (AND), the sign “^” indicates an inverted logic (NOT), and the sign “r”. "Indicates the initial value of the delay circuit. Each signal indicated by r, a1, a2, b1, b2 is data having a value of “0” or “1”.
[0031]
If the output of the delay adjustment circuit is “r” at a certain moment, “a1” is input as “data 1” and “b1” is input as “data 2”.
The value observed at point a is “a1”.
The value observed at point c is “^ a1”.
The value observed at the point f is “r + ^ a1” because it is an exclusive OR of the value of the point e and the value of the point c.
Thereafter, the logical operation continues in the same manner, and the values of the final output points “n, o” are a1 and b1. In this way, a two-multiplex code conversion circuit is realized.
[0032]
In addition, it is possible to expand to an n-multiplex code conversion circuit with n = 2 or more by increasing the parallel number of the 2-multiplex code conversion circuit shown in FIG.
[0033]
[Fourth Embodiment]
FIG. 4 shows a configuration example of a two-multiplex RZ optical duobinary signal transmission circuit. Two parallel optical pulse data signals having the same transmission rate are multiplexed by optical time division multiplexing, and each optical signal before multiplexing is multiplexed. It is an example of the optical transmission circuit for producing | generating the RZ optical duobinary signal which has a transmission rate twice as high as a pulse data signal. In FIG. 4, 401 is a code conversion circuit, 402 and 403 are optical modulation circuits, 404 and 405 are delay adjustment circuits, 406 is a pulse light source, 407 is an optical branch circuit, 408 is an optical coupling circuit, 409 is an optical branch circuit, 410 Indicates an optical spectrum observation circuit.
[0034]
The code conversion circuit 401 is a code conversion circuit using an n-multiplex code conversion circuit (see FIG. 1) according to the present invention or a two-multiplex code conversion circuit (see FIG. 2 or FIG. 3). It is a pulse light source that outputs an optical pulse train. The optical branching circuit 407 receives the optical pulse train from the pulse light source 406, splits the input light into two, and outputs it.
[0035]
Each of the two branched optical outputs is sent to two optical modulation circuits 402 and 403. For example, the first optical modulation circuit 403 receives the first three logical data signals (data 1_1 and data 1_2), the input light is modulated according to the following “light modulation rule”.
• For the first logic (eg, “0”) of the three logic data, minimize the light intensity.
Maximize the light intensity for the second logic (eg, “+1”) and the third logic (eg, “+2”) of the three logic data.
The optical phase of the third logic data with respect to the second logic (eg, “+1”) and the third logic (eg, “+2”) is modulated so as to have a phase difference of π from each other.
[0036]
The output light (light data 2) of the light modulation circuit 402 is input to the delay adjustment circuit 404, and the output light (light data 1) of the light modulation circuit 403 is input to the delay adjustment circuit 405. The delay adjustment circuits 404 and 405 adjust the delay amount by the “delay control signal” output from the optical spectrum observation circuit 410, and the delay amount is adjusted as follows.
In the initial state, the delay amount is manually adjusted so that the optical spectrum becomes the spectrum of the RZ optical duobinary signal, and the generation of the RZ optical duobinary signal is confirmed.
・ Normally, when the power at the maximum value of the optical spectrum, the intensity of the frequency component at the maximum value, and the optical transmission rate are R [bit / s], they are (2/3) × R higher than the carrier frequency. The intensities of the frequency components on the frequency band side and the low frequency side are observed, and the delay amount is adjusted so that the intensities of both frequency components are not more than a predetermined value with respect to the intensity of the frequency component at the maximum value. The optical spectrum observation circuit 410 adjusts the delay amounts of the two delay adjustment circuits 404 and 405 so that the input optical spectrum becomes the spectrum of the RZ optical duobinary signal.
[0037]
The outputs of the two delay adjustment circuits 404 and 405 are combined by an optical coupling circuit 408 and further output to a predetermined route via an optical branching circuit 409.
[0038]
As the optical modulation circuits 402 and 403 shown in FIG. 4, a Mach-Zehnder optical modulator driven by both-side electrodes can be used (refer to Non-Patent Document 2 for details). The Mach-Zehnder type optical modulator driven by both electrodes, for example, takes the operating point at the point where the light transmittance is minimized and sets the driving voltage to “V × (π / 2)”, so that the potential difference between the two electrodes can be obtained. It is possible to generate light without changing the optical carrier phase and chirp.
[0039]
Further, as the pulse light source 406, a DFB laser may be used, or a laser output of CW (continuous) output may be modulated in a pulse shape by an optical modulator such as an EA modulator. Optical branch circuits 407 and 409 As the optical coupling circuit 408, a waveguide type 3db coupler may be used.
[0040]
As described above, in this example, timing adjustment at the phase level of the optical carrier is necessary during OTBM. However, as described above, the delay adjustment circuits 404 and 405 are provided to adjust the delay amount from the outside. In addition to the configuration in which the optical path is configured, the optical system of the optical branching-optical modulation-optical coupling may be realized as a waveguide designed so that the optical paths have the same length. As the delay adjustment circuits 404 and 405, an optical delay device that changes the propagation distance of light using a reflection boundary can be used.
[0041]
For generation of the “delay control signal” by the optical spectrum observation circuit 410, a high-resolution optical spectrum analyzer capable of GP-IB (General Purpose Interfase Bus) control can be used.
[0042]
[Fifth Embodiment]
FIG. 5 shows a configuration example of a two-multiplexed optical duobinary signal transmission circuit. In FIG. 5, 501 is a code conversion circuit, 502 and 503 are optical modulation circuits, 504 and 505 are delay adjustment circuits, 506 is a pulse light source, 507 is an optical branching circuit, 508 is an optical coupling circuit, and 509 is an optical BPF (band pass). Filter), 510 indicates an optical branch circuit, and 511 indicates an optical spectrum observation circuit. The “two-multiplex optical duobinary signal transmission circuit” illustrated in FIG. 5 has basically the same configuration as the circuit illustrated in FIG. 4 except that an optical BPF 509 is added.
[0043]
That is, by passing the RZ optical duobinary signal generated by the circuit shown in FIG. 4 through an optical filter (optical BPF) 509 having an optical duobinary signal band, the RZ optical duobinary signal is converted to NRZ, and the occupied band is further increased. A sandwiched optical duobinary signal can be generated. As the optical BPF (band pass filter), an AWG (Arrayed Waveguide Grating) or a waveguide type can be used.
[0044]
In FIG. 5, a code conversion circuit 501 is an n-multiplex code conversion circuit (see FIG. 1) or a 2-multiplex code conversion circuit (see FIG. 2 or 3) according to the present invention, and a pulse light source 506 converts an optical pulse train. It is a pulse light source to output. The optical branch circuit 507 receives the optical pulse train from the pulse light source 506, splits the input light into two, and outputs it.
[0045]
Each of the two branched optical outputs is sent to two optical modulation circuits 502 and 503. For example, the first optical modulation circuit 502 converts the input light into the first three logical data of the code conversion circuit 501. Depending on (data 1_1 and data 1_2) on the signal, modulation is performed according to the following “light modulation rule”.
• For the first logic (eg, “0”) of the three logic data, minimize the light intensity.
Maximize the light intensity for the second logic (eg, “+1”) and the third logic (eg, “+2”) of the three logic data.
The optical phase of the third logic data with respect to the second logic (eg, “+1”) and the third logic (eg, “+2”) is modulated so as to have a phase difference of π from each other.
[0046]
The output light (light data 2) of the light modulation circuit 502 is input to the delay adjustment circuit 504, and the output light (light data 1) of the light modulation circuit 503 is input to the delay adjustment circuit 505. The delay adjustment circuits 504 and 505 adjust the delay amount by the “delay control signal” output from the optical spectrum observation circuit 511.
[0047]
The delay amount is adjusted as follows.
In the initial state, the delay amount is manually adjusted so that the optical spectrum becomes the spectrum of the optical duobinary signal, and the generation of the optical duobinary signal is confirmed.
-Normally, when the power at the maximum value of the optical spectrum, the intensity of the frequency component at the maximum value, and the optical transmission rate are R [bit / s], the carrier frequency is higher by (1/2) × R. The intensities of the frequency components on the frequency band side and the low frequency side are observed, and the delay amount is adjusted so that the intensities of both frequency components are not more than a predetermined value with respect to the intensity of the frequency component at the maximum value. The optical spectrum observation circuit 511 adjusts the delay amounts of the two delay adjustment circuits 404 and 405 so that the input optical spectrum becomes the spectrum of the optical duobinary signal.
[0048]
Then, the outputs of the two delay adjustment circuits 504 and 505 are combined by an optical coupling circuit 508, and the combined light is converted into an optical duobinary signal band (the optical pulse data of each optical pulse data before the multiplexing is performed). RZ optical duobinary signal is converted to NRZ by passing it through an optical filter (optical BPF) 509 having an optical duobinary signal having a transmission speed n times that of the signal and having the same bandwidth as that of the fundamental wave component. An optical duobinary signal with a band can be generated.
[0049]
As the optical modulation circuits 502 and 503 shown in FIG. 5, a Mach-Zehnder optical modulator driven by both-side electrodes can be used (refer to Non-Patent Document 2 for details). The Mach-Zehnder type optical modulator driven by both electrodes, for example, takes the operating point at the point where the light transmittance is minimized and sets the driving voltage to “V × (π / 2)”, so that the potential difference between the two electrodes can be obtained. It is possible to generate light without changing the optical carrier phase and chirp.
[0050]
Further, as the pulse light source 506, a DFB laser may be used, or a laser output of CW (continuous) output may be modulated in a pulse shape by an optical modulator such as an EA modulator. As the optical coupling circuit 508, a waveguide type 3db coupler may be used.
[0051]
As described above, in this example, timing adjustment at the phase level of the optical carrier is necessary during OTBM. However, as described above, the delay adjustment circuits 504 and 505 are provided to adjust the amount of delay from the outside. In addition to the configuration in which the optical path is configured, the optical system of the optical branching-optical modulation-optical coupling may be realized as a waveguide designed so that the optical paths have the same length. As the delay adjustment circuits 504 and 505, an optical delay device that changes the propagation distance of light using a reflection boundary can be used.
[0052]
For generation of the “delay control signal” by the optical spectrum observation circuit 510, a high-resolution optical spectrum analyzer capable of GP-IB (General Purpose Interfase Bus) control can be used.
[0053]
[Sixth Embodiment]
FIG. 6 is an example in which the “two multiplexed RZ optical duobinary signal transmission circuit” shown in FIG. 4 is configured as an “n multiplexed RZ optical duobinary signal transmission circuit”, and n parallel optical pulses having the same transmission rate. An optical transmission circuit for multiplexing data signals by optical time division multiplexing and generating an RZ optical duobinary signal having a transmission rate n times that of each optical pulse data signal before multiplexing.
[0054]
In FIG. 6, 601 is an n-multiplex code conversion circuit, 602 is an optical modulation circuit corresponding to the nth data (data n), 603 is an optical modulation circuit corresponding to the second data (data 2), and 604 is the first. , 605 is a pulse light source, 606 is an optical branching circuit, 607 is an optical coupling circuit, and 608 is an optical branching circuit.
[0055]
The code conversion circuit 601 is an n-multiplex code conversion circuit (see FIG. 1) according to the present invention, and the pulse light source 605 is a pulse light source that outputs an optical pulse train. The optical branch circuit 606 receives the optical pulse train from the pulse light source 605, branches the input light n times, and outputs it.
[0056]
Each of the n-branched optical outputs is sent to n optical modulation circuits 602 to 604. For example, the first optical modulation circuit 604 converts the input light into the first three logical data of the code conversion circuit 601. The signal (data 1_1 and data 1_2) is modulated according to the following “light modulation rule”.
• For the first logic (eg, “0”) of the three logic data, minimize the light intensity.
Maximize the light intensity for the second logic (eg, “+1”) and the third logic (eg, “+2”) of the three logic data.
The optical phase of the third logic data with respect to the second logic (eg, “+1”) and the third logic (eg, “+2”) is modulated so as to have a phase difference of π from each other.
[0057]
Then, the outputs of the n optical modulation circuits 602 to 604 are combined by the optical coupling circuit 607 and output toward a predetermined route via the optical branching circuit 608.
[0058]
[Seventh Embodiment]
FIG. 7 shows an example in which the “two multiplexed optical duobinary signal transmission circuit” shown in FIG. 5 is configured as an “n multiplexed optical duobinary signal transmission circuit”.
[0059]
In FIG. 7, 701 is a code conversion circuit, 702 is an optical modulation circuit corresponding to the nth data (data n), 703 is an optical modulation circuit corresponding to the second data (data 2), and 704 is the first data. An optical modulation circuit corresponding to (data 1), 705 a pulse light source, 706 an optical branch circuit, 707 an optical coupling circuit, 708 an optical BPF (bandpass filter), and 709 an optical branch circuit.
[0060]
The transmission circuit illustrated in FIG. 7 has the same basic configuration as the “n-multiplexed RZ optical duobinary signal transmission circuit” illustrated in FIG. 6 except that an optical BPF 708 is added.
[0061]
That is, the RZ optical duobinary signal generated by the optical transmission circuit shown in FIG. 6 is converted into an optical optical BPF 708 (an optical duobinary signal whose pass band has a transmission speed n times that of each optical pulse data signal before multiplexing). RZ optical duobinary signal can be converted to NRZ by passing the signal having the same band as that occupied by the fundamental wave component, and an optical duobinary signal with a more occupied band can be generated. As the optical BPF (band pass filter), an AWG (Arrayed Waveguide Grating) or a waveguide type can be used.
[0062]
[Eighth Embodiment]
As another configuration example of the n-multiplex code conversion circuit diagram, FIG. 8 shows a configuration example of an n-multiplex code conversion circuit using 2 × 2 switches.
[0063]
Although the embodiments of the present invention have been described above, the code conversion circuit and the optical transmission circuit of the present invention are not limited to the above illustrated examples, and various modifications can be made without departing from the scope of the present invention. Of course, can be added.
[0064]
【The invention's effect】
As described above, in the n-multiplex code conversion circuit of the present invention, when code conversion is performed on 2 logic data to 3 logic data, “0” of 3 logic data is input to “0” of 2 logic data. Is output. Also, for the input of “+1” of 2 logic data, if the 3 logic data one time slot before the time t1 when the 3 logic data is output is “+1” or “+2”, the same logic is used. Output. If the three logical data one time slot before the time t1 is “0”, the time goes back from the time t1 until the time t2 when the output logic of the three logical data is “+1” or “+2” for the first time. The number of consecutive “0” s in between is checked, and if it is even, the same logic as the output at time t2 is output at time t1, and the number of consecutive “0” s is odd and output at time t2. If the logic is “+1”, “+2” is output, and if the logic is “+2”, “+1” is output.
Accordingly, an optical transmission circuit in which an optical signal after optical time division multiplexing becomes an n-multiplexed RZ optical duobinary signal or an n-multiplexed optical duobinary signal can be configured, and an electric circuit used in the optical transmission circuit can be configured. The operating speed can be 1 / n of the optical signal speed.
[0065]
In the two-multiplex code conversion circuit of the present invention, a two-multiplex code conversion circuit is configured by two delay circuits and two exclusive OR circuits.
As a result, the code conversion circuit can have a simple circuit configuration, and the electrical circuit can be easily increased in speed. Also, commercially available parts can be used. Furthermore, an n-multiplex code conversion circuit can be easily configured by arranging a plurality of 2-multiplex code conversion circuits.
[0066]
In the two-multiplex code conversion circuit of the present invention, a two-multiplex code conversion circuit is configured by one delay circuit, two exclusive OR circuits, four logic inversion circuits, and four AND circuits. .
As a result, the code conversion circuit can have a simple circuit configuration, and the electrical circuit can be easily increased in speed. Also, commercially available parts can be used. Furthermore, an n-multiplex code conversion circuit can be easily configured by arranging a plurality of 2-multiplex code conversion circuits.
[0067]
Further, in the optical transmission circuit of the present invention, the n-multiplex code conversion circuit according to the present invention is used, the optical pulse train of the pulse light source is n-branched by the optical branch circuit, and each of the branched optical outputs is divided into n light beams. Modulate by a modulation circuit. As the modulation rule, the light intensity is minimized for “0” of the three logical data, the light intensity is maximized for “+1” and “+2”, and the optical phase for “+1” and “+2” is A phase difference of π is given to each other. Then, the outputs of the n optical modulation circuits are combined by an optical coupling circuit, and an n-multiplexed RZ optical duobinary signal is output.
This makes it possible to configure an n-multiplexed RZ optical duobinary signal transmission circuit in which the optical signal after optical time division multiplexing becomes an RZ optical duobinary signal, and the operation speed of the electric circuit used in the transmission circuit can It can be 1 / n of the signal speed.
[0068]
Also, in the optical transmission circuit of the present invention, the RZ optical duobinary signal output from the n-multiplexed RZ optical duobinary signal transmission circuit according to the present invention is filtered by an optical BPF (optical bandpass filter), and n-multiplexed light Obtain a duobinary signal.
As a result, the n-multiplexed RZ optical duobinary signal can be converted to NRZ, and an n-multiplexed optical duobinary signal with a more occupied band can be generated.
[0069]
Further, in the optical transmission circuit of the present invention, the two-multiplex code conversion circuit according to the present invention is used, the optical pulse train of the pulse light source is bifurcated by the optical branch circuit, and each of the branched optical outputs is divided into two optical signals. Modulate by a modulation circuit. As the modulation rule, the light intensity is minimized for “0” of the three logical data, the light intensity is maximized for “+1” and “+2”, and the optical phase for “+1” and “+2” is A phase difference of π is given to each other. Further, the output from the light modulation circuit is input to the delay adjustment circuit to adjust the delay amount. The outputs of the two delay adjustment circuits are combined by an optical coupling circuit, and a two-multiplexed RZ optical duobinary signal is output.
As a result, a two-multiplex RZ optical duobinary signal transmission circuit in which the optical signal after optical time division multiplexing becomes an RZ optical duobinary signal can be configured, and the operation speed of the electric circuit used in the transmission circuit can The signal speed can be ½.
[0070]
Further, in the optical transmission circuit of the present invention, the two-multiplex code conversion circuit according to the present invention is used, the optical pulse train of the pulse light source is bifurcated by the optical branch circuit, and each of the branched optical outputs is divided into two optical signals. Modulate by a modulation circuit. As the modulation rule, the light intensity is minimized for “0” of the three logical data, the light intensity is maximized for “+1” and “+2”, and the optical phase for “+1” and “+2” is A phase difference of π is given to each other. Further, the output from the light modulation circuit is input to the delay adjustment circuit to adjust the delay amount. The light obtained by combining the outputs of the two delay adjustment circuits by the optical coupling circuit is filtered by an optical BPF (optical bandpass filter) to obtain a two-multiplexed optical duobinary signal.
As a result, the two-multiplexed RZ optical duobinary signal is converted to NRZ, and a two-multiplexed optical duobinary signal with a more occupied band can be generated.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an n-multiplex code conversion circuit according to the present invention.
FIG. 2 is a diagram illustrating a first configuration example of a two-multiplex code conversion circuit.
FIG. 3 is a diagram illustrating a second configuration example of the two-multiplex code conversion circuit;
FIG. 4 is a diagram illustrating a configuration example of a two-multiplex RZ optical duobinary signal transmission circuit.
FIG. 5 is a diagram illustrating a configuration example of a two-multiplexed optical duobinary signal transmission circuit.
FIG. 6 is a diagram illustrating a configuration example of an n-multiplex RZ optical duobinary signal transmission circuit.
FIG. 7 is a diagram illustrating a configuration example of an n-multiplex optical duobinary signal transmission circuit.
FIG. 8 is a diagram illustrating a configuration example of an n-multiplex code conversion circuit using a 2 × 2 switch.
FIG. 9 is a diagram illustrating an example of generating a slot signal of three logical data.
FIG. 10 is a diagram illustrating a conventional optical duobinary signal generation circuit.
[Explanation of symbols]
101 Code conversion circuit
201, 202 exclusive OR circuit
203, 204 delay circuit
301, 302, 308, 311 logic inversion circuit
303 Delay circuit
304, 305 exclusive OR circuit
306, 307, 309, 310 AND circuit
401 Code conversion circuit
402, 403 Light modulation circuit
404, 405 delay adjustment circuit
406 Pulsed light source
407, 409 optical branch circuit
408 Optical coupling circuit
410 Optical spectrum observation circuit
501 Code conversion circuit
502, 503 Light modulation circuit
504, 505 Delay adjustment circuit
506 Pulsed light source
507, 510 Optical branch circuit
508 Optical coupling circuit
509 Hikari BPF
511 Optical spectrum observation circuit
601 Code conversion circuit
602, 603, 604 Optical modulation circuit
605 Pulsed light source
606, 608 optical branch circuit
607 optical coupling circuit
701 Code conversion circuit
702, 703, 704 Optical modulation circuit
705 Pulsed light source
706, 709 Optical branch circuit
707 Optical coupling circuit
708 Hikari BPF

Claims (6)

A code conversion circuit having an n-parallel two-logic data signal having an equal signal speed as an input and an n-parallel three-logic data signal having a signal speed equal to the signal speed as an output,
A first electric signal (two logical data) obtained by time division multiplexing the n parallel input signals for each time slot and a first electric signal obtained by time division multiplexing the n parallel output signals for each time slot. In order to determine the output logic of the second electrical signal (3 logic data) in 2 electrical signals (3 logic data),
Means for outputting the first logic (0) as the second electric signal (three logic data) when the first logic (0) is inputted as the first electric signal (two logic data);
When the second logic (+1) is input as the first electrical signal (2 logic data), the second electrical signal (3 logic data) is changed to the first electrical signal (2 logic data). At a time point 1 that is a logic output time point of the corresponding second electric signal (3 logic data), a second output is determined by the logic output pattern of the second electric signal (3 logic data) before the time point 1. Output logic determining means of logic (+1) or third logic (+2) of
When the output logic is determined by the output logic determining means, there is no output logic of the second electric signal (three logic data) one time slot before the time point 1, that is, the time point 1 is the second electric signal (3 (Logic data) is output at the start time, means for outputting the second logic (+1) at time 1;
When the output logic is determined by the output logic determining means, if the output logic of the second electrical signal (3 logic data) one time slot before time 1 is the second logic (+1), Means for outputting a second logic (+1) at 1;
When the output logic is determined by the output logic determination means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the third logic (+2), Means for outputting a third logic (+2) at time point 1;
When the output logic is determined by the output logic determining means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the first logic (0), The output logic of the second electrical signal (3 logic data) is examined retroactively from time 1 and the output logic of the second electrical signal becomes the second logic (+1) or the third logic (+2) for the first time. At time point 2, time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic ( 0) if the consecutive time slots are even, means for outputting the same logic as the output logic at time 2 at time 1;
According to the counting result of the time slot counting means, if the continuous time slot of the first logic (0) is an odd number and the output logic at the time 2 is the second logic (+1), the third logic at the time 1 If logic (+2) is output and the consecutive time slots of the first logic (0) are odd and the output logic at time 2 is the third logic (+2), the second logic (at time 1) +1) and a means for outputting
With
The parallel number n of the code conversion circuit is 2,
The three logic data signals are represented by two binary signals, in which the first logic (0) and the second logic (+1) of the two binary signals are used to express the first of the three logic data signals. The second logic (+1) of the three logic data signals is represented by the third logic (+2) of the two binary signals, and the fourth of the two binary signals is represented by the fourth logic (0) of the two binary signals. The logic (+3) represents the third logic (+2) of the three logic data signal, and
In the code conversion circuit,
A first delay circuit providing a delay of one time slot;
A second delay circuit providing a delay of one time slot;
A first exclusive OR circuit that receives the first two logic data input signal and the output of the first delay circuit as inputs, and outputs an exclusive OR of both;
A second exclusive output that receives the second two-logic data input signal and the output of the first exclusive OR circuit and outputs the exclusive OR of the two to the first delay circuit and the second delay circuit. And a logical OR circuit,
Furthermore, in the code conversion circuit,
One binary logic data signal is expressed by a pair of a binary signal output from the first exclusive OR circuit and a binary signal output from the second exclusive OR circuit;
A code conversion circuit characterized in that one three-logic data signal is expressed by a pair of a binary signal output from the first exclusive OR circuit and a binary signal output from a second delay circuit. . A code conversion circuit having an n-parallel two-logic data signal having an equal signal speed as an input and an n-parallel three-logic data signal having a signal speed equal to the signal speed as an output,
A first electric signal (two logical data) obtained by time division multiplexing the n parallel input signals for each time slot and a first electric signal obtained by time division multiplexing the n parallel output signals for each time slot. In order to determine the output logic of the second electrical signal (3 logic data) in 2 electrical signals (3 logic data),
Means for outputting the first logic (0) as the second electric signal (three logic data) when the first logic (0) is inputted as the first electric signal (two logic data);
When the second logic (+1) is input as the first electrical signal (2 logic data), the second electrical signal (3 logic data) is changed to the first electrical signal (2 logic data). At a time point 1 that is a logic output time point of the corresponding second electric signal (3 logic data), a second output is determined by the logic output pattern of the second electric signal (3 logic data) before the time point 1. Output logic determining means of logic (+1) or third logic (+2) of
When the output logic is determined by the output logic determining means, there is no output logic of the second electric signal (three logic data) one time slot before the time point 1, that is, the time point 1 is the second electric signal (3 (Logic data) is output at the start time, means for outputting the second logic (+1) at time 1;
When the output logic is determined by the output logic determining means, if the output logic of the second electrical signal (3 logic data) one time slot before time 1 is the second logic (+1), Means for outputting a second logic (+1) at 1;
When the output logic is determined by the output logic determination means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the third logic (+2), Means for outputting a third logic (+2) at time point 1;
When the output logic is determined by the output logic determining means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the first logic (0), The output logic of the second electrical signal (3 logic data) is examined retroactively from time 1 and the output logic of the second electrical signal becomes the second logic (+1) or the third logic (+2) for the first time. At time point 2, time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic ( 0) if the consecutive time slots are even, means for outputting the same logic as the output logic at time 2 at time 1;
According to the counting result of the time slot counting means, if the continuous time slot of the first logic (0) is an odd number and the output logic at the time 2 is the second logic (+1), the third logic at the time 1 If logic (+2) is output and the consecutive time slots of the first logic (0) are odd and the output logic at time 2 is the third logic (+2), the second logic (at time 1) +1) and a means for outputting
With
The parallel number n of the code conversion circuit is 2,
The three logic data signals are represented by two binary signals, in which the first logic (0) and the second logic (+1) of the two binary signals are used to express the first of the three logic data signals. The second logic (+1) of the three logic data signals is represented by the third logic (+2) of the two binary signals, and the fourth logic (2 of the two binary signals ( +3) represents the third logic (+2) of the three logic data signal,
In the code conversion circuit,
A first logic inversion circuit which receives the first two logic data input signals and outputs inverted logic;
A second logic inversion circuit which receives the second two logic data input signal and outputs inverted logic;
A delay circuit providing a delay of one time slot;
A first exclusive OR circuit that receives the output of the first logic inversion circuit and the output of the delay circuit as inputs, and outputs an exclusive OR of both;
A second exclusive OR circuit that receives the output of the second logic inversion circuit and the output of the first exclusive OR circuit and outputs the exclusive OR of both to the delay circuit;
A first logical product circuit that receives the first two logical data input signal and the output of the first exclusive OR circuit and outputs a logical product of the two,
A third logic inverting circuit that receives the output of the first exclusive OR circuit and outputs inverted logic;
A second AND circuit that inputs the first two logic data input signals and the third logic inversion circuit and outputs a logical product of the two;
A third AND circuit that inputs the second two-logic data input signal and the output of the second exclusive OR circuit and outputs the logical product of the same;
A fourth logic inverting circuit that receives the output of the second exclusive OR circuit and outputs inverted logic;
A fourth logical product circuit that inputs the second two logical data input signal and the fourth logical inverting circuit and outputs a logical product of the two logical data input signals;
Furthermore, in the code conversion circuit,
A single 3-logic data signal is expressed by a pair of a binary signal output from the first AND circuit and a binary signal output from the second AND circuit,
A code conversion circuit characterized in that one 3-logical data signal is represented by a pair of a binary signal output from a third AND circuit and a binary signal output from a fourth AND circuit. An optical transmission circuit that multiplexes n parallel optical pulse data signals having the same transmission speed by optical time division multiplexing and generates an RZ optical duobinary signal having a transmission speed n times that of each optical pulse data signal before multiplexing. There,
In the optical transmission circuit,
A code conversion circuit which receives an n-parallel 2-logic data signal having an equal signal speed as an input and outputs an n-parallel 3-logic data signal having a signal speed equal to the signal speed;
A pulse light source that outputs an optical pulse train;
An optical branching circuit having the optical pulse train as an input, the optical branching circuit outputting n-branch and outputting the input light; and
An n number of optical modulation circuits each having each of the n-branched optical outputs as inputs, wherein the kth optical modulation circuit uses the input light as the kth three logic data signal of the code conversion circuit. And a light modulation circuit that modulates according to a predetermined light modulation rule.
The code conversion circuit includes:
A first electric signal (two logical data) obtained by time division multiplexing the n parallel input signals for each time slot and a first electric signal obtained by time division multiplexing the n parallel output signals for each time slot. In order to determine the output logic of the second electrical signal (3 logic data) in 2 electrical signals (3 logic data),
Means for outputting the first logic (0) as the second electric signal (three logic data) when the first logic (0) is inputted as the first electric signal (two logic data) ;
When the second logic (+1) is input as the first electrical signal (2 logic data), the second electrical signal (3 logic data) is changed to the first electrical signal (2 logic data). At a time point 1 that is a logic output time point of the corresponding second electric signal (3 logic data), a second output is determined by the logic output pattern of the second electric signal (3 logic data) before the time point 1. Output logic determining means of logic (+1) or third logic (+2) of
When the output logic is determined by the output logic determining means, there is no output logic of the second electric signal (three logic data) one time slot before the time point 1, that is, the time point 1 is the second electric signal (3 (Logic data) is output at the start time, means for outputting the second logic (+1) at time 1;
When the output logic is determined by the output logic determining means, if the output logic of the second electrical signal (3 logic data) one time slot before time 1 is the second logic (+1), Means for outputting a second logic (+1) at 1;
When the output logic is determined by the output logic determination means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the third logic (+2), Means for outputting a third logic (+2) at time point 1;
When the output logic is determined by the output logic determining means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the first logic (0), The output logic of the second electrical signal (3 logic data) is examined retroactively from time 1 and the output logic of the second electrical signal becomes the second logic (+1) or the third logic (+2) for the first time. At time point 2, time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic ( 0) if the consecutive time slots are even, means for outputting the same logic as the output logic at time 2 at time 1;
According to the counting result of the time slot counting means, if the continuous time slot of the first logic (0) is an odd number and the output logic at the time 2 is the second logic (+1), the third logic at the time 1 If logic (+2) is output and the consecutive time slots of the first logic (0) are odd and the output logic at time 2 is the third logic (+2), the second logic (at time 1) +1) and a means for outputting
With
The optical transmission circuit includes:
The previous Symbol light modulation rule,
For the first logic (0), minimize the light intensity,
For the second logic (+1) and the third logic (+2), the light intensity is maximized, and the optical phases for the second logic (+1) and the third logic (+2) have a phase difference of π from each other Shall have
Furthermore, the a n inputs each output of the optical modulator, the optical coupling circuits for coupling to output the input light
Optical transmitter circuit comprising: a. The optical transmission circuit according to claim 3 , further comprising an optical bandpass filter having an output of the optical coupling circuit as an input, wherein the passband is n times transmission of each optical pulse data signal before multiplexing. An optical transmission circuit comprising an optical bandpass filter equal to a band occupied by a fundamental wave component of an optical duobinary signal having speed, and generating an optical duobinary signal. An optical transmission circuit that multiplexes two parallel optical pulse data signals having the same transmission rate by optical time division multiplexing and generates an RZ optical duobinary signal having a transmission rate twice that of each optical pulse data signal before multiplexing. There,
In the optical transmission circuit,
A code conversion circuit which receives an n-parallel 2-logic data signal having an equal signal speed as an input and outputs an n-parallel 3-logic data signal having a signal speed equal to the signal speed;
A pulse light source that outputs an optical pulse train;
A first optical branching circuit that receives the optical pulse train as an input and splits the input light into two to output;
Two optical modulation circuits each having each of the two branched optical outputs as inputs, wherein the kth optical modulation circuit uses the input light as the kth three logic data signal of the code conversion circuit. And a light modulation circuit that modulates according to a predetermined light modulation rule.
The code conversion circuit includes:
A first electric signal (two logical data) obtained by time division multiplexing the n parallel input signals for each time slot and a first electric signal obtained by time division multiplexing the n parallel output signals for each time slot. In order to determine the output logic of the second electrical signal (3 logic data) in 2 electrical signals (3 logic data),
Means for outputting the first logic (0) as the second electric signal (three logic data) when the first logic (0) is inputted as the first electric signal (two logic data);
When the second logic (+1) is input as the first electrical signal (2 logic data), the second electrical signal (3 logic data) is changed to the first electrical signal (2 logic data). At a time point 1 that is a logic output time point of the corresponding second electric signal (3 logic data), a second output is determined by the logic output pattern of the second electric signal (3 logic data) before the time point 1. Output logic determining means of logic (+1) or third logic (+2) of
When the output logic is determined by the output logic determining means, there is no output logic of the second electric signal (three logic data) one time slot before the time point 1, that is, the time point 1 is the second electric signal (3 (Logic data) is output at the start time, means for outputting the second logic (+1) at time 1;
When the output logic is determined by the output logic determining means, if the output logic of the second electrical signal (3 logic data) one time slot before time 1 is the second logic (+1), Means for outputting a second logic (+1) at 1;
When the output logic is determined by the output logic determination means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the third logic (+2), Means for outputting a third logic (+2) at time point 1;
When the output logic is determined by the output logic determining means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the first logic (0), The output logic of the second electrical signal (3 logic data) is examined retroactively from time 1 and the output logic of the second electrical signal becomes the second logic (+1) or the third logic (+2) for the first time. At time point 2, time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic ( 0) if the consecutive time slots are even, means for outputting the same logic as the output logic at time 2 at time 1;
According to the counting result of the time slot counting means, if the continuous time slot of the first logic (0) is an odd number and the output logic at the time 2 is the second logic (+1), the third logic at the time 1 If logic (+2) is output and the consecutive time slots of the first logic (0) are odd and the output logic at time 2 is the third logic (+2), the second logic (at time 1) +1) and a means for outputting
With
The optical transmission circuit includes:
The light modulation rule is
For the first logic (0), minimize the light intensity,
For the second logic (+1) and the third logic (+2), the light intensity is maximized, and the optical phases for the second logic (+1) and the third logic (+2) have a phase difference of π from each other Shall have
Further, two delay adjustment circuits that take each optical modulation signal as an input, give a delay according to a delay control signal, and perform output,
An optical coupling circuit that receives the output of each of the two delay adjustment circuits as an input, and combines and outputs the input light;
A second optical branch circuit that takes the output of the optical coupling circuit as an input and branches a part of the input light to the optical spectrum observation circuit;
An optical spectrum observation circuit that adjusts a delay amount of the two delay adjustment circuits so that an input optical spectrum becomes a spectrum of an RZ optical duobinary signal, and
Furthermore, in order to adjust the delay amount,
In the initial state, a means for confirming the generation of the RZ optical duobinary signal by adjusting the delay amount so that the optical spectrum becomes the spectrum of the RZ optical duobinary signal;
Normally, when the power at the maximum value of the optical spectrum, the intensity of the frequency component at the maximum value, and the optical transmission rate are set to R [bit / s], (2/3) × R higher than the carrier frequency. And a means for observing the intensity of the frequency component on the low frequency side and adjusting the delay amount so that the intensity of both frequency components is not more than a predetermined value with respect to the intensity of the frequency component at the maximum value. An optical transmission circuit characterized by that. An optical transmission circuit that multiplexes two parallel optical pulse data signals having the same transmission rate by optical time division multiplexing and generates an optical duobinary signal having a transmission rate twice that of each optical pulse data signal before multiplexing. And
In the optical transmission circuit,
A code conversion circuit which receives an n-parallel 2-logic data signal having an equal signal speed as an input and outputs an n-parallel 3-logic data signal having a signal speed equal to the signal speed;
A pulse light source that outputs an optical pulse train;
A first optical branching circuit that receives the optical pulse train as an input and splits the input light into two to output;
Two optical modulation circuits each having each of the two branched optical outputs as inputs, wherein the kth optical modulation circuit uses the input light as the kth three logic data signal of the code conversion circuit. And a light modulation circuit that modulates according to a predetermined light modulation rule.
The code conversion circuit includes:
A first electric signal (two logical data) obtained by time division multiplexing the n parallel input signals for each time slot and a first electric signal obtained by time division multiplexing the n parallel output signals for each time slot. In order to determine the output logic of the second electrical signal (3 logic data) in 2 electrical signals (3 logic data),
Means for outputting the first logic (0) as the second electric signal (three logic data) when the first logic (0) is inputted as the first electric signal (two logic data);
When the second logic (+1) is input as the first electrical signal (2 logic data), the second electrical signal (3 logic data) is changed to the first electrical signal (2 logic data). At a time point 1 that is a logic output time point of the corresponding second electric signal (3 logic data), a second output is determined by the logic output pattern of the second electric signal (3 logic data) before the time point 1. Output logic determining means of logic (+1) or third logic (+2) of
When the output logic is determined by the output logic determining means, there is no output logic of the second electric signal (three logic data) one time slot before the time point 1, that is, the time point 1 is the second electric signal (3 (Logic data) is output at the start time, means for outputting the second logic (+1) at time 1;
When the output logic is determined by the output logic determining means, if the output logic of the second electrical signal (3 logic data) one time slot before time 1 is the second logic (+1), Means for outputting a second logic (+1) at 1;
When the output logic is determined by the output logic determination means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the third logic (+2), Means for outputting a third logic (+2) at time point 1;
When the output logic is determined by the output logic determining means, when the output logic of the second electric signal (three logic data) one time slot before the time point 1 is the first logic (0), The output logic of the second electrical signal (3 logic data) is examined retroactively from time 1 and the output logic of the second electrical signal becomes the second logic (+1) or the third logic (+2) for the first time. At time point 2, time slot counting means for counting the number of time slots in which the first logic (0) from time point 1 to time point 2 continues, and the first logic ( 0) if the consecutive time slots are even, means for outputting the same logic as the output logic at time 2 at time 1;
According to the counting result of the time slot counting means, if the continuous time slot of the first logic (0) is an odd number and the output logic at the time 2 is the second logic (+1), the third logic at the time 1 If logic (+2) is output and the consecutive time slots of the first logic (0) are odd and the output logic at time 2 is the third logic (+2), the second logic (at time 1) +1) and a means for outputting
With
The optical transmission circuit includes:
The light modulation rule is
For the first logic (0), minimize the light intensity,
For the second logic (+1) and the third logic (+2), the light intensity is maximized, and the optical phases for the second logic (+1) and the third logic (+2) have a phase difference of π from each other Shall have
Further, two delay adjustment circuits that take each optical modulation signal as an input, give a delay according to a delay control signal, and perform output,
An optical coupling circuit that receives the output of each of the two delay adjustment circuits as an input, and combines and outputs the input light;
An optical bandpass filter having the output of the optical coupling circuit as an input, wherein the passband occupies the fundamental wave component of an optical duobinary signal having a transmission rate twice that of each optical pulse data signal before multiplexing. An optical bandpass filter equal to the band to be
A second optical branching circuit that takes the output of the optical bandpass filter as an input and branches a part of the input light to the optical spectrum observation circuit;
An optical spectrum observation circuit that adjusts a delay amount of the two delay adjustment circuits so that an input optical spectrum becomes a spectrum of an optical duobinary signal,
Furthermore, in order to adjust the delay amount,
In the initial state, means for adjusting the delay amount so that the optical spectrum becomes the spectrum of the optical duobinary signal and confirming the generation of the optical duobinary signal;
Normally, when the power at the maximum value of the optical spectrum, the intensity of the frequency component at the maximum value, and the optical transmission speed are R [bit / s], the carrier frequency is higher by (1/2) × R. And a means for observing the intensity of the frequency component on the low frequency side, and adjusting the amount of delay so that the intensity of both frequency components is not more than a predetermined value with respect to the intensity of the frequency component at the maximum value. A characteristic optical transmission circuit.

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