JP3961707B2 - Exposure method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an exposure method for an area in which a plurality of patterns having a common periodicity are arranged.
[0002]
[Prior art]
In recent years, miniaturization of semiconductor integrated circuits has progressed, and requirements for dimensional controllability and depth of focus for resist patterns have become strict. Therefore, various super-resolution techniques for various patterns have been proposed.
[0003]
As an example, in a one-dimensional periodic pattern such as a line and space, it is known that a greater depth of focus can be obtained by exposing with oblique incidence illumination such as annular illumination. In the exposure method using the oblique incidence illumination method, the effect is further improved by using a halftone phase shift mask as a mask to be used.
[0004]
In the case of a one-dimensional periodic pattern, it is possible to obtain a wider depth of focus by performing exposure using a Levenson type phase shift mask under illumination conditions with a relatively small σ value of about σ value 0.3. The optimum value and shape of σ vary depending on the pattern size to be formed on the substrate, and it is necessary to optimize this for various patterns in order to obtain the maximum depth of focus.
[0005]
In general, in the case of a semiconductor device such as a DRAM, a pattern having a relatively high periodicity is formed in the cell array, but the peripheral circuit portion often does not have a certain periodicity. Therefore, as disclosed in Japanese Patent Laid-Open No. 10-64788, there has been proposed a method of performing multiple exposure using different masks for the cell array portion and the peripheral circuit portion under optimized illumination conditions.
[0006]
On the other hand, it is known that a two-dimensional pattern such as a contact hole, unlike a one-dimensional periodic pattern, can obtain a large depth of focus by exposing with a halftone phase shift mask and a small σ illumination condition.
[0007]
However, when various different illumination conditions are mixed in the exposure process performed when creating patterns corresponding to the components of each semiconductor device in this way, they are transferred onto the wafer depending on the individual illumination conditions and pattern pitches. It is expected that the position will be displaced and the overlay accuracy will deteriorate.
[0008]
Generally, in alignment exposure of a semiconductor device, an exposure device detects an alignment mark formed in advance on a substrate on which a pattern is to be transferred, and based on the coordinate data, each chip to be transferred onto a wafer is detected. The position and magnification are calculated and transferred. As for the alignment accuracy of the transferred pattern, a deviation of the relative position between the alignment accuracy measurement mark formed on the substrate in advance and the alignment accuracy measurement mark formed by resist or the like by exposure is measured. In the actual exposure process, when the deviation of the relative position deviates from the allowable value, the deviation is corrected and exposure is performed again.
[0009]
However, when lens distortion such as coma aberration exists in the optical system, a positional shift occurs due to a difference in pattern pitch. Therefore, even if the pattern position accuracy in the mask has sufficient accuracy, if the optical system has coma aberration, the positional deviation may occur in the cell.
[0010]
[Problems to be solved by the invention]
As described above, when exposure is performed using a variety of different illumination conditions in order to satisfy the requirements for dimensional controllability and depth of focus, the position is transferred onto the wafer depending on the individual illumination conditions and pattern pitch. There was a problem that a deviation occurred and the overlay accuracy deteriorated.
[0011]
An object of the present invention is to provide an exposure method that suppresses deterioration of overlay accuracy while satisfying requirements for dimensional controllability and depth of focus.
[0012]
[Means for Solving the Problems]
[Constitution]
The present invention is configured as follows to achieve the above object.
(1) The exposure method of the present invention (Claim 1) has a plurality of periodicities common to the periodic pattern arrangement region of the substrate to be exposed. Kind of An exposure method for exposing a pattern, each having the common periodicity seed Pattern exposure is performed under substantially the same illumination conditions using a mask on which a pattern corresponding to the common periodicity is arranged, and the mask and the substrate to be exposed are moved relative to the substrate. At least one by performing exposure seed The pattern is exposed.
[0013]
Preferred embodiments of the present invention are shown below.
The substrate to be processed is composed of a plurality of layers, each having the common periodicity seed Pattern exposure is performed on a plurality of layers in the periodic pattern arrangement region of the substrate to be processed.
Each having the common periodicity seed The pattern exposure is performed on the same layer in the periodic pattern arrangement region of the substrate to be processed.
[0014]
(2) An exposure method of the present invention (Claim 4) is an exposure method for exposing a cell array region of a DRAM, and the exposure in the cell array includes a plurality of exposures in the cell array. Kind of It is performed under substantially the same illumination conditions using the same mask on which a pattern corresponding to the common periodicity of the pattern is formed, and at least one seed The substrate is exposed while moving the mask and the substrate to be exposed relative to the pattern.
[0015]
Preferred embodiments of the present invention are shown below.
A mask on which a pattern corresponding to the hole pattern is formed is used as the mask.
The mask is a halftone phase shift mask.
Exposure is performed under small σ illumination conditions.
Auxiliary patterns for eliminating side lobes are arranged and formed around the pattern corresponding to the hole pattern.
In addition, it is preferable that exposure of the cell array and multiple exposure of the peripheral circuit portion are performed on the alignment mark formed on the substrate that is exposed and formed with a mask different from the mask.
[0016]
[Action]
The present invention has the following operations and effects by the above configuration.
Since a plurality of patterns can be formed without changing the mask and illumination conditions, it is possible to form a pattern in which deterioration of overlay accuracy due to positional deviation between masks or lens distortion between different illumination conditions is suppressed. .
[0017]
In particular, in a cell array in a dynamic random access memory, a plurality of patterns having a common periodicity are formed, and the demand for misalignment is severe. Therefore, by using the present invention, misalignment is reduced and yield is reduced. Can be improved.
[0018]
In addition, since there is a hole pattern as a common periodicity in the cell array, the misalignment can be reduced by using a mask on which a pattern corresponding to the hole pattern is formed.
[0019]
In forming the hole pattern, a large depth of focus can be obtained by using a halftone phase shift mask.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
The resist pattern forming method using the present invention will be described below. The content of the invention is not limited to this.
[0021]
[First Embodiment]
A DUV exposure apparatus using a KrF excimer laser as a light source in the photolithography process in the manufacture of a semiconductor device having a pattern with a relatively high periodicity such as a cell array region of a DRAM (dynamic random access memory) using the present invention An embodiment when using is shown. As an example, the exposure apparatus shows an exposure method using a reduction projection optical system, but the present invention is not limited to this. A reflection optical system may be used as the deep ultraviolet exposure apparatus. The light source is not limited to this. By the way, the reduction ratio is 1/4.
[0022]
In this embodiment, the pattern is moved in the horizontal direction (xy direction) and the vertical direction (z direction), taking as an example the case of forming a pattern with relatively high periodicity in the cell array region of the DRAM designed with the minimum design rule of 0.175 μm. A case where an exposure apparatus having a possible wafer stage is used will be described.
[0023]
First, as shown in FIG. 1, a mask is prepared in which a pattern corresponding to a periodicity common to a series of patterns for forming a cell structure is arranged. In FIG. 1, 2F × 4F = 8F ² A mask in the case of corresponding to the cell structure (F = 0.175 μm × 2 = 0.35 μm) is shown.
[0024]
0.72 μm per side in the center of a rectangular cell of 5.6 μm in the x direction (transferred to 5.6 / 4 = 1.4 μm on the wafer) and 2.8 μm in the y direction (0.7 μm on the wafer) On the wafer (0.18 μm), a square central opening (hereinafter referred to as a hole) 11 and four corners with four corners on each side. 12 Is formed. On the actual mask, there are four corner holes. 12 Is the hole in the other four corners of the adjacent cell 12 As in the case of the hole 11 at the center, one hole having a side of 0.72 μm is formed. Accordingly, when exposure is performed without relatively moving the mask and the wafer, as shown in FIG. 2, a hole pattern having a side of 0.72 μm (0.18 μm on the wafer) is transferred.
[0025]
The mask 10 is formed of a halftone phase shift mask, and auxiliary patterns 13 and 14 for suppressing side ropes are formed around the holes 11 and 13. When a halftone phase shift mask is used to form a hole pattern and exposure is performed under illumination conditions with a small σ, a large depth of focus can be obtained.
[0026]
FIG. 3 shows a schematic configuration of the exposure apparatus used in the exposure of the present embodiment. The position of the reticle stage 32 on which the mask 31 is placed is detected by the reticle stage xy coordinate detection mechanism 33, and the position of the stage 32 is controlled by the reticle stage control unit 34. The exposure light transmitted through the mask 31 is irradiated onto the surface of the wafer 36 placed on the wafer stage 37 via the reduction optical system 35. The vertical position of the wafer stage 37 is measured by the wafer stage z coordinate detection mechanism 38 and the horizontal position is measured by the wafer stage xy coordinate detection mechanism 39, and the position of the stage 37 is controlled by the wafer stage control unit 40. .
[0027]
The pattern is transferred to the wafer coated with the negative resist through the mask 31. An optical image of holes as shown in FIG. 4 is formed on the wafer. FIG. 4 shows an optical image when the NA of the exposure apparatus obtained by simulation is 0.6 and σ is 0.3. Contour lines indicate isodose lines cut at 5%. The vertical direction of FIG. 4 shows an image when the focus value is changed at 0.2 μm with the center as the focus center.
[0028]
At this time, the pattern shown in FIG. 5 is transferred onto the wafer by moving the wafer relative to the mask while scanning in the x direction. FIG. 5 shows a simulation result of an optical image transferred onto the wafer when the images obtained in FIG. 4 are shifted by 1.0 μm (on the wafer) in the x direction. In the present embodiment, a negative resist is used to form a line having a length of 1.0 μm and a width of 0.175 μm.
[0029]
The stage is moved by the following method. First, the wafer 36 on the wafer stage 37 is set at a predetermined position with respect to the mask 31. This is performed by detecting the position of the stage 37 by the wafer stage xy position detection mechanism 39 and moving it by the wafer stage control unit 40. Such a wafer moving mechanism is possible by using a wafer stepper or scanner wafer stage mechanism used in a lithography process of a semiconductor device.
[0030]
Actually, the formation of the pattern shown in FIG. 5 will be described with reference to FIG. It moves without exposure to a position (point B) shifted to the right (or left) by 0.5 μm from the center (point A) of the pattern on the stage (dotted line in FIG. 6). Subsequently, exposure is performed with an exposure amount for obtaining a predetermined dimension (a pillar-shaped pattern having a diameter of 0.175 μm). Thereafter, the stage is moved 10 nm in the left (or right) direction, and exposure is performed again with the same exposure amount. While repeating this, it moves 1 μm to point C (solid line in FIG. 6).
[0031]
In this case, it is desirable to make the moving distance in the lateral direction as small as the stage accuracy permits. Specifically, in order to reduce the roughness generated in the resist edge portion, it is desirable to set it to 1/100 or less of the total moving distance.
[0032]
As a comparative example, FIG. 7 shows a simulation result when a slit having a width of 0.7 μm (0.175 μm in terms of wafer) is provided on a mask. The illumination conditions are NA = 0.6, σ = 0.75, and the annular zone shielding rate is 0.67. It can be seen that the image quality of the pattern is not deteriorated by using the present invention. Further, in the pattern formed by the mask having the slit opening, there is a deterioration in dimensional accuracy such as a difference in dimension between the bright part between the adjacent patterns and the central part of the bright part is small.
[0033]
The hole pattern shown in FIG. 2 and the pattern shown in FIG. 6 can be formed under the same mask and the same illumination condition, and there is no misalignment due to the positional accuracy of a plurality of masks in a region having periodicity. It is possible to form. The exposure of these different patterns may be performed on the same layer or on different layers.
[0034]
In general, when multiple patterns are used on a single substrate using multiple masks, coordinate offsets, scaling, and straightness, and in-shot scaling and straightness position correction are performed for each shot in the wafer. Although it is performed, no correction is made for local positional deviation such as shot stitching at the time of mask drawing. Accordingly, since the pattern is displaced in the mask, the resist pattern burned on the wafer is also displaced.
[0035]
However, in the present invention, since various patterns are formed using the same mask, misalignment due to mask shot joining is also avoided.
[0036]
As for the peripheral circuit, multiple exposure is performed with a separate reticle to form a pattern. Generally, however, the peripheral circuit does not require alignment accuracy as much as in the cell, so alignment misalignment due to multiple exposure is not a problem.
[0037]
Next, an alignment method in the case where patterns are formed in different layers (layers) in a DRAM (dynamic random access memory) cell array region will be described. Before the cell array pattern is transferred onto the wafer, the wafer alignment mark 81 and each layer are aligned at a predetermined position in the exposure area on the wafer using a first exposure mask 80 as shown in FIG. A part or all of the accuracy measurement mark 82 is transferred. In FIG. 8, both marks are provided in the dicing line area.
[0038]
In the subsequent exposure of the cell array region, the wafer alignment marks transferred in the first exposure are detected and aligned to perform overlay exposure. In the cell array exposure mask 90 shown in FIG. 9, the alignment mark 91 and the alignment mark 91 and the alignment accuracy measurement mark 82 of the first exposure mask 80 corresponding to the wafer alignment mark 81 and the alignment accuracy measurement mark 82 of each layer in advance. An alignment accuracy measurement mark 92 is formed.
[0039]
As an example, when an alignment accuracy detection method called a bar-in-bar method is used, a part or all of outer marks for a series of layers are formed by the first exposure. In the subsequent formation of the inner mark of each layer, when the cell array portion is exposed, as shown in FIG. 10, a blind 100 having an opening in a specific area is used, and the cell array portion to be formed is formed. This is moved by a predetermined amount of movement so that only the alignment mark is exposed. FIG. 10 shows a case where only d of the alignment accuracy measurement marks 92 of a to g shown in FIG. 10A is exposed.
[0040]
The blind 100 having a specific opening is moved by a predetermined amount in the x and y directions on the mask, and as shown in FIG. 10B, the alignment accuracy detection mark among the alignment accuracy detection marks a to g. Only d is exposed. In this case, since the contrast of the image formed on the wafer deteriorates at the edge portion of the area shielded by the blind, the distance l between the marks is set to 50 to 100 μm, and between the marks is shielded. Is desirable.
[0041]
As shown in FIG. 11A, the alignment accuracy measurement mark shifts in position according to the movement amount of the overlay exposure of the cell pattern (the dotted line area shown in the drawing is exposed). The alignment accuracy measurement mark shown in FIG. 11 is moved in the x direction with respect to the hole pattern in the cell array as shown in FIG. The movement indicates a case where movement is made at an equal distance in both directions with respect to a reference hole position (x = 0). The position of the inner mark to be transferred is determined by calculating the edge position after taking this movement amount into account, and the alignment accuracy is measured.
[0042]
Next, alignment between the cell array portion and the peripheral circuit will be described. First, a case where two adjacent wires from the cell array are connected to the sense amplifier will be described.
[0043]
A case where two adjacent wirings (131 and 132, 13 ′ and 132 ′) are overlaid and exposed on a peripheral circuit (sense amplifier) as shown in FIG. 12 will be described.
[0044]
First, a negative resist is applied on a substrate, and heat treatment is performed to form a resist film. Next, exposure is performed while moving the wafer relative to the mask as follows. First, exposure is started from point a in FIG. 13, and exposure is performed while moving to point b in the y direction. As the wafer moves with respect to the mask in this way, line patterns 131, 133, 131 ′ and 133 ′ as shown in FIG. 12 are formed. Subsequently, the image moves to the point c in the x direction without performing exposure, and reaches the point d from the point c in the y direction while performing exposure again. Movement from the point c to the point d forms the lines 132, 134, 132 ′ and 134 ′ shown in FIG. At the points b and c, the portions overlapping the patterns of the lines 131 and 132 in FIG. On the opposite side of the cell array portion, lines 133 and 134 in FIG. 12 are similarly connected to the sense amplifier portion.
[0045]
Next, the case where every other wiring from the cell array is connected to the peripheral circuit will be described. A case will be described in which the wiring (151 and 153 and 151 ′ and 152 ′) is alternately exposed on the peripheral circuit as shown in FIG.
[0046]
As described above, first, a negative resist is applied on the substrate, and heat treatment is performed to form a resist film. Subsequently, exposure is performed while moving the wafer relative to the mask as follows. First, exposure is started from point a in FIG. 15, and exposure is performed while moving to point b in the y direction. As the wafer moves in this manner, line patterns 151, 152, 151 ′ and 152 ′ as shown in FIG. 14 are formed. Subsequently, without exposure, the point moves to point c having one pitch in the x direction and one pitch in the y direction, and reaches point d from point c in the y direction while performing exposure again. Movement from the point c to the point d forms the lines 153, 154, 153 ′ and 154 ′ shown in FIG. At the points b and c, the sense amplifier section overlaps with the overlapping portions of the line patterns 151 and 153 in FIG. On the opposite side of the cell array portion, the lines 152 and 154 in FIG. 14 are similarly connected to the sense amplifier portion.
[0047]
[Second Embodiment]
In this embodiment, the case where the twin hole pattern shown in FIG. 16 is formed by the exposure method similar to that of the first embodiment is shown.
[0048]
In the case of forming a hole pattern, exposure is performed on a wafer coated with a positive resist under the same illumination conditions as in the first embodiment. The optical image transferred onto the wafer when the wafer is not scanned is the same as in FIG. However, in this embodiment, since a positive resist is used, the resist in the exposed portion is removed.
[0049]
The exposure method will be described with reference to FIG. First, the stage is moved from point A to point D without exposure (dotted line from point A to point D in the figure). Then, it exposes with the exposure amount required in order to form a desired dimension. Thereafter, the wafer is moved 4.5 nm in the Y direction and exposed again with the same exposure amount. By repeating this 100 times, it moves to point E and forms a hole pattern on one side. The total amount of movement at this time is 0.45 μm (solid line from point D to point E in the figure). Subsequently, it moves 0.35 μm without exposure in the X direction (dotted line from point E to point F in the figure). Further, exposure is performed while moving in the Y direction in the direction opposite to the direction in which the previous exposure is performed in the same manner as described above while moving a total of 0.45 μm (solid line from point F to point G in the figure). FIG. 9 shows the simulation result of the optical image obtained in this case, as in FIG. Even in this case, good image quality can be obtained in the formed pattern.
[0050]
Furthermore, in the present invention, a semiconductor device with better alignment accuracy can be provided by forming these series of resist patterns and performing processing.
[0051]
[Third Embodiment]
In order to obtain the pattern formed in the first and second embodiments, the stage may be moved continuously. In this embodiment, the first embodiment so Another method for forming the pattern shown is shown.
[0052]
The mask used is the same as in the first embodiment. The exposure method is as follows. First, the stage is moved to a point C further to the left of point A. Next point C The stage is accelerated further to the right so that the speed is constant before passing through point A. At the same time as the stage passes through the point A, exposure is started with a predetermined constant exposure amount. When the stage passes point B which is 1.0 μm rightward from point A, the exposure is finished. By doing so, an optical image equivalent to or higher than that of the first embodiment can be obtained on the wafer. The movement of the wafer during the post-exposure is not necessarily performed at a constant speed. In that case, it is necessary to control in advance the speed change during exposure and the exposure amount at that time.
[0053]
Further, to form these patterns, the reticle stage may be moved. In this case, the movement amount is four times that of the wafer stage (depending on the reduction magnification). The moving method is the same as that of the wafer stage.
[0054]
[Fourth Embodiment]
The exposure method by the equal magnification X-ray exposure by this invention is shown. Basically, an equal-magnification X-ray mask in which a hole pattern having periodicity is formed is prepared as in the first embodiment.
[0055]
In the case of the same magnification X-ray exposure, the movement of the mask (reticle) and the wafer may be performed on either stage. In this case, unlike the reduction optical system, the movement amount of the reticle stage is the same as that of the wafer stage.
[0056]
[Fifth Embodiment]
The present invention can also be applied to pattern drawing of a mask (reticle) used in a lithography process of a semiconductor device. In particular, a series of master patterns can be drawn with higher accuracy by using the drawing by the laser drawing apparatus and the exposure method according to the present invention. In particular, by combining the present invention with a reduction optical system such as a mask aligner, it is possible to draw a pattern with higher accuracy.
[0057]
In the present embodiment, first, a master disk having a common periodicity is prepared for a series of patterns serving as a base. This is the same as the basic configuration of the mask shown in the first embodiment. The only difference is its size. Subsequently, as in the wafer process of the first embodiment, the pattern is transferred by moving the reticle stage relative to the stage of the master.
Furthermore, by drawing the peripheral circuit of each pattern with a laser drawing apparatus, drawing in a cell having a huge amount of data can be performed more quickly.
[0058]
The present invention is not limited to the above embodiment. For example, in the present invention, 1 cm for light exposure, X-ray exposure, etc. ² Although it is more effective in an exposure method that can expose the above large light intensity region in a lump, it is also basically effective in a drawing method such as electron beam exposure.
In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.
[0059]
【The invention's effect】
As described above, according to the present invention, the mask on which the pattern corresponding to the common periodicity is formed and the substrate to be processed are moved relative to the plurality of patterns having the common periodicity. By forming each pattern by exposing it under almost the same illumination conditions, multiple patterns can be formed without changing the mask and illumination conditions, so that the positional deviation between masks and lens distortion between different illumination conditions, etc. It is possible to form a pattern that suppresses deterioration of overlay accuracy due to.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a mask that exposes a pattern having a common periodicity according to the first embodiment.
2 is a plan view showing a hole pattern formed when exposure is performed without relatively moving the mask and the hole shown in FIG. 1;
FIG. 3 is a view showing the schematic arrangement of an exposure apparatus according to the first embodiment.
4 is a plan view showing an optical image of holes formed using the mask shown in FIG. 1. FIG.
FIG. 5 is a diagram showing a simulation result of an optical image transferred onto a wafer when the optical image shown in FIG. 4 is shifted in the x direction.
FIG. 6 is a view for explaining an exposure method according to the first embodiment.
FIG. 7 is a view showing a simulation result when exposure is performed with the slit of FIG.
FIG. 8 is a plan view showing a configuration of a mask having wafer alignment marks and alignment accuracy measurement marks according to the first embodiment.
FIG. 9 is a plan view showing a schematic configuration of a mask used for exposure of a cell array.
10 is a view for explaining an exposure method using FIGS. 9 and 10. FIG.
FIG. 11 is a diagram showing alignment accuracy marks during exposure.
FIG. 12 is a plan view showing a circuit in which two wirings are connected to a peripheral circuit adjacent from the cell array.
13 is a diagram for explaining a method of performing two-layer exposure using the mask shown in FIG. 1 on two wirings connected to the peripheral circuit of the wiring pattern shown in FIG. 12;
FIG. 14 is a plan view showing a circuit in which every other wiring is connected to a peripheral circuit adjacent from the cell array;
15 is a diagram for explaining a method of performing superposition exposure using the mask shown in FIG. 1 for every other wiring connected to the peripheral circuit of the wiring pattern shown in FIG. 14;
16 is a plan view showing the configuration of a twin hole according to the second embodiment and formed using the mask of FIG. 1. FIG.
[Explanation of symbols]
10 ... Mask
11 ... Hall
13 ... Hall
31 ... reticle
32 ... Reticle stage
33 ... Reticle stage coordinate detection mechanism
34 ... Reticle stage control unit
35 ... Reduction optical system
36 ... wafer
37 ... Wafer stage
38 ... Wafer stage z-coordinate detection mechanism
39 ... Wafer stage xy coordinate detection mechanism
40 ... Wafer stage control unit
80... First exposure mask
81 ... Mark for wafer alignment
82 ... Mark for measuring alignment accuracy
90 ... Mask
91 ... Mark for wafer alignment
92 ... Mark for measuring alignment accuracy

Claims (7)

An exposure method for exposing a plurality of types of patterns having a common periodicity to a periodic pattern arrangement region of a substrate to be exposed,
The exposure of each species patterns having a common periodicity performed in substantially the same illumination conditions using the same mask pattern is disposed and formed corresponding to the common periodicity said, and said for at least a kind of pattern mask And exposing the substrate while relatively moving the substrate and the substrate to be exposed. The target substrate is composed of a plurality of layers, the exposure of each species patterns having the common periodicity is characterized by being performed for a plurality of layers in the periodic pattern area of the target substrate The exposure method according to claim 1. The exposure of each species patterns having a common periodicity The exposure method according to claim 1, characterized in that said made to the same layer of the cyclic pattern in placement region of the substrate. An exposure method for exposing a cell array region of a DRAM,
Exposure in the cell array is carried out in substantially the same illumination conditions using the same mask pattern is formed corresponding to the common periodicity having a plurality of kinds of pattern in the cell array, and at least one kind of pattern An exposure method comprising exposing the substrate while relatively moving the mask and the substrate to be exposed.   The exposure method according to claim 4, wherein a mask on which a pattern corresponding to a hole pattern is formed is used as the mask.   6. The exposure method according to claim 5, wherein the mask is a halftone phase shift mask.   6. The exposure method according to claim 5, wherein an auxiliary pattern for erasing the side lobe is arranged around the pattern corresponding to the hole pattern.

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