JP3962120B2 - Gate turn-off thyristor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gate turn-off thyristor, and more particularly to a gate turn-off thyristor (hereinafter also abbreviated as a GTO thyristor) with reduced power loss.
[0002]
[Prior art]
GTO thyristors are required to have higher withstand voltages in the field of high withstand voltage and large current as self-extinguishing elements for electric power.
[0003]
However, high breakdown voltage GTO thyristors have large increases in both steady loss and switching loss, and reduction of these losses is required.
[0004]
FIG. 9 is a perspective view showing an example of a conventional GTO thyristor. In FIG. 9, 1 is a pE, 2 is an n ⁻ layer, 3 is a pB layer, 4 is an nE layer, and 5 is a metal layer provided on the exposed surface of the pE layer 1 to form an anode electrode portion. 6 is a metal layer provided on the nE layer 4 and forms a cathode electrode portion as a cathode electrode layer.
[0005]
In the GTO thyristor of FIG. 9, the thickness W of the n ⁻ layer or the n base layer 2 increases as the breakdown voltage increases. However, in general, the thickness W of the n base layer 2 and the ON voltage are in a proportional relationship. Therefore, when the thickness W of the n base layer 2 increases, the ON voltage increases, resulting in an increase in steady loss.
[0006]
In order to solve the above problem, a GTO thyristor as shown in FIG. 10 has been proposed. In the GTO thyristor of FIG. 10, the n ⁺ layer 9 and the n ⁻ layer 10 form the equivalent of the n base layer 2 in FIG. 9, and the GTO thyristor in FIG. 10 is generally called a pnνpn structure. Is.
[0007]
In the pnνpn structure, since the n base of the pn base structure of FIG. 9 is formed by the low concentration n ⁻ layer 9 and the high concentration n ⁺ layer 10, the thickness of the n base is the same under the same withstand voltage. There is an advantage that about 70% of the thickness in the case of FIG. That is, the steady loss is small in the pnνpn structure accordingly.
[0008]
On the other hand, the switching loss includes a turn-on loss and a turn-off loss. Of these, the turn-on loss is about 10% of the turn-off loss, and it is the turn-off loss that increases when the breakdown voltage of the device is increased. Nearly 90% of the turn-off loss is caused by tail loss, and this tail loss is caused by tail current.
[0009]
In the GTO thyristor turn-off process, the tail current draws excess carriers in the p base layer from the p gate layer, and remains in the n base layer when the main junction between the p base layer and the n base layer recovers. This is a current that flows when excess carriers disappear.
[0010]
Since the n base layer does not have a gate portion unlike the p base layer, excess carriers are not extracted from the gate portion, but disappear by recombination with carriers injected from the p emitter layer.
[0011]
When the device withstand voltage is increased, the impurity concentration of the n base layer is lowered and the thickness thereof must be increased, so that excessive carriers are increased. Moreover, in order to prevent the turn-on characteristics from being significantly impaired by increasing the thickness of the n base layer, the carrier lifetime of the n base layer must be set long. For these reasons, the higher the withstand voltage of the GTO thyristor, the higher the tail current and the higher the tail loss.
[0012]
In order to solve such problems, recently, a structure called an anode-emitter short structure has been proposed in the pnpn structure and the pnνpn structure of the conventional GTO thyristor. For example, such a structure is disclosed in JP-A-1-165169 (part 1), JP-A-4-23472 (part 1 (h)) or JP-A-4-112543 (part 1). (H) and Japanese Patent Laid-Open No. 1-318264 (part 1) thereof. In this structure, a part of the n base layer is extended so as to penetrate the p emitter layer and shorted to the anode electrode, and excess carriers in the n base layer during the tail time can be extracted from the anode electrode. This is the structure. Therefore, the anode-emitter short structure has an advantage that tail loss is small and, as a result, switching loss is small.
[0013]
[Problems to be solved by the invention]
A structure in which an anode-emitter short structure is applied to a pnνpn structure is applied as an effective method for reducing steady loss and switching loss which increase with the increase in withstand voltage of a GTO thyristor. However, since the method using a short circuit between the n ⁺ buffer layer and the p emitter layer is used there, in order to realize higher frequency in addition to higher voltage resistance, The problem of increased turn-off loss due to tail current comes up again.
[0014]
The present invention has been made to solve such a problem, and has a novel structure of a GTO thyristor that can realize a sufficient reduction in turn-off loss even for higher withstand voltage and higher frequency. Thus, it is possible to provide the conventional manufacturing method by adding only one step.
[0015]
[Means for Solving the Problems]
The invention according to claim 1 includes a first emitter layer having a first conductivity type impurity having a first surface concentration, a first base layer having a second conductivity type impurity, and the first conductivity type impurity. In a gate turn-off thyristor in which a second base layer and a second emitter layer having an impurity of the second conductivity type are sequentially stacked, the first base layer has a second surface concentration of the second conductivity type. A semiconductor layer for promoting excess carrier recombination having impurities, a buffer layer having impurities of the second conductivity type having a third surface concentration, and a base body layer having impurities of the second conductivity type having a fourth surface concentration; And the relationship of the first surface concentration> the second surface concentration> the third surface concentration> the fourth surface concentration is established.
[0016]
According to a second aspect of the present invention, in the gate turn-off thyristor according to the first aspect, the third surface concentration is such that an electric field of a depletion layer caused by a rated voltage does not affect the semiconductor layer for promoting excess carrier recombination. It is characterized by being set to.
[0017]
According to a third aspect of the present invention, in the gate turn-off thyristor according to the first or second aspect, if the first surface concentration is 10 ⁿ , a difference between the first surface concentration and the second surface concentration is (10 ⁿ The second surface concentration is set to be −10 ⁿ⁻¹ ) or less.
[0018]
The invention according to claim 4 is the gate turn-off thyristor according to any one of claims 1 to 3, wherein the first emitter layer is formed on the first electrode layer, and the second electrode layer is the second emitter. The second emitter layer is laminated on a predetermined portion of the second base layer, and a predetermined portion corresponding to a part of the excess carrier recombination promoting semiconductor layer is formed on the first emitter layer. It penetrates and is connected with the 1st electrode layer, It is characterized by the above-mentioned.
[0019]
The invention according to claim 5 is the gate turn-off thyristor according to claim 4, wherein the predetermined portion of the semiconductor layer for promoting excess carrier recombination is formed immediately below the second emitter layer. It is characterized by being formed in a direction parallel to the direction.
[0020]
According to a sixth aspect of the present invention, in the gate turn-off thyristor according to the fourth aspect, the predetermined portion of the excessive carrier recombination promoting semiconductor layer is formed immediately below the second emitter layer. It is formed in a direction orthogonal to the direction.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor device according to the present invention includes a pE layer (first emitter layer), an n ⁺⁺ layer (excess carrier recombination promoting semiconductor layer), an n ⁺ layer (buffer layer), and an n ⁻ layer (first base body layer). , PB layer (second base layer) and nE layer (second emitter layer) constitute a GTO thyristor element, and the six-layer structure and the conventional anode-emitter short structure are also optimized. It is a thing.
[0022]
(Embodiment 1)
The element structure of the GTO thyristor according to Embodiment 1 of the present invention will be described with reference to FIGS. The element structure of the thyristor is basically a pnνpn structure.
[0023]
As shown in the perspective view of FIG. 1, a pE layer 1 as a p-type emitter layer and an n-type semiconductor layer for promoting excess carrier recombination are formed on an anode electrode layer (metal layer) 5 that functions as an anode electrode. N ⁺⁺ layer 11, n ⁺ layer 10 as an n-type buffer layer for blocking the electric field of the depletion layer, n ⁻ layer 9 functioning as an n-type base layer body, and pB layer 3 as a p-type base layer In addition, nE layers 4 as n-type emitter layers are sequentially stacked. However, the nE layer 4 is laminated on the predetermined portion 3A of the pB layer 3 in parallel with the first direction D1. Reference numeral 6 denotes a metal layer provided on the nE layer 4 and forms a cathode electrode portion as a cathode electrode layer. 7 is a gate electrode layer laminated on the upper surface of the pB layer 3 other than the predetermined portion 3A in the first direction D1, and the portion of the pB layer 3 immediately below the gate electrode layer 7 functions as a p-type gate portion. To do. The n ⁻ layer 9, the n ⁺ layer 10, and the n ⁺⁺ layer 11 form an “n-type base layer (first base layer)”.
[0024]
The core of this structure is that an n ⁺⁺ layer 11 is formed entirely between the pE layer 1 and the n ⁺ layer 10.
[0025]
The diffusion profile in this structure is shown in FIG. In FIG. 2, 1 ′ represents the surface concentration (first surface concentration) of the impurity of the pE layer 1, 9 ′ represents the surface concentration of the n ⁻ layer 2 (fourth surface concentration), and 3 ′ represents the surface concentration of the pB layer 3. 4 ′ is the surface concentration of the nE layer 4, 10 ′ is the surface concentration of the n ⁺ layer 10 (third surface concentration), 11 ′ is the surface concentration of the n ⁺⁺ layer 11 (second surface concentration), Each is shown schematically. As is clear from FIG. 2, in this structure, the relationship 1 ′> 11 ′> 10 ′> 9 ′ is established, and the relationship described later is established between the surface concentrations 1 ′ and 11 ′.
[0026]
The surface concentration 10 ′ of the n ⁻ layer 10 shown in FIG. 2 is a minimum surface concentration such that the electric field of the depletion layer generated in the n base layer does not reach the formation part of the n ⁺⁺ layer 11 with respect to the rated voltage. Is set.
[0027]
The method for forming the element having the structure shown in FIG. 1 is realized by providing only one step of forming the n ⁺⁺ layer 11 compared to the conventional method for manufacturing the pnνpn structure. That is, the pB layer 3 is formed by diffusion on the second main surface on the cathode side of the n ⁻ layer silicon substrate 20, and then the n ⁺ diffusion layer is formed from the first main surface on the anode side of the substrate 20, An n ⁻ layer 9 is obtained. Next, an nE layer 4 is formed on the predetermined portion 3A of the pB layer 3, and an n ⁺⁺ layer 11 having a higher concentration than the n ⁺ layer 10 is formed by diffusing a larger amount of n-type impurities than the first main surface. Then, the pE layer 1 having a higher concentration is formed. Thereafter, the electrode layers 5, 6, and 7 are formed. Thus, with respect to the conventional pnνpn structure constituted by five layers of the pE layer, the n ⁺ layer, the n ⁻ layer, the pB layer, and the nE layer, the n ⁺ is interposed between the pE layer 1 and the n ⁺ layer 10. ^{A +} layer 11 is formed.
[0028]
In order to achieve a further reduction in turn-off loss for higher withstand voltage and higher frequency, it is necessary to accelerate recombination of excess carriers generated in the n base layer more quickly. It is necessary, and the conventional technique of extracting excess carriers to the anode electrode side cannot be considered as a fundamental solution. However, in the conventional pnνpn structure, since the concentration difference between the surface concentration of the pE layer 1 and the surface concentration of the n ⁺ layer 10 is 10 ⁴ or more, this concentration difference causes excessive carrier discharge ( This is a cause of inhibiting recombination).
[0029]
In the present invention, focusing on this point, annihilation due to recombination of the excess carriers is promoted, and a further rapid decrease in tail current is promoted. That is, when the surface concentration 11 ′ of the n ⁺⁺ layer 11 formed in a stacked manner between the pE layer 1 and the n ⁺ layer 10 is 10 ⁿ and the surface concentration 1 ′ of the pE layer 1 is 10 ⁿ , the concentration is 10 ^{n−. 1} so that the difference between the surface concentration 1 ′ of the pE layer 1 and the surface concentration 11 ′ of the n ⁺⁺ layer 11 is 10 ⁿ −10 ⁿ⁻¹ (of course, the concentration difference is 10 ⁿ -10 ^n-1 may be smaller). As a result, the concentration difference between the both 1 and 11 is optimized to such an extent that it does not hinder recombination, so that recombination between excess carriers and carriers injected from the pE layer 1 is further promoted, and the turn-off process is performed. It is possible to significantly increase the discharge efficiency of excess carriers in the n ⁻ layer 9 at, thereby reducing the tail current rapidly and greatly reducing the turn-off loss. The effect of reducing tail loss by utilizing the promotion of recombination annihilation is much larger than the reduction due to short-circuit in the conventional anode-emitter short structure. For this reason, the present structure can be applied to demands for higher withstand voltage and higher frequency.
[0030]
Note that the cathode electrode layer 6 and the gate electrode layer 7 in FIG. 1 may have an opposite arrangement relationship (an arrangement in which the gate electrode layer is arranged in the central region and the cathode electrode layer is disposed on the outer periphery thereof).
[0031]
(Embodiment 2)
In the first embodiment, the case where annihilation due to recombination of excess carriers is promoted by adding an n ⁺⁺ layer in the pnνpn structure has been described. However, a conventional anode emitter short structure is applied to this structure. Thus, both (1) excess carrier recombination annihilation and (2) excess carrier extraction by short circuit to the anode side can be achieved. That is, a predetermined portion corresponding to a part of the n ⁺⁺ layer is formed so as to penetrate the pE layer, and the predetermined portion is connected to the anode electrode, thereby short-circuiting the n ⁺⁺ layer and the pE layer. As a result, an anode-emitter short structure pattern is additionally formed, and the same effect as in the first embodiment and the effect of the prior art can be obtained simultaneously.
[0032]
For example, as shown in the longitudinal sectional view 4 and the perspective view of FIG. 3, Te than short-circuit pattern portion 11C which is extended and formed to reach the anode electrode layer 5 from any position n ⁺⁺ layer 11, n ^{+ The +} layer 11 and the pE layer 1 are short-circuited (the pattern of the extended portion 11C of the n ⁺⁺ layer 11 is formed so as to form a dot shape with respect to the nE layer 4).
[0033]
(Embodiment 3)
The present embodiment is a modification of the second embodiment, and the formation position of a predetermined portion of the n ⁺⁺ layer 11 extended to the anode electrode is specified in relation to the nE layer 4.
[0034]
As shown in the perspective view of FIG. 5 and FIG. 6 which is a longitudinal sectional view thereof, the short-circuit pattern portion 11A for short-circuiting the n ⁺⁺ layer 11 and the pE layer 1 4 is formed in a direction (D1) parallel to the forming direction of 4.
[0035]
Thereby, in addition to the effect of Embodiment 2, the following effect is obtained by superimposing. That is, since the area of the short-circuit pattern portion 11A facing the nE layer 4 is larger than that in the second embodiment, the excess carrier discharging efficiency in the turn-off process can be further increased.
[0036]
(Embodiment 4)
The fourth embodiment is also a modification of the second embodiment, but it is intended to improve the demerits of the third embodiment (although the merits of the third embodiment will be slightly reduced). .
[0037]
As shown in FIG. 7 and its longitudinal cross-sectional view 8, when short-circuiting the n ⁺⁺ layer 11 and the pE layer 1 to extend forming a predetermined portion of the n ⁺⁺ layer 11, nE directly below the position of the nE layer 4 A short-circuit pattern portion 11B of the n ⁺⁺ layer 11 is formed along a direction D2 orthogonal to the formation direction D1 of the layer 4.
[0038]
As a result, the excess carrier discharging efficiency in the turn-off process is slightly lower than that in the third embodiment, but the area of the short-circuit pattern portion 11B facing the nE layer 4 is smaller than that in the third embodiment. Only the characteristics in the turn-on process can be improved as compared with the third embodiment.
[0039]
【The invention's effect】
According to the first to third aspects, the semiconductor layer for promoting excess carrier recombination is formed between the buffer layer and the first emitter layer, and the first surface concentration> the second surface concentration> the third. Since the relationship of surface concentration> fourth surface concentration is established, recombination between excess carriers generated in the first base layer and carriers in the first emitter layer at the time of turn-off is further promoted, and this recombination disappears. As a result, the discharge efficiency of excess carriers can be drastically increased. As a result, the tail current can be further reduced. Therefore, it is possible to realize a gate turn-off thyristor with a small turn-off loss even for higher withstand voltage and higher frequency.
[0040]
In particular, in the invention of claim 2, since the third surface concentration of the buffer layer is set appropriately, the semiconductor layer for promoting excess carrier recombination is not affected by the electric field of the depletion layer.
[0041]
According to the invention of claim 3, since the surface concentration difference between the first emitter layer and the semiconductor layer for promoting excess carrier recombination is set to (10 ⁿ -10 ^n-1 ) or less, There is an effect that the difference is small and the recombination annihilation of excess carriers can be more easily generated.
[0042]
According to the fourth aspect of the present invention, the excessive carrier recombination promoting semiconductor layer is formed to extend with a predetermined portion and connected to the first electrode layer. The semiconductor layer and the first emitter layer are short-circuited, and a path for extracting excess carriers generated in the first base layer to the first electrode layer is formed. Therefore, by providing the excessive carrier recombination promoting semiconductor layer itself, both the effects of promoting the recombination annihilation of excess carriers and drawing the excess carriers to the first electrode layer side are obtained in a superimposed manner. Further reduction in tail current or tail loss at turn-off can be achieved.
[0043]
According to the fifth aspect of the present invention, since the predetermined portion of the excess carrier recombination promoting semiconductor layer is formed in parallel with the second emitter layer, the second emitter is included in the excess carrier recombination promoting semiconductor layer. The area of the part facing the layer increases. As a result, the excess carrier discharge efficiency at turn-off can be further increased.
[0044]
According to the sixth aspect of the present invention, the predetermined portion of the excess carrier recombination promoting semiconductor layer is formed so as to be orthogonal to the second emitter layer in particular. 2 The area facing the emitter layer can be secured and the area can be made smaller than in the case of the invention of claim 5, so that the excess carrier discharge efficiency at the turn-off is increased and the loss at the turn-on is reduced. An increase can also be prevented.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an element structure of a GTO thyristor according to a first embodiment.
FIG. 2 is a diagram showing a diffusion profile of each layer in the present invention.
FIG. 3 is a perspective view showing an element structure of a GTO thyristor according to a second embodiment.
FIG. 4 is a longitudinal sectional view showing an element structure of a GTO thyristor according to a second embodiment.
5 is a perspective view showing an element structure of a GTO thyristor according to Embodiment 3. FIG.
FIG. 6 is a longitudinal sectional view showing an element structure of a GTO thyristor according to a third embodiment.
7 is a perspective view showing an element structure of a GTO thyristor of Embodiment 4. FIG.
FIG. 8 is a longitudinal sectional view showing an element structure of a GTO thyristor according to a fourth embodiment.
FIG. 9 is a perspective view showing an element structure of a conventional GTO thyristor.
FIG. 10 is a perspective view showing an element structure of a conventional GTO thyristor.
[Explanation of symbols]
1 pE layer, 3 pB layer, 4 nE layer, 5 anode electrode layer, 6 cathode electrode layer, 9 n ⁻ layer, 10 n ⁺ layer, 11 n ⁺⁺ layer, 11A, 11B, 11C short-circuit pattern portion.

Claims (6)

A first emitter layer having a first conductivity type impurity having a first surface concentration; a first base layer having a second conductivity type impurity; a second base layer having the first conductivity type impurity; In a gate turn-off thyristor in which a second emitter layer having two conductivity type impurities is sequentially stacked,
The first base layer includes
A semiconductor layer for promoting excess carrier recombination having an impurity of the second conductivity type at a second surface concentration;
A buffer layer having impurities of the second conductivity type at a third surface concentration;
Formed by sequential stacking with the base body layer having the second conductivity type impurity of the fourth surface concentration,
The relationship of the first surface concentration> the second surface concentration> the third surface concentration> the fourth surface concentration is satisfied,
Gate turn-off thyristor. The gate turn-off thyristor according to claim 1,
The third surface concentration is set so that an electric field of a depletion layer caused by a rated voltage does not affect the semiconductor layer for promoting excess carrier recombination,
Gate turn-off thyristor. The gate turn-off thyristor according to claim 1 or 2,
When the first surface concentration is 10 ⁿ , the second surface concentration is set such that the difference between the first surface concentration and the second surface concentration is (10 ⁿ -10 ^n-1 ) or less. It is characterized by
Gate turn-off thyristor. The gate turn-off thyristor according to any one of claims 1 to 3,
The first emitter layer is stacked on the first electrode layer;
A second electrode layer is formed on the second emitter layer;
The second emitter layer is stacked on a predetermined portion of the second base layer,
A predetermined portion corresponding to a part of the semiconductor layer for promoting excess carrier recombination is connected to the first electrode layer through the first emitter layer,
Gate turn-off thyristor. The gate turn-off thyristor according to claim 4,
The predetermined portion of the semiconductor layer for promoting excess carrier recombination is formed immediately below the second emitter layer and in a direction parallel to the formation direction of the second emitter layer,
Gate turn-off thyristor. The gate turn-off thyristor according to claim 4,
The predetermined portion of the semiconductor layer for promoting excess carrier recombination is formed in a direction perpendicular to a forming direction of the second emitter layer immediately below the second emitter layer.
Gate turn-off thyristor.

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