JP3963620B2 - Semiconductor chip and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor chip and a manufacturing method thereof, and more particularly to a conductor chip that can be mounted on a substrate and a manufacturing method thereof.
[0002]
[Prior art]
FIG. 8 shows a semiconductor chip 330 according to the prior art and its mounting form. Solder 344 for forming bumps 310 is provided on the aluminum electrode pad 332 of the semiconductor chip 330 via the nickel plating layer 334 and the gold plating layer 338. Here, the semiconductor chip 330 is electrically connected to the electrode pad 352 on the package 350 side via the bump 310.
[0003]
Incidentally, the semiconductor chip 330 and the package 350 have different coefficients of thermal expansion, so it is necessary to relieve stress generated between them. In the mounting form shown in FIG. An underfill 336 is disposed between the two and 350, and the two are fixed so that stress is not concentrated on the electrical connection portion, so that the electrical connection portion is not broken. .
[0004]
However, with the recent high integration of semiconductor chips, the bumps of the semiconductor chip have been downsized, and the electrical connection portion reduced in size due to the stress between the semiconductor chip 330 and the package 350 even in the above-described mounting form. Sometimes broke.
[0005]
[Problems to be solved by the invention]
In response to such problems, the present inventors have devised a technique for forming a thick insulating layer and a copper plating post on the electrode pad side of the semiconductor chip. Here, by increasing the thickness of the insulating layer, the height of the copper plating post is increased to provide flexibility, and the stress generated between the semiconductor chip and the substrate is absorbed. However, it has been found that this method causes a warp when the thick insulating layer is cured, causing a break in the semiconductor chip.
[0006]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor chip that can be mounted with high reliability and a method for manufacturing the semiconductor chip.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, claim 1 is a semiconductor chip to which an external connection substrate is attached via an adhesive,
In the semiconductor chip, an insulating layer on the electrode pad side and a via connected to the electrode pad formed in the insulating layer are formed,
A via hole, a protruding conductor connected to the via side at one end of the via hole, and a bump for external connection at the other end of the via hole are formed on the external connection substrate. Is a technical feature.
[0008]
A second aspect of the present invention provides the electrode pad according to the first aspect, wherein the electrode pad is a zincated aluminum electrode pad, and the via made of copper plating is formed on the electrode pad via a composite plating layer of nickel and copper. This is a technical feature.
[0009]
Claim 3 is a method of manufacturing a semiconductor chip including at least the following steps (1) to (5).
(1) A step of forming a non-through hole reaching the metal layer by laser processing on an insulating base material having a metal layer formed on one surface;
(2) A step of filling the non-through hole formed in (1) with electrolytic plating to form a via hole;
(3) A step of forming a protruding conductor made of a conductive paste or a low melting point metal on the surface of the via hole on the opposite side of the metal layer to form an external connection substrate.
(4) forming an insulating layer on the electrode pad side and a via and a redistribution layer of the insulating layer connected to the electrode pad on the semiconductor chip;
(5) A step of attaching the external connection substrate to the semiconductor chip with an adhesive, and connecting the via hole of the external connection substrate and the rewiring layer of the semiconductor chip via the protruding conductor.
[0010]
Claim 4 is a method of manufacturing a semiconductor chip including at least the following steps (1) to (6).
(1) A step of forming a non-through hole reaching the metal layer by laser processing on an insulating substrate having a metal layer formed on one surface and an adhesive layer and a film stuck on the other surface;
(2) A step of filling the non-through hole formed in (1) with electrolytic plating to form a via hole;
(3) A step of forming a protruding conductor made of a conductive paste or a low melting point metal on the surface of the via hole on the opposite side of the metal layer to form an external connection substrate.
(4) peeling the film of the substrate for external connection and exposing the protruding conductor from the adhesive layer;
(4) forming an insulating layer on the electrode pad side and a via and a redistribution layer of the insulating layer connected to the electrode pad on the semiconductor chip;
(5) A step of attaching the external connection substrate to the semiconductor chip with the adhesive, and connecting the via hole of the external connection substrate and the rewiring layer of the semiconductor chip via the protruding conductor.
[0011]
The semiconductor chip manufacturing method according to claim 5 is a semiconductor chip manufacturing method including at least the following steps (1) to (6).
(1) A step of forming a non-through hole reaching the metal layer by laser processing on an insulating base material having a metal layer formed on one surface;
(2) A step of filling the non-through hole formed in (1) with electrolytic plating to form a via hole;
(3) A step of forming a protruding conductor made of a conductive paste or a low melting point metal on the surface of the via hole on the opposite side of the metal layer to form an external connection substrate.
(4) A step of applying an adhesive to the opposite side of the metal layer of the external connection substrate.
(5) forming an insulating layer on the electrode pad side and a via and a redistribution layer of the insulating layer connected to the electrode pad on the semiconductor chip;
(6) A step of attaching the external connection substrate to the semiconductor chip with the adhesive, and connecting the via hole of the external connection substrate and the rewiring layer of the semiconductor chip via the protruding conductor.
[0012]
According to another aspect of the semiconductor chip of the present invention, the external connection substrate is attached to the semiconductor chip, and the external connection substrate absorbs the stress generated by the difference in thermal expansion between the semiconductor chip and the substrate. The connection reliability of the semiconductor chip can be improved.
[0013]
In claim 2, although it is difficult to perform copper plating on the surface of the aluminum electrode pad of the semiconductor chip, in the present invention, after the zincate treatment is performed on the surface of the aluminum electrode pad, the composite of nickel and copper is formed. In order to form a plating layer, a via can be formed on the composite plating layer by copper plating.
[0014]
In the semiconductor chip manufacturing method according to the third aspect, since the external connection substrate is bonded to the semiconductor chip with an adhesive, the semiconductor chip is not warped during the bonding.
[0015]
In the method for manufacturing a semiconductor chip according to the fourth aspect, since the external connection substrate is attached to the semiconductor chip with an adhesive, the semiconductor chip is not warped at the time of attachment. Here, since the film of the substrate for external connection is peeled off and the protruding conductor is connected to the semiconductor chip in a state exposed from the adhesive layer, the electrical connection reliability is excellent.
[0016]
According to the semiconductor chip manufacturing method of the fifth aspect, since the external connection substrate is attached to the semiconductor chip with an adhesive, the semiconductor chip is not warped during the attachment. Here, since the adhesive is applied after the protruding conductor is formed, the adhesive is not brought into contact with the plating solution or the like, so that the reliability of the adhesive is excellent.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor chip and a method for manufacturing the semiconductor chip according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a semiconductor chip according to a first embodiment of the present invention.
On the lower surface of the semiconductor chip 30, an aluminum electrode pad 32 that is zincated in the opening of the passivation film 34 is formed. In this embodiment, an insulating layer 42 is disposed on the lower surface of the passivation film 34, and a non-through hole 42 a that extends in a tapered shape reaching the aluminum electrode pad 32 is formed in the insulating layer 42. The aluminum electrode pad 32 at the bottom of the non-through hole 42a has a nickel plating layer 38, a composite plating layer 40 of nickel and copper, and a via 44 and a rewiring layer 46 filled with copper plating. Is formed.
[0018]
An external connection substrate 50 is affixed to the lower surface of the semiconductor chip 30. A via hole 62 is formed in the external connection substrate 50, and the upper surface of the via hole 62 is connected to the rewiring layer 46 on the semiconductor chip side via a protruding conductor 64. Solder bumps 68 are formed on the lower surface of the via hole 62. The external connection substrate 50 is connected to the pads 92 of the external substrate 90 through solder bumps 68.
[0019]
Here, the thickness of the external connection substrate 50 and the height of the via hole 62 are 25 to 250 μm. On the other hand, the via hole 62 has a diameter of 20 μm to 300 μm. Here, the thermal expansion coefficients of the semiconductor chip 30 and the substrate 90 are different, and stress is generated between the semiconductor chip 30 and the substrate 90 due to the heat generated during the operation of the semiconductor chip 30. Since the stress can be absorbed by the external connection substrate 50 and the via hole 62 made of copper and having elasticity, no crack is generated in the electrical connection portion, and high connection reliability between the semiconductor chip 30 and the substrate 90 is achieved. Giving sex.
[0020]
Next, a method for manufacturing the semiconductor chip 30 according to this embodiment will be described with reference to FIGS.
Here, first, formation of the insulating layer 42 and the via 44 on the semiconductor chip side will be described. Copper plating posts and bumps are formed in the following steps on the semiconductor chip 30 in which the aluminum electrode pad 32 is formed in the opening of the passivation film 34 shown in the step (A) of FIG. First, as shown in step (B) of FIG. 2, the semiconductor chip 30 is immersed in a solution in which zinc oxide, which is a metal salt, and sodium hydroxide as a reducing agent is mixed for 10 to 30 seconds at room temperature. A zincate process is performed on the pad 32. Thereby, precipitation of a nickel plating layer or a composite plating layer is made easy.
[0021]
Subsequently, as shown in step (C) of FIG. 2, the semiconductor chip 30 is immersed in a nickel electroless plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32. Even if the step of forming the nickel plating layer is omitted, a composite plating layer described later can be directly formed on the aluminum electrode pad 32.
[0022]
Then, as shown in step (D) of FIG. 2, the semiconductor chip 30 is immersed in a nickel-copper composite plating solution, and a nickel-copper composite plating of 0.01 to 5 μm is formed on the nickel plating layer 38. Layer 40 is formed. In addition to enabling the composite plating layer to be formed on the aluminum electrode pad by making the composite plating layer 1 to 60% by weight of nickel and the balance being mainly copper, the copper plating can be easily formed on the surface. To. Moreover, it becomes possible to form copper plating on the surface by setting the thickness of the composite plating layer to 0.01 μm or more. On the other hand, it can precipitate in a short time by setting it as 5 micrometers or less.
[0023]
Next, an insulating resin is applied as shown in step (E) of FIG.
In this embodiment, a thermosetting epoxy resin or polyimide resin is used as the insulating resin in order to form non-through holes by laser processing. When the non-through hole is formed by chemical treatment, a photosensitive epoxy resin or polyimide resin can be used. Next, after performing a drying process as shown in step (F) of FIG. 3, the non-through holes 42a are formed by a laser. Further, an insulating layer 42 having a non-through hole 42a reaching the aluminum electrode pad 32 is formed by heat treatment.
[0024]
Next, as shown in step (G) of FIG. 3, the via 44 is formed by filling the non-through hole 42 a with copper plating, and the rewiring layer 46 is formed on the insulating layer 42. These are formed by electroless plating.
[0025]
Next, a method for manufacturing the external connection substrate 50 will be described with reference to FIG.
As shown in step (A) of FIG. 4, an adhesive layer 54 and a PET (polyethylene terephthalate) film 52 are attached to an insulating substrate 56 having a metal layer 58 formed on one side.
Here, as the insulating substrate 56 to be used, any organic insulating substrate can be used. Specifically, an aramid nonwoven fabric-epoxy resin substrate, a glass cloth epoxy resin substrate, an aramid nonwoven fabric-polyimide group. It may be one kind selected from a rigid base material selected from a material, a bismaleimide triazine resin base material, or a flexible base material made of a film such as a polyphenylene ether (PPE) film or a polyimide (PI). desirable.
[0026]
The insulating substrate 56 is preferably a rigid laminated substrate, and a single-sided copper-clad laminate is particularly suitable. This is because the position of the wiring pattern and via hole is not shifted during handling after the metal layer 58 is etched, and the positional accuracy is excellent.
[0027]
The metal layer 58 formed on the insulating base material 56 can use a copper foil. The copper foil may be matted for improving adhesion. Here, a single-sided copper-clad laminate is used. A single-sided copper-clad laminate can be obtained by laminating a glass cloth with a thermosetting resin such as epoxy resin, phenol resin, bismaleimide-triazine resin, etc., and laminating a prepreg and copper foil as a B-stage, followed by hot pressing. It is a substrate. The single-sided copper-clad laminate is a rigid substrate and is easy to handle and most advantageous in terms of cost. Moreover, after depositing a metal on the surface of the insulating base material 56, a metal layer can also be formed using electrolytic plating.
[0028]
The thickness of the insulating substrate 56 is 25 to 250 μm, preferably 50 to 100 μm. If it is thinner than these ranges, the strength will be reduced, making it difficult to handle and making it difficult to provide sufficient flexibility, and conversely, if it is too thick, it will be difficult to form fine via holes and fill with conductive materials. .
On the other hand, the thickness of the metal layer 58 is 5 to 35 μm, preferably 8 to 30 μm, and preferably 12 to 25 μm. This is because, as will be described later, when drilling is performed by laser processing, if it is too thin, it penetrates. If it is too thick, etching is difficult.
[0029]
The adhesive layer 54 can be formed by coating the entire surface of either the external connection substrate 50 or the insulating layer 42 of the semiconductor chip 30, and there is no need to make a hole for conduction in the adhesive layer. . The adhesive layer 54 is preferably made of an organic adhesive, and examples of the organic adhesive include an epoxy resin, a polyimide resin, a thermosetting polyphenolene ether (PPE), an epoxy resin and a thermoplastic resin. It is desirable to be at least one resin selected from a composite resin, a composite resin of an epoxy resin and a silicone resin, and a BT resin.
[0030]
Curtain coaters, spin coaters, roll coaters, spray coats, screen printing, etc. can be used as a method for applying an uncured resin that is an organic adhesive. The adhesive layer can also be formed by laminating an adhesive sheet. As for the thickness of an adhesive bond layer, 5-50 micrometers is desirable. Since the adhesive layer is easy to handle, it is preferable to pre-cure the adhesive layer.
[0031]
Next, the non-through hole 60 is opened in the insulating base material 56 by laser processing (step (B)). As the laser processing machine, a carbon dioxide laser processing machine, a UV laser processing machine, an excimer laser processing machine, or the like can be used. The pore diameter is preferably 20 to 300 μm. The carbon dioxide laser processing machine is most suitable for industrial use because it has a high processing speed and can be processed at low cost, and is the most desirable laser processing machine for the present invention. Here, when a carbon dioxide laser processing machine is used, a slightly melted resin tends to remain on the surface of the metal layer 58 in the hole 60. Therefore, desmear treatment ensures connection reliability. This is desirable.
[0032]
Subsequently, electrolytic plating is filled in the non-through hole 60 opened by laser processing to form a via hole 62 (step (E)). As electrolytic plating, for example, copper, gold, nickel, and solder plating can be used, and electrolytic copper plating is particularly optimal. In this case, bumps can be formed simultaneously.
[0033]
Electrolytic plating is performed using the metal layer 58 formed on the insulating substrate 56 as a plating lead. Since the metal layer 58 is formed on the entire surface of the insulating base material 56, the current density becomes uniform, and the non-through holes can be filled at a uniform height by electrolytic plating. Here, before the electrolytic plating, the surface of the metal layer 58 in the non-through hole 60 may be activated with an acid or the like. When performing plating, a mask (not shown) is put on the metal layer 58 side so as not to deposit electrolytic plating on the surface side of the metal layer 58 formed on the insulating base material 56, or the same insulating property is used. It is preferable to perform electrolytic plating so that two substrates 56 and metal layers 58 are laminated and adhered so as not to touch the plating solution.
[0034]
After the electrolytic plating, bumps 64 are formed on the surface of the via hole 62 on the side opposite to the metal layer 58 in the step (D). For example, the bump 64 may be formed by screen printing a conductive paste using a metal mask having an opening at a predetermined position, a method of printing a solder paste which is a low melting point metal, a method of performing solder plating, or a molten solder bath. It can form by the method of immersing in.
As the low melting point metal, Pb—Sn solder, Ag—Sn solder, indium solder, or the like can be used.
[0035]
The height of the bump from the insulating base material 56 is preferably 3 to 60 μm. The reason for this is that if the thickness is less than 3 μm, variation in bump height cannot be allowed due to the deformation of the bump, and if it exceeds 60 μm, the resistance value increases, and when the bump is deformed, it spreads in the lateral direction. Cause a short circuit.
[0036]
Finally, as shown in step (E), by peeling the film 52, the surface of the bump 64 protrudes from the adhesive layer 54, thereby completing the external connection substrate 50.
[0037]
Next, the step of stacking the semiconductor chip 30 described above with reference to FIG. 2 and the external connection substrate 50 described above with reference to FIGS. 3 and 4 will be described with reference to FIG.
[0038]
As shown in step (A) of FIG. 5, the external connection substrate 50 and the semiconductor chip 30 are laminated so that the bumps 64 of the external connection substrate 50 and the rewiring layer 46 of the semiconductor chip 30 correspond to each other. They are integrated by heating at 150 to 200 ° C. using a hot press and pressing at 5 to 100 kgf / cm 2, preferably 20 to 50 kgf / cm 2. Note that a vacuum hot press is preferably used as the hot press. Thereby, the lamination is completed as shown in the step (B). In the present embodiment, since the completed external connection substrate 50 is attached to the semiconductor chip 30 via an adhesive, no warping occurs. In the first embodiment, since the bumps 64 are protruded from the adhesive layer 54, the bumps 54 are in direct contact with the rewiring layer 46, and there is an advantage that the electrical connection reliability is high.
[0039]
Subsequently, as shown in the step (C), the bump layer 59 is formed by etching the metal layer 58 in a portion corresponding to the through hole 62. Finally, as shown in step (D), solder bumps 68 are formed on the bump lands 59 to complete the semiconductor chip 30. For forming the solder bumps 68, a method of printing solder solder and reflowing is suitable, but a method of mounting solder balls is also possible. The semiconductor chip 30 is mounted on the substrate 90 as described above with reference to FIG. 1 by being placed on the substrate 90 so that the solder bumps 68 correspond to the pads 92 of the substrate 90 and reflowed.
[0040]
Next, a second embodiment of the present invention will be described. In the second embodiment, the formation of the via 44 and the redistribution layer 46 on the semiconductor chip side is the same as in the first embodiment, and therefore only the method for manufacturing the external connection substrate 50 is described with reference to FIG. explain.
[0041]
As shown in step (A) of FIG. 6, an insulating base material 56 having a metal layer 58 formed on one side is used as a starting material. Here, as the insulating substrate 56 to be used, any organic insulating substrate can be used as in the first embodiment. The metal layer 58 formed on the insulating base material 56 can use a copper foil.
[0042]
Next, the non-through hole 60 is opened in the insulating base material 56 by laser processing (step (B)). Subsequently, electrolytic plating is filled in the non-through hole 60 opened by laser processing to form a via hole 62 (step (C)). It is also possible to carry out by partially filling electrolytic plating and filling the remaining portion with conductive paste.
As electrolytic plating, for example, copper, gold, nickel, and solder plating can be used, and electrolytic copper plating is particularly optimal. In this case, bumps can be formed simultaneously.
[0043]
Electrolytic plating is performed using the metal layer 58 formed on the insulating substrate 56 as a plating lead. Since the metal layer 58 is formed on the entire surface of the insulating base material 56, the current density becomes uniform, and the non-through holes can be filled at a uniform height by electrolytic plating. In the second embodiment, the non-through holes are completely filled by electrolytic plating. Here, before the electrolytic plating, the surface of the metal layer 58 in the non-through hole 60 may be activated with an acid or the like.
[0044]
After the electrolytic plating, as shown in step (D), the electrolytic plating (metal 62) raised from the hole 60 can be removed by polishing or the like and planarized. For polishing, a belt sander or buffing can be used.
[0045]
Next, in step (E), a bump 64 is formed on the surface of the via hole 62 opposite to the surface on which the metal layer 58 is formed. For example, the bump 64 may be formed by screen printing a conductive paste using a metal mask having openings at predetermined positions, a method of printing a solder paste that is a low melting point metal, a method of performing solder plating, or a solder melt. It can form by the method of immersing in.
As the low melting point metal, Pb—Sn solder, Ag—Sn solder, indium solder, or the like can be used.
[0046]
The height of the bump from the insulating base material 56 is preferably 3 to 60 μm. The reason for this is that if the thickness is less than 3 μm, variation in bump height cannot be allowed due to the deformation of the bump, and if it exceeds 60 μm, the resistance value increases, and when the bump is deformed, it spreads in the lateral direction. Cause a short circuit.
[0047]
Next, as shown in the step (F), an adhesive layer 54 made of an uncured resin is formed by applying a resin to the entire surface of the insulating substrate 56 on the bump 64 side and drying it. . The adhesive layer 54 can be made of the same material as in the first embodiment.
[0048]
Also in the second embodiment, the semiconductor chip 30 and the substrate 50 for external connection are heated and pressed using a hot press to bond the semiconductor chip 30 and the substrate 50 together. Here, first, by applying pressure, an uncured adhesive (insulating resin) interposed between the bun 64 of the external connection substrate 50 and the rewiring layer 46 of the semiconductor chip 30 is applied. It pushes out to the surroundings and comes into contact with the rewiring layer 46 to establish a connection therebetween. Furthermore, the adhesive layer 54 is cured by being heated simultaneously with the pressurization, and strong bonding is performed between the semiconductor chip 30 and the substrate 50. Note that a vacuum hot press is preferably used as the hot press.
[0049]
Subsequently, a third embodiment of the present invention will be described. In the third embodiment, the formation of the via 44 and the redistribution layer 46 on the semiconductor chip side is the same as in the first embodiment, and therefore only the method for manufacturing the external connection substrate 50 is described with reference to FIG. explain.
[0050]
As shown in step (A) of FIG. 7, a protective film 52 mainly used as a mask for printing a conductive paste is applied to an insulating base material (single-sided copper-clad laminate) 56 on which a metal layer 58 is formed. Affix it. As this protective film 52, for example, a polyethylene terephthalate film (PET) having an adhesive layer on the surface can be used. In step (B), this single-sided copper-clad laminate 56 is laser processed to provide non-through holes 60.
[0051]
In the step (C), a part of the non-through hole 60 is filled with the electrolytic plating 62 so that the plating does not deposit on the metal layer 58. Further, in the step (D), the remaining space is filled with the conductive paste 164. In the third embodiment, the height of the bumps can be made uniform by correcting the variation in the height of the electrolytic plating with the conductive paste 146. In this case, a low melting point metal can be filled instead of the conductive paste.
[0052]
As the conductive paste, a conductive paste made of at least one metal particle selected from silver, copper, gold, nickel, and solder can be used. In addition, as the metal particles, those obtained by coating the surfaces of the metal particles with different metals can be used. Specifically, the metal particle which coat | covered the noble metal chosen from gold | metal | money and silver on the surface of a copper particle can be used.
[0053]
As the conductive paste, an organic conductive paste in which a thermosetting resin such as an epoxy resin or a phenol resin or a thermoplastic resin such as polyphenylene sulfide (PPS) is added to metal particles is desirable.
[0054]
The filling rate of non-through holes of electrolytic plating (height of electrolytic plating × 100 / depth of non-through holes) is 50% or more and less than 100% on average, more preferably 55% to 95%. % To 90% is optimal.
[0055]
The conductive paste 146 filled in the opening of the protective film 52 becomes a bump. In step (F), the film 101 is removed to expose the bumps formed of the conductive paste 146, thereby obtaining the external connection substrate 50 of the third embodiment.
[0056]
The bump made of the conductive paste is preferably semi-cured. The conductive paste is hard even in a semi-cured state, and can penetrate the organic adhesive layer softened during hot pressing. In addition, the contact area is increased by deformation at the time of pressing, so that the conduction resistance can be lowered and the variation in bump height can be corrected.
[0057]
In the above-described embodiment, the hole for forming the via hole is formed by using laser processing, but it is also possible to make a hole by a mechanical method such as drilling or punching.
[0058]
In addition, the external connection substrate of the present invention is subjected to various processing treatments generally performed on printed wiring boards, for example, formation of solder resist on the surface, nickel / gold plating or soldering treatment on the surface conductor circuit , Drilling, cavity processing, through-hole plating, and the like can be performed.
[0059]
Furthermore, in the second and third embodiments, when the external connection substrate is manufactured, the non-through hole of the insulating substrate is formed by laser processing, but it is necessary to drill the adhesive layer by laser processing. There is no need to drill the insulating base material and the adhesive layer simultaneously by laser processing. That is, after the insulating substrate is drilled by laser processing, an adhesive layer can be formed on the substrate for external connection or the substrate having a conductor circuit. For this reason, the desmear process after drilling can be performed before the formation of the adhesive layer, and the adhesive layer is not eroded by the desmear process.
[0060]
In the second and third embodiments, when filling the non-through hole with electrolytic plating, the non-through hole is formed in the insulating substrate by laser processing, and after the electrolytic plating is filled, the external connection substrate or the conductor circuit is formed. Since the adhesive layer can be formed on the substrate, the electrolytic plating solution and the adhesive layer do not come into contact with each other. Therefore, the adhesive layer is not eroded by the plating solution.
[0061]
Since the adhesive layer is uncured until the final process of hot pressing, it tends to deteriorate with desmear treatment or plating solution, but in the second and third embodiments, the occurrence of such a problem is prevented, It has the feature that a highly reliable substrate can be easily formed. For this reason, the reliability of the adhesive layer 54 is excellent.
Further, in the external connection substrates of the second and third embodiments, the non-through holes of the insulating base material are filled with electrolytic plating to form via holes, and the conductor circuit of the insulating base material is formed. On the surface of the via hole on the opposite side of the surface, a conductive conductor or a low melting point metal is used to form a protruding conductor, so that the conductive paste or low melting point metal deforms during hot pressing, resulting in variations in electrolytic plating height. Thus, a multilayer printed wiring board having excellent connection reliability by preventing connection failure can be obtained.
[0062]
In the above-described embodiment, since the external connection substrate 50 and the via on the semiconductor chip are manufactured separately, the production efficiency can be improved. In particular, the external connection substrate 50 can be manufactured inexpensively because a large single-sided substrate can be used. Further, since the through hole is formed by electrolytic plating, a high through hole can be formed in a short time.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor chip according to a first embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.
FIG. 3 is a manufacturing process diagram of the semiconductor chip according to the first embodiment;
FIG. 4 is a manufacturing process diagram of the external connection substrate according to the first embodiment;
FIG. 5 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.
FIG. 6 is a manufacturing process diagram of an external connection substrate of a semiconductor chip according to a second embodiment of the present invention.
FIG. 7 is a manufacturing process diagram of an external connection substrate of a semiconductor chip according to a third embodiment of the present invention.
FIG. 8 is a cross-sectional view of a conventional semiconductor chip.
[Explanation of symbols]
30 Semiconductor chip 32 Aluminum electrode pad 34 Passivation film 38 Nickel plating layer 40 Composite plating layer 44 Via 46 Redistribution layer 50 External connection substrate 52 Film 54 Adhesive layer 56 Insulating base material 58 Metal layer 60 Non-through hole 62 Through hole 64 Bump (protruding conductor)

Claims (5)

A semiconductor chip to which an external connection substrate is attached via an adhesive,
In the semiconductor chip, an insulating layer on the electrode pad side and a via connected to the electrode pad formed in the insulating layer are formed,
A via hole, a protruding conductor connected to the via side at one end of the via hole, and a bump for external connection at the other end of the via hole are formed on the external connection substrate. A semiconductor chip characterized by the following. The electrode pad is a zincate-treated aluminum electrode pad, and the via made of copper plating is formed on the electrode pad via a composite plating layer of nickel and copper. 1. The semiconductor chip according to 1. A method for producing a semiconductor chip, comprising at least the following steps (1) to (5).
(1) A step of forming a non-through hole reaching the metal layer by laser processing on an insulating base material having a metal layer formed on one surface;
(2) A step of filling the non-through hole formed in (1) with electrolytic plating to form a via hole;
(3) A step of forming a protruding conductor made of a conductive paste or a low melting point metal on the surface of the via hole on the opposite side of the metal layer to form an external connection substrate.
(4) forming an insulating layer on the electrode pad side and a via and a redistribution layer of the insulating layer connected to the electrode pad on the semiconductor chip;
(5) A step of attaching the external connection substrate to the semiconductor chip with an adhesive, and connecting the via hole of the external connection substrate and the rewiring layer of the semiconductor chip via the protruding conductor. A semiconductor chip manufacturing method including at least the following steps (1) to (6).
(1) A step of forming a non-through hole reaching the metal layer by laser processing on an insulating substrate having a metal layer formed on one surface and an adhesive layer and a film stuck on the other surface;
(2) A step of filling the non-through hole formed in (1) with electrolytic plating to form a via hole;
(3) A step of forming a protruding conductor made of a conductive paste or a low melting point metal on the surface of the via hole on the opposite side of the metal layer to form an external connection substrate.
(4) peeling the film of the substrate for external connection and exposing the protruding conductor from the adhesive layer;
(5) forming an insulating layer on the electrode pad side and a via and a redistribution layer of the insulating layer connected to the electrode pad on the semiconductor chip;
(6) A step of attaching the external connection substrate to the semiconductor chip with the adhesive, and connecting the via hole of the external connection substrate and the rewiring layer of the semiconductor chip via the protruding conductor. A semiconductor chip manufacturing method including at least the following steps (1) to (6).
(1) A step of forming a non-through hole reaching the metal layer by laser processing on an insulating base material having a metal layer formed on one surface;
(2) A step of filling the non-through hole formed in (1) with electrolytic plating to form a via hole;
(3) A step of forming a protruding conductor made of a conductive paste or a low melting point metal on the surface of the via hole on the opposite side of the metal layer to form an external connection substrate.
(4) A step of applying an adhesive to the opposite side of the metal layer of the external connection substrate.
(5) forming an insulating layer on the electrode pad side and a via and a redistribution layer of the insulating layer connected to the electrode pad on the semiconductor chip;
(6) A step of attaching the external connection substrate to the semiconductor chip with the adhesive, and connecting the via hole of the external connection substrate and the rewiring layer of the semiconductor chip via the protruding conductor.

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