JP3963636B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device formed by a multilayer wiring process and having a fuse relief function in the process.
[0002]
[Prior art]
Until now, we do not know the progress of high integration and high performance of semiconductor integrated circuit devices, and today, a system LSI (hereinafter referred to as “memory macro”) and a large capacity memory core are combined. Mass production of simply referred to as system LSIs is in full swing.
[0003]
In order to realize this system LSI, a multilayer wiring process of three or more layers is generally applied. However, it is applied in order to maximize the features of each system LSI in consideration of cost, performance, etc. Even if the miniaturization process rule is the same, the number of wiring layers used differs depending on the product.
[0004]
The problem here is the fuse formation layer of the memory macro mounted on the system LSI as described above. This memory macro is used for switching the connection by disconnecting the internal wiring for the purpose of replacing the defective memory cell with a redundant memory cell or for adjusting the voltage value generated in the internal power supply circuit. Fuse technology is widely adopted.
[0005]
When cutting these fuses with a laser trimmer or the like, the fuse to be cut is likely to be cut near the surface of the chip and needs to be formed with the uppermost wiring layer. Even if the miniaturization process rule is the same, the number of wiring layers used differs depending on the product, so that the fuse formation layer of the memory macro needs to be matched with the uppermost wiring layer of each product.
[0006]
FIG. 16 shows a cross-sectional structure of a fuse portion in a conventional memory macro in which a fuse is formed in a third wiring layer (hereinafter referred to as M3). This memory macro is applied to a product having M3 as the uppermost layer wiring.
[0007]
Both ends of the fuse 3F formed in M3 are connected to a second wiring layer (hereinafter referred to as M2) via a third wiring layer-second wiring interlayer contact (hereinafter referred to as V2), respectively. , V2 has one end connected to a first internal circuit node formed of M3 and the other end connected to a second internal circuit node formed of M3.
[0008]
FIG. 17 shows a cross-sectional structure of a fuse portion in a conventional memory macro in which a fuse is formed in a fourth wiring layer (hereinafter referred to as M4). This memory macro is applied to a product having M4 as the uppermost layer wiring. In this case, the memory macro itself is completed with the wiring layers up to M3, but the layer in which the fuse (hatched portion) is formed is M4 and is adapted to the uppermost layer wiring of the product.
[0009]
Both ends of the fuse 4F formed in M4 are respectively connected to M3 via a fourth wiring layer-third wiring interlayer contact (hereinafter referred to as V3), and further connected to M2 via V2. Again through V2, one end is connected to a first internal circuit node formed of M3 and the other end is connected to a second internal circuit node formed of M3.
[0010]
As shown in FIGS. 16 and 17, a laser trimmer or the like is formed by combining a fuse forming layer with the uppermost layer wiring of each system LSI product, that is, by forming a fuse with the wiring layer closest to the chip surface. This makes it easier to cut the fuse.
[0011]
[Problems to be solved by the invention]
However, in the conventional semiconductor integrated circuit device as described above, even if the memory macro mounted in each system LSI product has the same electrical specifications, the uppermost wiring layer of each product It is necessary to prepare a memory macro having a fuse formation layer corresponding to each LSI product individually.
[0012]
For this reason, the number of types of memory macros corresponding to each of the system LSI products increases, thereby increasing the number of man-hours for design and verification and complicating the management of the types of memory macros.
[0013]
The present invention solves the above-mentioned conventional problems, and in the case of a system LSI product in which memory macros of electrically identical specifications are mounted, no matter how many all the wiring layers are, the fuse forming layer is Memory macros can be configured appropriately for all the number of wiring layers, increase in the number of types of memory macros is suppressed, man-hours for designing and verifying LSI products are increased, and management of memory macro types is complicated A semiconductor integrated circuit device capable of preventing the above is provided.
[0014]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device comprising a plurality of wiring layers formed by a multi-layer wiring process, and having a fuse relief function in the process. Providing a plurality of hierarchical fuses composed of a plurality of fuses formed in different wiring layers, wherein the plurality of hierarchical fuses are respectively provided between the first internal circuit node and the second internal circuit node. A specific fuse is selectively connected to the first internal circuit node and the second internal circuit node from a plurality of fuses formed in different wiring layers.
[0015]
As described above, a fuse formation layer can always be present at the uppermost layer of all the wiring layers regardless of the total number of wiring layers of the LSI product , and each includes different wiring layers according to the fuse cutting information. A fuse that is effective in a circuit can be selected from a plurality of fuses, and even if a fuse in a non-selected state is damaged, it can be prevented from affecting the circuit .
[0016]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor integrated circuit device according to claim 1 of the present invention is a semiconductor integrated circuit device comprising a plurality of wiring layers formed by a multilayer wiring process, and having a fuse relief function in the process, wherein the plurality of wiring layers Provided with a plurality of hierarchical fuses formed of a plurality of fuses formed in different wiring layers, wherein the plurality of hierarchical fuses are provided between the first internal circuit node and the second internal circuit node, respectively. Only a specific fuse is selectively connected from the plurality of fuses formed in the layer to the first internal circuit node and the second internal circuit node.
[0017]
According to this configuration, regardless of the total number of wiring layers of an LSI product, a fuse forming layer always exists at the top layer of all wiring layers, and a plurality of wiring layers each having a different wiring layer are determined according to fuse cutting information. A fuse that is effective in a circuit can be selected from among the fuses in the circuit, and even if a fuse in a non-selected state is damaged, the circuit is not affected at all .
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device in which the plurality of hierarchical fuses according to the first aspect are arranged so as not to be displaced between different wiring layers.
[0018]
According to this configuration, it is possible to arrange a plurality of fuses without increasing the area of the fuse forming portion formed of a single wiring layer as in the prior art.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device having a configuration in which the plurality of hierarchical fuses according to the first aspect are arranged in a state where they are stacked in different steps between different wiring layers.
[0019]
According to this configuration, damage to the lower fuse that occurs when the fuse formed in the uppermost wiring layer is cut by a laser trimmer or the like is eliminated.
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device having a configuration in which the plurality of hierarchical fuses according to the first aspect are arranged in a staggered manner in different positions between different wiring layers.
[0020]
According to this configuration, it is possible to eliminate damage to the lower layer fuse that occurs when the fuse formed in the uppermost wiring layer is cut by a laser trimmer or the like, and all of the multiple fuses constituting one hierarchical fuse are horizontal. The layout is shifted in the direction, facilitating the connection layout to each fuse terminal and internal circuit node.
[0023]
According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit device, wherein one end of the plurality of fuses formed in the different wiring layers according to the second to fourth aspects is selectively used as a first internal circuit node. A first fuse selection circuit for connection is provided.
[0024]
According to this configuration, one specific terminal is selected from one terminal group of a plurality of fuses each having a different wiring layer, and the one terminal is electrically connected to the first internal circuit node.
[0025]
A semiconductor integrated circuit device according to claim 6 is a second circuit for selectively connecting the other end of the plurality of fuses formed in the different wiring layers according to claim 5 to the second internal circuit node. The fuse selection circuit is provided.
[0026]
According to this configuration, one specific terminal is selected from the other terminal group of the plurality of fuses each formed of a different wiring layer, and the one terminal is electrically connected to the second internal circuit node.
[0027]
The semiconductor integrated circuit device according to claim 7, comprising a logic signal generation circuit for generating a logic signal for controlling the selective connection of the first or and second fuse selection circuit according to claim 5 or claim 6 configuration And
[0028]
According to this configuration, the fuse selection circuit is controlled by the logic signal from the logic signal generation circuit.
According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a control signal generating circuit for generating a control signal for controlling generation of a logic signal from the logic signal generating circuit according to the seventh aspect .
[0029]
According to this configuration, the logic signal generation circuit is controlled by the control signal from the control signal generation circuit.
A semiconductor integrated circuit device according to a ninth aspect is configured such that the control signal from the control signal generating circuit according to the eighth aspect is switched by a mask application step of the manufacturing process.
[0030]
According to this configuration, the logic of the control signal generated from the control signal generation circuit is determined by the mask application process of the manufacturing process.
According to a tenth aspect of the present invention, there is provided the semiconductor integrated circuit device according to the ninth aspect , wherein the control signal generating circuit according to the ninth aspect is input with a power-on reset signal generated when the device is powered on, and controlled based on the power-on reset signal. Configure to generate a signal.
[0031]
According to this configuration, the control signal from the control signal generation circuit whose logic is determined by the mask application process of the manufacturing process is automatically generated by powering on the LSI product.
[0032]
Hereinafter, a semiconductor integrated circuit device according to an embodiment of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a block diagram showing an outline of a circuit configuration for selectively connecting hierarchical fuses in the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 1, 1 is a control signal generating circuit to which a power-on reset signal POR is inputted, 2 is a control signal generated from the control signal generating circuit 1, 3 is a logic signal generating circuit controlled by the control signal 2, and 4 is The logic signal 5 generated from the logic signal generating circuit 3 is a first hierarchical fuse composed of a plurality of fuses each having a different wiring layer, 6L is a terminal group of the first hierarchical fuse 5, and 6R is a first terminal fuse. The other terminal group 7L of one hierarchical fuse 5 is installed between the internal circuit node (11) and one terminal group 6L of the first hierarchical fuse 5, and is a first fuse selection circuit controlled by a logic signal 4. (L) and 7R are first fuse selection circuits (R) that are installed between the internal circuit node (21) and the other terminal group 6R of the first hierarchical fuse 5 and controlled by the logic signal 4.
[0033]
The first hierarchy fuse 5 and the first fuse selection circuit (L) 7L and the first fuse selection circuit (R) 7R respectively arranged on the left and right of the first hierarchy fuse 5 are internal circuit nodes ( 11) and the internal circuit node (21) are arranged in a straight line, and similarly, in parallel therewith, a second hierarchical fuse, a second fuse selection circuit (L), and a second fuse selection circuit (R) is arranged in a straight line between the internal circuit node (12) and the internal circuit node (22).
[0034]
Similarly, in parallel with this, the nth hierarchical fuse, the nth fuse selection circuit (L), and the nth fuse selection circuit (R) are connected to the internal circuit node (1n) and the internal circuit node (2n). ) In a straight line.
[0035]
The plurality of fuse selection circuits (L) and fuse selection circuits (R) are all controlled by a common logic signal 4.
FIG. 2 is a block diagram showing an outline of a circuit configuration for selectively connecting hierarchical fuses in the semiconductor integrated circuit device according to the second embodiment of the present invention. The difference from FIG. 1 is that the fuse selection circuit (L) is removed and the circuit is simplified, and one terminal group 6L of the hierarchical fuse is physically and electrically connected to the internal circuit node 11. It is configured. Otherwise, the configuration is the same as in FIG.
[0036]
FIGS. 3 to 5 are diagrams schematically showing an overlapping structure of hierarchical fuses in the semiconductor integrated circuit devices according to the first and second embodiments of the present invention.
The schematic diagram of FIG. 3 shows a case where, for example, a plurality of wiring layer fuses constituting one hierarchical fuse of the first to third hierarchical fuses are arranged in a state where there is no positional displacement in the horizontal direction hierarchically. ing.
[0037]
In the schematic diagram of FIG. 4, for example, a plurality of wiring layer fuses constituting one hierarchical fuse of the first to third hierarchical fuses are arranged in a state where the positions in the horizontal direction are shifted in a layered manner. Shows the case.
[0038]
In the schematic diagram of FIG. 5, for example, a plurality of wiring layer fuses constituting one hierarchical fuse of the first to third hierarchical fuses are arranged in a state in which the horizontal position is shifted in a hierarchically stacked manner. Shows the case.
[0039]
As shown in FIGS. 3 to 5 above, the hierarchical fuse may have any configuration.
6 to 8 are schematic diagrams showing the concept of hierarchical fuse selection switching in the semiconductor integrated circuit device according to the first embodiment of the present invention. The memory macro in this case can be mounted on any of the system LSI whose uppermost layer wiring is the fourth layer, the system LSI whose uppermost layer wiring is the fifth layer, and the system LSI whose uppermost layer wiring is the sixth layer. It is.
[0040]
The schematic diagram of FIG. 6 shows the concept of hierarchical fuse selection switching when the memory macro is mounted on a system LSI having the sixth layer as the uppermost layer wiring. In this case, in the hierarchical fuse portion, there are three fuses of the fourth layer wiring fuse, the fifth layer wiring fuse, and the sixth layer wiring fuse, but the fuses arranged on the left and right of the hierarchical fuse portion including these fuses. The selection circuit (L) and the fuse selection circuit (R) select both terminals of the sixth-layer wiring fuse, which is the uppermost-layer wiring fuse, so that the internal circuit node (1) has the fuse selection circuit (L), It is electrically connected to the internal circuit node (2) through the sixth layer wiring fuse and the fuse selection circuit (R) in this order.
[0041]
As a result, only the sixth-layer wiring fuse, which is the uppermost-layer wiring fuse, is electrically effective as a fuse, and the fourth-layer wiring fuse and the fifth-layer wiring fuse have no meaning as a fuse. Become.
[0042]
The schematic diagram of FIG. 7 shows the concept of hierarchical fuse selection switching when the memory macro is mounted on a system LSI having the fifth layer as the uppermost layer wiring. In this case, there are two fuses, the fourth layer wiring fuse and the fifth layer wiring fuse, in the hierarchical fuse portion. The fuse selection circuits (L) disposed on the left and right of the hierarchical fuse portion including these fuses, The fuse selection circuit (R) selects both terminals of the fifth-layer wiring fuse, which is the uppermost-layer wiring fuse, so that the internal circuit node (1) has the fuse selection circuit (L), the fifth-layer wiring fuse, It is electrically connected to the internal circuit node (2) through the fuse selection circuit (R) in order.
[0043]
Thus, only the fifth-layer wiring fuse, which is the uppermost-layer wiring fuse, is electrically effective as a fuse, and the fourth-layer wiring fuse does not make sense as a fuse.
[0044]
The schematic diagram of FIG. 8 shows the concept of hierarchical fuse selection switching when the memory macro is mounted on a system LSI having the fourth layer as the uppermost layer wiring. In this case, the hierarchical fuse portion has only one fuse that is the fourth-layer wiring fuse, and the fuse selection circuit (L) and the fuse selection circuit (R) arranged on the left and right of the hierarchical fuse portion, respectively. The internal circuit node (1) selects the fuse selection circuit (L), the fourth layer wiring fuse, and the fuse selection circuit (R) by selecting both terminals of the fourth layer wiring fuse, which is the uppermost layer wiring fuse. Through the order, they are electrically connected to the internal circuit node (2).
[0045]
As a result, the fourth-layer wiring fuse is electrically effective.
FIG. 9 is a block diagram showing a hierarchical fuse selection switching configuration in the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 9, Tr4L, Tr4R, Tr5L, Tr5R, Tr6L, and Tr6R are NchMOS transistors, and the sources of Tr4L, Tr5L, and Tr6L are commonly connected to the internal circuit node (1), and the drains are sequentially connected to the fourth layer. It is connected to one end of the wiring fuse, one end of the fifth layer wiring fuse, and one end of the sixth layer wiring fuse.
[0046]
The sources of Tr4R, Tr5R, and Tr6R are commonly connected to the internal circuit node (2), and the drains are sequentially connected to the other end of the fourth-layer wiring fuse, the other end of the fifth-layer wiring fuse, and the sixth-layer wiring fuse, respectively. Is connected to the other end.
[0047]
Further, the gates of Tr4L and Tr4R are connected in common to the logic signal O1 from the logic signal generation circuit 3, and the gates of Tr5L and Tr5R are connected in common to the logic signal O2 from the logic signal generation circuit 3, and Tr6L and Tr6R The gates are commonly connected to the logic signal O3 from the logic signal generation circuit 3.
[0048]
The logic signal generation circuit 3 is composed of NAND elements and inverter elements, and receives four control signals A, / A, B, / B, and three logic signals O1, O2 based on these control signals. , O3 is output.
[0049]
FIG. 10 is an operation function table of the logic signal generation circuit 3 shown in FIG. 9 (the logic signal generation circuit 3 is a common configuration in the first and second embodiments). FIG. 10 shows that only one signal among the three logic signals O1, O2, and O3 output from the logic signal generation circuit 3 is “H”. Note that the fuse selection circuit and the logic signal generation circuit shown in FIG. 9 are only one configuration example. For example, a PchMOS transistor may be used for the configuration of the fuse selection circuit. Needless to say, the operation function table in FIG. 3 and FIG.
[0050]
FIG. 11 is a circuit block diagram showing the configuration of the control signal generation circuit 1 (the control signal generation circuit 1 is a configuration common to the first and second embodiments) in the semiconductor integrated circuit device of the present invention. In FIG. 11, SW_A and SW_B are both switches that are determined to be ON or OFF in the mask application process of the manufacturing process. The switch SW_A is a sixth wiring layer-fifth wiring interlayer contact (hereinafter referred to as V5). ) And the mask of the sixth wiring layer (hereinafter referred to as M6) are applied, and SW_B is a fifth wiring layer-fourth wiring interlayer contact (hereinafter referred to as V4). ) And the mask of the fifth wiring layer (hereinafter referred to as M5) are applied, and the switch is turned on.
[0051]
That is, in the manufacturing process in which the mask application is advanced in the order of V4, M5, V5, and M6 after M4, SW_A and SW_B are both in the OFF state in the product having the M4 process as the final process of the wiring layer. SW_A is in the OFF state, SW_B is in the ON state in the product that is the final process of the wiring layer, and SW_A and SW_B are both in the ON state in the product that has the M6 process as the final process of the wiring layer.
[0052]
The control signal generation circuit 1 is supplied with a power-on reset signal POR. When the power is turned on, the logic of the control signals A, / A, B, and / B that are output signals of the control signal generation circuit 1 Is determined.
[0053]
FIG. 12 is an operation function table of the control signal generation circuit 1 shown in FIG. It shows that the logic of the control signals A, / A, B, and / B changes depending on the ON / OFF state of SW_A and SW_B.
[0054]
FIG. 13 to FIG. 15 show how the states of SW_A and SW_B are switched in the mask application process of the manufacturing process, with cross-sectional structures of the respective switches. FIG. 13 shows a state where up to M4 is formed, and both SW_A and SW_B are OFF. FIG. 14 shows a state where up to M5 is formed, where SW_A is OFF and SW_B is ON. FIG. 15 shows a state where up to M6 is formed, and both SW_A and SW_B are ON.
[0055]
In each of the above embodiments, the fuse formation layer in the memory macro has been described. However, the present invention is not limited to only the fuse formation layer in the memory macro, and the semiconductor integrated circuit device to which the multilayer wiring process is applied. Applicable to all.
[0056]
【The invention's effect】
As described above, according to the first aspect of the present invention, a fuse formation layer can always be present at the uppermost layer of all the wiring layers, regardless of the total number of wiring layers of the LSI product . According to the cutting information, it is possible to select a fuse that is effective in terms of a circuit from among a plurality of fuses each having a different wiring layer, and even if a non-selected fuse is damaged, there is nothing in terms of the circuit. It can be made to have no effect .
[0057]
According to the second aspect of the present invention, a plurality of fuses can be arranged without increasing the area of the fuse forming portion formed of a single wiring layer as in the prior art. According to the third aspect of the invention, it is possible to eliminate damage to the lower layer fuse that occurs when the fuse formed in the uppermost wiring layer is cut by a laser trimmer or the like.
[0058]
According to the invention described in claim 4, it is possible to eliminate damage to the lower layer fuse that occurs when the fuse formed in the uppermost wiring layer is cut by a laser trimmer or the like, and a plurality of fuses constituting one hierarchical fuse All of the fuses are arranged so as to be shifted in the horizontal direction, and the connection layout to each fuse terminal and the internal circuit node can be facilitated.
[0060]
According to the fifth aspect of the present invention, a specific one terminal is selected from one terminal group of a plurality of fuses each having a different wiring layer, and the one terminal is electrically connected to the first internal circuit node. be able to.
[0061]
According to the sixth aspect of the present invention, a specific one terminal is selected from the other terminal group of the plurality of fuses each having a different wiring layer, and the one terminal is electrically connected to the second internal circuit node. be able to.
[0062]
According to the seventh aspect of the invention, the fuse selection circuit can be controlled by the logic signal from the logic signal generation circuit.
According to the eighth aspect of the invention, the logic signal generation circuit can be controlled by the control signal from the control signal generation circuit.
[0063]
According to the ninth aspect of the present invention, the logic of the control signal generated from the control signal generation circuit can be determined by the mask application process of the manufacturing process.
According to the tenth aspect of the present invention, the control signal from the control signal generation circuit whose logic is determined by the mask application process of the manufacturing process can be automatically generated by turning on the power to the LSI product.
[0064]
As described above, in the case of a system LSI product in which memory macros of electrically identical specifications are mounted, the memory macro whose fuse formation layer appropriately corresponds to the number of all wiring layers, regardless of the number of all wiring layers. Thus, the increase in the number of types of memory macros can be suppressed, and the man-hours for designing and verifying LSI products and the complexity of managing the types of memory macros can be prevented.
[Brief description of the drawings]
1 is a block diagram showing a schematic configuration for selectively connecting hierarchical fuses in a semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. 2 is a hierarchical fuse in a semiconductor integrated circuit device according to a second embodiment of the present invention; FIG. 3 is a schematic diagram showing an overlapping configuration of hierarchical fuses in the first and second embodiments.
FIG. 4 is a schematic diagram 2 showing an overlapping configuration of hierarchical fuses in the first and second embodiments.
FIG. 5 is a schematic diagram showing an overlapping configuration of hierarchical fuses in the first and second embodiments.
FIG. 6 is a schematic diagram showing a hierarchical fuse selection switching concept according to the first embodiment;
FIG. 7 is a schematic diagram showing a hierarchical fuse selection switching concept according to the first embodiment;
FIG. 8 is a schematic diagram showing a hierarchical fuse selection switching concept according to the first embodiment;
FIG. 9 is a block diagram showing a hierarchical fuse selection switching configuration according to the first embodiment. FIG. 10 is an explanatory diagram of an operation function of the logic signal generation circuit according to the first and second embodiments. FIG. 12 is a block diagram showing a configuration of a control signal generating circuit in 1 and 2. FIG. 12 is an explanatory diagram of an operation function of the control signal generating circuit in the first and second embodiments. FIG. FIG. 1 is an explanatory diagram of state switching of a switch unit in a generation circuit.
FIG. 14 is an explanatory diagram of state switching of a switch unit in the control signal generation circuit according to the first and second embodiments.
FIG. 15 is an explanatory diagram of state switching of a switch unit in the control signal generation circuit according to the first and second embodiments.
FIG. 16 is a cross-sectional structure diagram of a fuse portion by a third wiring layer in a conventional semiconductor integrated circuit device. FIG. 17 is a cross-sectional structure diagram of a fuse portion by a fourth wiring layer in a conventional semiconductor integrated circuit device.
DESCRIPTION OF SYMBOLS 1 Control signal generation circuit 2 Control signal 3 Logic signal generation circuit 4 Logic signal 5 Hierarchical fuse 6L Hierarchical fuse's one terminal group 6R Hierarchical fuse's other terminal group 7L Fuse selection circuit (L)
7R Fuse selection circuit (R)

Claims (10)

A semiconductor integrated circuit device comprising a plurality of wiring layers formed in a multilayer wiring process and having a fuse relief function in the process, wherein the plurality of fuses are formed in different wiring layers of the plurality of wiring layers. The plurality of hierarchical fuses are provided between the first internal circuit node and the second internal circuit node, respectively, and only a specific fuse is selected from the multiple fuses formed in different wiring layers. A semiconductor integrated circuit device configured to be selectively connected to the first internal circuit node and the second internal circuit node.   2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of hierarchical fuses are arranged so as to overlap each other with no positional deviation between different wiring layers.   The semiconductor integrated circuit device according to claim 1, wherein the plurality of hierarchical fuses are arranged in a state of being shifted in different layers between different wiring layers.   The semiconductor integrated circuit device according to claim 1, wherein the plurality of hierarchical fuses are arranged in a staggered manner in different positions between different wiring layers.   3. A first fuse selection circuit for selectively connecting one end of a plurality of fuses formed in different wiring layers to a first internal circuit node. 5. The semiconductor integrated circuit device according to any one of 4 above.   6. A second fuse selection circuit for selectively connecting the other end of a plurality of fuses formed in different wiring layers to a second internal circuit node is provided. Semiconductor integrated circuit device.   7. The semiconductor integrated circuit device according to claim 5, further comprising a logic signal generation circuit that generates a logic signal for controlling selection connection of the first or second fuse selection circuit.   8. The semiconductor integrated circuit device according to claim 7, further comprising a control signal generation circuit that generates a control signal for controlling generation of a logic signal from the logic signal generation circuit.   9. The semiconductor integrated circuit device according to claim 8, wherein a control signal from the control signal generation circuit is switched by a mask application process of a manufacturing process.   The control signal generation circuit is configured to receive a power-on reset signal generated when the apparatus is turned on and generate a control signal based on the power-on reset signal. Semiconductor integrated circuit device.

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