JP3965595B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, a signal generated in a global area when a CAS operation is terminated by a precharge interrupt command during a CAS access. The present invention relates to a semiconductor memory device in which a signal line going to the bank side is reduced by preventing the predecoder operation and unnecessary power consumption is reduced.
[0002]
[Prior art]
FIG. 1 is a block diagram of a conventional semiconductor memory device at an interrupt-related portion when a precharge signal is generated.
As shown in the figure, a command buffer unit 1 for inputting a TTL level rasbar (rasb), a casbar (casb), and a write enable bar signal (web) to buffer the CMOS level, and a TTL level bank address signal (bad). <I>) is buffered at the CMOS level, and a bank enable buffer signal generator 2 for generating a cass enable bank signal (casen_ba <i>) for notifying a bank in which a cas (CAS) instruction is currently being processed. 3 and the output signal (rasx, casz, wex) of the command buffer unit 1 are input and combined, and the bank of the precharge instruction input by receiving the output signal (bat <i>) of the bank address buffer unit 2 And select the cascading enable bank signal (casen). If it matches with the bank of the input precharge instruction (ba <i>), the precharge interrupt signal generator 4 generates a precharge interrupt signal (pcgtterm) in the corresponding bank (5_n). .
[0003]
In the conventional precharge interrupt method, the output signals (rasx, casz, wex) of the command buffer unit 1 are combined by the precharge interrupt signal generation unit 4, and the output signal (bat <i>) of the bank address buffer unit 2 is combined. In response to this, the bank of the precharge command to which the currently input bank address is input is selected.
[0004]
Then, a cass enable bank signal (casen_ba <i>) for notifying which bank the cas (CAS) operation currently in progress is made is input, and the bank of the precharge command and the cass enable bank signal ( casen_ba <i>), if they match, a precharge interrupt signal (pcgtterm) is generated, and the column selection signal (at read) enabled in the corresponding bank or the core (core) at the global input / output line The signal (at the time of writing) transmitted to the data bus line is disabled by the corresponding clock (clock).
[0005]
However, in the conventional semiconductor memory device having the above-described configuration, it is difficult for the precharge interrupt signal (pcgtterm) to cover all the banks at one time. Signals are generated locally one by one. As a result, the conventional semiconductor memory device has many signal lines going from the global area to the local area, and the interrupted signals are almost in the final stage of cell access, which is unnecessary. There is a problem that a lot of power is consumed.
[0006]
[Technical Problem to be Solved by the Invention]
Therefore, the present invention has been made to solve the above-described problems. The object of the present invention is to select a column locally when a precharge interrupt is input during a CAS access. Rather than interrupting the signal (column selection signal) or data on the data bus line, the master clock latch (master clock latch) is used in the buffer, and the delay time until the interrupt internal instruction is enabled is reduced to the predecoder strobe signal. An object of the present invention is to provide a semiconductor memory device in which signal lines going to the bank side are reduced by interrupting to prevent unnecessary operations of the predecoder and to reduce power consumption.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor memory device according to the present invention includes a command buffer unit for inputting a TTL level rasb, casb, and write enable bar (web) signal and buffering it at a CMOS level. A bank address buffer unit for buffering a TTL level bank address signal at a CMOS level, a cass enable bank signal generating means for generating a cass enable bank signal for informing a bank in which cass (CAS) is being advanced, and the command buffer A precharge command is detected by combining the output signals of the unit, the output signal of the bank address buffer unit is compared with the already-input cass enable bank signal, and the enabled bank and the detected precharge command are compared. Bank selected by If they match, generates an enable signal, and the precharge interrupt signal generating means for outputting a precharge interrupt signal after the enable signal is latched in the master clock generated, operate by the pre-charge interrupt signal is controlled, external Kas Or predecoder strobe signal generating means for generating a strobe signal for operating a predecoder for selecting a bank according to an internal cascading , wherein the precharge interrupt signal generating means outputs the output signal of the command buffer unit. The instruction decoding unit to be coded, the output signal of the bank address buffer unit and the cascade enable bank signal are compared, and whether the enabled bank matches the bank selected by the detected precharge instruction A bank decoding unit that outputs a signal indicating whether or not, an enable signal generation unit that generates an enable signal using an output signal of the bank decoding unit, based on an output signal of the instruction decoding unit, and the enable signal And a latch unit that outputs a precharge interrupt signal after being latched by the master clock .
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Next, a specific example of an embodiment of a semiconductor memory device according to the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof is omitted .
[0009]
FIG. 2 is a block diagram of a semiconductor memory device according to the present invention .
[0010]
As shown in the figure, a command buffer unit 10 for inputting a TTL level rasbar (rasb), a casbar (casb), and a write enable bar signal (web) to buffer the CMOS level, and a TTL level bank address signal (bad). <I>) is buffered to the CMOS level, the bank address buffer unit 20 is buffered to the TTL level clock signal (clk) to the CMOS level, and the cas A bank address buffer unit 20 detects a precharge command by combining a cass enable bank signal generator 30 that generates a enable bank signal (casen_ba <i>) and an output signal (rase, casd, wee) of the command buffer unit 10. Output signal (b <I>) as compared with previously input input Kas enable bank signal (casen_ba <i>), the enable signal if a match is selected bank by a precharge command is detected to bank is enabled The operation is controlled by a precharge interrupt signal generator 50 that outputs a precharge interrupt signal after latching the generated enable signal to the master clock and a precharge interrupt signal (pcgtarm). (Cas) and the internal cas (cas), a predecoder strobe signal generator 70 for generating a strobe signal for operating a predecoder for selecting a bank, and a strobe signal (s) output from the predecoder strobe signal generator 70 Type b <n>), respectively, and a predecoder section 80 for selecting a corresponding bank (n).
[0011]
FIG. 3 is a block diagram showing a configuration of precharge interrupt signal generator 50 shown in FIG.
As shown in the figure, the precharge interrupt signal generator 50 of the present invention includes an instruction decoding unit 51 for decoding an output signal (rase, casd, wee) of the command buffer unit 10 and an output of the bank address buffer unit. The signal (ba <i>) and the cascade enable bank signal (casen_ba <i>) are compared, and a signal indicating whether the enabled bank and the bank selected by the detected precharge command match each other is output. The n bank decoding units (52_n) and the output signal (pre_pcg) of the instruction decoding unit 51 multiplex the output signals of the n bank decoding units (52_n) to generate an enable signal (pcg_bk). Enable signal generator 53 and enable signal After latched by Pcg_bk) a master clock (master clock), is constituted by a latch 54 for outputting precharge interrupt signal (pcgterm).
[0012]
The core of the present invention is that after buffering to convert external input to CMOS level, pre-charge instruction decoding, and bank address of this instruction, before latching to the internal master clock (master clock), in progress By comparing and checking the banks of CAS operations, it is determined whether or not to perform an interrupt before the strobe signal of the predecoder is enabled by the internal CAS command. The purpose is to control the strobe signal of the predecoder.
[0013]
Now, the semiconductor memory device of the present invention will be described with reference to the block diagram shown in FIG.
The command buffer unit 10, the bank address buffer unit 20, and the clock buffer unit 40 serve only to convert an external input instruction from the TTL level to the CMOS level. The output command (rase, casd, wee) and the bank address (ba <i>) of the command buffer unit 10 are input to the precharge interrupt signal generation unit 50. Here, the output command (rase, casd, wee) of the command buffer unit 10 is combined with the precharge command. The bank address (ba <i>) is compared with the already enabled standby enable signal (casen_ba <i>), and the bank selected by the detected precharge instruction is detected. If they match, a precharge interrupt signal (pcgtterm) is generated.
[0014]
The precharge interrupt signal (pcgtterm) is sent to the predecoder strobe signal generation unit 70 that generates the predecoder strobe signal (stb <n>) to prevent the predecoder strobe signal (stb <n>) from being enabled. To prevent decoding from the original. At this time, it is int_cas of the internal cas (CAS) instruction and ext_cas of the external cas (CAS) instruction that enables the predecoder strobe signal (stb <n>) by the predecoder strobe signal generator 70. Is enabled after the delay of at least five inverters after being latched by the clock, so that the predecoder strobe signal (stb <n>) is output by the precharge interrupt signal (pcgtterm) output immediately after the clock is latched. There is no problem to be controlled.
[0015]
Next, the precharge interrupt signal generator 50 that generates the precharge interrupt signal (pcgtterm) will be described.
As shown in FIG. 3, the bank address is buffered in the same manner as the control signal and the like that were initially buffered (in FIG. 3, a bank address that has been decoded but has not been decoded) However, there is no problem even if the input terminal of the NAND gate is increased.), And casen_ba <i: n> that informs the bank information of the CAS operation that is in progress. Etc. are input and undergo decoding.
[0016]
If the combination of the output commands (rase, casd, wee) output from the command buffer unit 10 is a precharge command, the output signal (pre_pcg) of the command decoding unit 51 is enabled and the enable signal generation unit 53 is enabled. Turn on. That is, the output signal (pre_pcg) of the instruction decoding unit 51 serves as a strobe of the enable signal generation unit 53. Then, the bank address (ba <n>) input at the same time is compared with the cascade enable bank signal (casen_ba <i>). If the enabled bank and the bank selected by the pcg instruction are the same, the corresponding bank The pcg_bn signal is enabled and input to the enable signal generator 53.
[0017]
If the bank address in which the casg operation is being performed and the bank address to which the pcg instruction is input do not match, the enable signal generator 53 is enabled even if the enable signal generator 53 is opened by the output signal (pre_pcg) of the instruction decoder unit 51. The signal (pcg_bk) should continue to be disabled, and if it matches, the enable signal (pcg_blk) should be enabled. After that, the enable signal (pcg_bk) is latched by the internal master clock (master clock) by the latch unit 54, and then the precharge interrupt signal (pcgtam) is output.
[0018]
For reference, in order to match the setup / hold time with the buffer, the buffered signal is usually given a fixed delay and then latched in the clock. The delay must be considered so as to coincide with the time until the enable signal (pcg_bk) reacts after the signal and address are input.
The enable signal (pcgtterm) thus enabled and latched to the clock receives the internal cas (CAS) instruction and interrupts the generation of the predecoder strobe signal (stb) as described above. Input to the generator 70.
[0019]
The present invention is not limited to this embodiment. Various modifications can be made without departing from the spirit of the present invention.
[0020]
【The invention's effect】
As described above, according to the semiconductor memory device of the present invention, the delay time for adjusting the setup / hold time is used, and a precharge interrupt internal command is used during this time. Since this signal is synchronized with the internal clock after the occurrence of the error, the enable time of the interrupt instruction can be advanced to finish the CAS (CAS) operation at the beginning. As a result, the circuit area can be reduced by interrupting a specific time of the CAS path in the global area, and power consumption can be reduced by interrupting unnecessary circuit operations. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor memory device for interrupting in accordance with a conventional precharge command.
FIG. 2 is a block diagram of a semiconductor memory device according to the present invention.
FIG. 3 is a detailed configuration diagram of a precharge interrupt signal generator shown in FIG. 2;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Command buffer part 20 Bank address buffer part 30 Cass enable bank signal generation part 40 Clock buffer part 50 Precharge interrupt signal generation part 51 Instruction decoding part 52_0-52_n Bank_0-Bank_n decoding part 53 Enable signal generation part 54 Latch Unit 60 external debris and internal debris generation unit 70 predecoder strobe signal generation unit 80 predecoder unit 100_0 to 100_n bank

Claims (1)

A command buffer unit for inputting a TTL level rasb, casb, and write enable bar (web) signal and buffering it at a CMOS level;
A bank address buffer unit for buffering a TTL level bank address signal to a CMOS level;
A cass enable bank signal generating means for generating a cass enable bank signal for informing a bank in which cass (CAS) is being advanced;
A precharge command is detected by combining the output signals of the command buffer unit, the output signal of the bank address buffer unit is compared with the already-added cass enable bank signal, and the detected bank and the detected bank are detected. A precharge interrupt signal generating means for generating an enable signal if the banks selected by the precharge instruction match, and outputting the precharge interrupt signal after latching the generated enable signal in the master clock;
Predecoder strobe signal generating means for controlling the operation by the precharge interrupt signal and generating a strobe signal for operating a predecoder for selecting a bank by external or internal debris ,
The precharge interrupt signal generating means comprises: an instruction decoding unit for decoding an output signal of the command buffer unit; an output signal of the bank address buffer unit and the cascade enable bank signal; A bank decoding unit that outputs a signal indicating whether or not the banks selected by the detected precharge command match, and an output signal of the bank decoding unit is used by an output signal of the command decoding unit. A semiconductor memory device comprising: an enable signal generating unit that generates an enable signal; and a latch unit that latches the enable signal with a master clock and then outputs a precharge interrupt signal .

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