JP3968786B2 - IC card and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to an IC card and a semiconductor integrated circuit suitable for use in, for example, a commuter pass used in an automatic ticket gate system.

  Currently, information is magnetically recorded on commuter passes used in automatic ticket gate systems, etc. When a commuter pass is inserted in an automatic ticket gate, a magnetic head is placed on the portion where the magnetic record is made. To read information.

  For this reason, when the commuter pass is stored in the case, the user needs to take it out and insert it into the automatic ticket gate, which is troublesome.

  Therefore, the present applicant has previously proposed a contactless card system. According to this contactless card system, it is possible to exchange information (data communication) and the like in a contactless manner. When this is applied to the automatic ticket gate system as described above, the user can use a commuter pass. It is possible to go in and out of the automatic ticket gate even if it is stored in the case.

  FIG. 15 shows a configuration example of the contactless card system previously proposed by the applicant. This non-contact card system supplies non-contact power to the IC card corresponding to the above-mentioned commuter pass and the IC card using electromagnetic waves as a medium, and performs reading and writing of data and other necessary processing. It consists of a reader / writer.

  The reader / writer is configured as follows. That is, the host computer 91 transmits a predetermined application program to the digital signal processing unit 92 in response to an instruction from another device or system administrator (not shown) or the reader / writer. The operation mode is determined or the received data is read from the digital signal processing unit 92 as described later.

  The digital signal processing unit 92 loads an application program transmitted from the host computer 92 and performs processing according to the program. The digital signal processing unit 92 controls the amplification factor of the amplifier 94 or receives data transmitted from the amplifier 100 in accordance with an instruction from the host computer 92, and performs predetermined processing on the data. The data is transmitted to the host computer 91.

  The carrier generator 93 has one output terminal connected to one end of the loop antenna 97, and the other output terminal connected to the input terminal of the amplifier 94, so as to output a carrier having a predetermined frequency. Yes. The amplifier 94 is a voltage control type amplifier, and its output terminal is connected to the other end of the loop antenna 97 via a resistor 95. As described above, the amplification factor in the amplifier 94 is controlled by the digital signal processing unit 92, so that the carrier signal output from the carrier generator 93 is amplified by the digital signal processing unit 92. By being changed, the amplitude is modulated.

  The capacitor 96 has one end connected to a connection point between the carrier generator 93 and the loop antenna 97, and the other end connected to a connection point between the resistor 95 and the loop antenna 97. Since the loop antenna 97 is equivalent to a coil, the capacitor 96 and the loop antenna 97 constitute a resonance circuit (parallel resonance circuit). The loop antenna 97 is formed as a pattern on a printed board, for example.

  The anode of a detection diode 98 is connected to the connection point between the resistor 95 and the loop antenna 97, and the cathode is connected to the input terminal of the amplifier 100 via a coupling capacitor (coupling capacitor) 99. ing. The output terminal of the amplifier 100 is connected to the digital signal processing unit 92.

  Next, the operation will be described with reference to the flowchart of FIG. In the reader / writer, first, in step S1, a command and write data if necessary are transmitted as an electromagnetic wave, and an unmodulated wave is transmitted for a certain period. That is, first, in the host computer 91, a predetermined application program and write data if necessary are transmitted to the digital signal processing unit 92 in response to an instruction from another system or system administrator. Thereafter, the host computer 91 is activated for the digital signal processing unit 92.

  When the digital signal processing unit 92 receives a program from the host computer 91, it loads the program into a built-in memory (when write data is also received, it is stored). When activated from the host computer 91, processing is performed according to the loaded program. That is, for example, the amplification factor of the amplifier 94 is controlled in accordance with a command for instructing processing to the IC card, a program to be executed by the IC card, other write data, and the like.

  The carrier is input from the carrier generator 93 to the amplifier 94. Therefore, in the amplifier 94, the carrier is amplitude-modulated in accordance with a command, program, and data from the digital signal processing unit 92 and output. Therefore, the carrier generator 93 and the amplifier 94 constitute an amplitude modulator.

  The amplitude-modulated wave output from the amplifier 94 is output via a resistor 95 to a capacitor (resonance capacitor) 96 and a loop antenna 97 that constitute a resonance circuit. The resonance frequency of the resonance circuit composed of the capacitor 96 and the loop antenna 97 is set to the frequency of the carrier output from the carrier generator 93. Therefore, the amplitude-modulated wave output from the amplifier 94 is transmitted from the loop antenna 97. It is radiated efficiently as an electromagnetic field.

  Thereafter, in the reader / writer, the digital signal processing unit 92 controls the amplification factor of the amplifier 94 to be a constant value, whereby the unmodulated wave becomes an electromagnetic field in the same manner as the amplitude-modulated wave described above. It is emitted efficiently.

  In step S2, it is determined whether or not there is a response from the IC card. Here, whether or not there is a response from the IC card is determined as follows. That is, in the IC card, as will be described later, a loop antenna 31 and a capacitor (resonance capacitor) 32 are connected in parallel to form a resonance circuit. Furthermore, a series circuit in which a capacitor 38 and an FET (N-channel FET) 39 are connected in series is connected in parallel to the capacitor 32. Therefore, when the FET 39 is turned on / off, the resonance circuit is connected to the loop antenna 31. And the capacitor 32, or the loop antenna 31, the capacitors 32, and 39, and the resonance frequency (impedance) thereof is changed.

  In the IC card, when responding to the reader / writer, the FET 39 is turned on / off, thereby changing the resonance frequency (impedance) of the resonance circuit. In this case, if the IC card and the reader / writer are at a distance that causes mutual induction between the loop antennas 31 and 97, the reader / writer that emits the electromagnetic field corresponding to the unmodulated wave as described above. The impedance when the loop antenna 97 side is viewed from the points A and B, which are the connection points of the capacitor 96 and the loop antenna 97, changes corresponding to the on / off of the FET 39, and therefore the point A (B) The voltage will also change. The voltage at the point A is detected by the diode 98, the direct current component is cut by the capacitor 99, further amplified by the amplifier 100, and input to the digital signal processing unit 92. The digital signal processing unit 92 makes a determination based on the signal from the amplifier 100.

  If it is determined in step S2 that there is no response from the IC card, that is, if the IC card and the reader / writer are not at a distance that causes mutual induction between the loop antennas 31 and 97, the process returns to step S1, and again The processing from step S1 is repeated. If it is determined in step S2 that there is a response from the IC card, the process proceeds to step S3, where the digital signal processing unit 92 demodulates the output signal of the amplifier 100 as a response obtained as described above, and demodulates the demodulated signal. Necessary processing is performed based on the data, and the processing is terminated.

  Next, the IC card will be described. The IC card is configured as follows. That is, the loop antenna 31 and the capacitor 32 are connected in parallel. Since the loop antenna 31 is equivalent to a coil like the loop antenna 97 described above, the loop antenna 31 and the capacitor 32 constitute a parallel resonance circuit. One of the connection points between the loop antenna 31 and the capacitor 32 is connected to one end of the capacitor 38, and the other is connected to the source of the FET 39. The drain of the FET 39 is connected to the other end of the capacitor 38.

  One end of the resistor 33 and the anode of the diode 83 are connected to a connection point between the loop antenna 31 and the capacitor 32 and a connection point between the capacitor 38. The diode 83 is for rectification and detection, and its cathode is connected to the input terminal of the constant voltage regulator 37.

  Connected to the other end of the resistor 33 are an anode of a diode group 81 in which a plurality of diodes are connected in series in multiple stages, and a cathode of a diode group 82. Both the cathode of the diode group 81 and the anode of the diode group 82 are connected to the source of the FET 39. Note that the source of the FET 39 is grounded.

  One end of the smoothing capacitor 35 is connected to a connection point between the diode 83 and the input terminal of the constant voltage regulator 37, and the other end is grounded. The constant voltage regulator 37 stabilizes the voltage applied to its input terminal to a predetermined constant voltage VDD and outputs it from its output terminal. One end of a bypass capacitor 36 is connected to the output terminal of the constant voltage regulator 37, and the other end is grounded. The constant voltage regulator 37 has a ground terminal, and the ground terminal is grounded.

  One end of the coupling capacitor 40 is connected to a connection point between the diode 83 and the constant voltage regulator 37, and the other end is connected to the input terminal of the amplifier 41. The amplifier 41 amplifies the signal input to the input terminal and outputs the amplified signal from the output terminal. The output terminal is connected to the input terminal of the digital signal processing unit 42. The digital signal processing unit 42 performs predetermined processing corresponding to the signal input from the amplifier 41. The digital signal processing unit 42 has an output terminal, and the output terminal is connected to the gate of the FET 39. Therefore, the FET 39 is turned on / off by the digital signal processing unit 42 in accordance with the voltage applied to its gate.

  Note that the amplifier 41 and the digital signal processing unit 42 are supplied with the voltage VDD output from the constant voltage regulator 37 as a power source. The amplifier 41 and the digital signal processing unit 42 have a ground terminal, and the ground terminal is grounded. Further, the digital signal processing unit 42 includes a nonvolatile memory 43, stores data from the amplifier 41, and turns on / off the FET 39 according to the stored data.

  Next, the operation will be described with reference to the flowchart of FIG. In the IC card, first, in step S11, an electromagnetic wave radiated from the reader / writer is received. That is, when the IC card is brought close to the reader / writer and a distance that causes mutual induction between the loop antennas 31 and 97, the loop antenna 31 includes the electromagnetic field (magnetic flux) radiated from the loop antenna 97. A counter electromotive force is generated in accordance with a change in magnetic flux interlinked there (change in magnetic field). Among the voltages generated in this manner, a voltage in a predetermined frequency band centered on the resonance frequency of the resonance circuit composed of the loop antenna 31 and the capacitor 32 is efficiently passed to the subsequent block.

  The resonance frequency of the resonance circuit composed of the loop antenna 31 and the capacitor 32 is, for example, the frequency of the carrier generated by the carrier generator 93 included in the reader / writer.

  Then, the process proceeds to step S12, in which the voltage VDD is supplied as a power source to the amplifier 41 and the digital signal processing unit 42, which are blocks that require a power source to operate, and a resonance circuit including the loop antenna 31 and the capacitor 32. The signal that passed through is detected.

  In other words, the signal that has passed through the resonance circuit constituted by the loop antenna 31 and the capacitor 32 is rectified through the diode 83, and the ripple is removed through the smoothing capacitor 35. The signal from which the ripple has been removed is supplied to the constant voltage regulator 37, where it is stabilized to a predetermined constant voltage VDD. The voltage VDD is supplied to the amplifier 41 and the digital signal processing unit 42 as a power source.

  As described above, after the power is supplied to the amplifier 41 and the digital signal processing unit 42 and the operation becomes possible, the signal that has passed through the resonance circuit including the loop antenna 31 and the capacitor 32 is a diode. The signal is detected via 83 and supplied to the capacitor 40.

  Then, the process proceeds to step S 13, and commands and data radiated as electromagnetic waves from the reader / writer are output to the digital signal processing unit 42. That is, the capacitor 40 removes a direct current component from the signal detected by the diode 83 and supplies the signal to the amplifier 41. In the amplifier 41, the signal from the capacitor 40 is amplified to a required level and supplied to the digital signal processing unit 42.

  In step S14, the digital signal processing unit 42 interprets a command included in the signal supplied from the amplifier 41, and proceeds to step S15 to determine whether or not the command is a request for writing. If it is determined in step S15 that the command is a request for writing, the process proceeds to step S16, where the data included in the signal supplied from the amplifier 41 is written to the nonvolatile memory 43, and the process proceeds to step S17.

  If it is determined in step S15 that the command does not request writing, step S16 is skipped and the process proceeds to step S17 to determine whether or not the command requests reading. . If it is determined in step S17 that the command is a request for reading, the process proceeds to step S18, a data reading process is performed, and the process proceeds to step S19. That is, in step S18, data stored in the nonvolatile memory 43 is read out, and a voltage is applied to the gate of the FET 39 corresponding to the data, and the process proceeds to step S19.

  Here, the FET 39 is turned on / off according to the voltage applied to its gate (normally in an off state). When the FET 39 is turned on, the loop antenna 31 and the capacitor 32 are turned on. Since the capacitor 38 is connected in parallel to the parallel resonance circuit consisting of the above, the voltage at the point A in the reader / writer changes corresponding to the read data as described above. .

  If it is determined in step S17 that the command does not require reading, the process proceeds to step S19, and processing corresponding to the command, for example, a program included in the signal supplied from the amplifier 41 is executed. The process is performed and the process ends.

  When the IC card is brought extremely close to the reader / writer, a high voltage (excess voltage) is generated in the loop antenna 31. As a result, a large current (excess current) flows through the IC card. It can be destroyed. Therefore, in the IC card, when such a large current is output from the resonance circuit composed of the loop antenna 31 and the capacitor 32, the output voltage of the resonance circuit has a predetermined peak value by bypassing a part thereof. It is made to limit to below the value.

  That is, for example, when a forward voltage or a reverse voltage is applied to the diode 83, the polarity of the current output from the resonance circuit composed of the loop antenna 31 and the coil 32 is referred to as positive polarity or negative polarity, respectively. When a positive current is output from the resonance circuit and the potential difference between the resistor 33 and the diode group 82 exceeds a predetermined value, a bypass current flows through the resistor 33 and the diode group 82. When a negative current is flowing, a bypass current flows through the diode group 81 and the resistor 33 when the potential difference between the diode group 81 and the resistor 33 exceeds a predetermined value.

  Accordingly, each of the diode groups 81 or 82 is composed of, for example, five diodes, and assuming that the voltage drop in each diode when current flows in the forward direction is, for example, 0.7 V, the loop antenna 31 and the capacitor 32 When the potential difference between the connection points is about 3.5 (= 0.7 × 5) V or more, a bypass current flows through the resistor 33 and the diode group 82, or the diode group 81 and the resistor 33, thereby causing a loop antenna. The potential difference between the connection points of 31 and the capacitor 32 is limited to 3.5V or less.

  Therefore, it can be said that the resistor 33 and the diode groups 81 and 82 constitute a protection circuit.

  By the way, since the IC card is carried by the user, it is desirable that the IC card can be configured to be small and inexpensive. As a method for reducing the size of the IC card, for example, it is conceivable that the subsequent stage portion of the resonance circuit formed of the loop antenna 31 and the capacitor 32 is formed of, for example, a one-chip CMOS (C-MOS).

  However, there are limitations on the diodes that can be realized on the CMOS process, and the diode 83 for rectification (and detection) in the IC card and the diode groups 81 and 82 constituting the protection circuit are the circuit configuration shown in FIG. Then, it was difficult to realize on a CMOS.

  The present invention has been made in view of such a situation, and enables an IC card to be configured on a single-chip CMOS.

The IC card of the present invention is a diode with a grounding structure that rectifies the output current of the antenna unit using a P-polarized or N-polar substrate of a semiconductor integrated circuit, or a well having the same polarity as the substrate as one pole of a PN junction. The rectifying means configured, the generating means for generating a signal to be a power supply voltage from the output of the rectifying means, the executing means for executing a predetermined process corresponding to the output of the rectifying means, and the source connected to the substrate is a drain connected to the antenna unit via a capacitor, in response to a voltage applied to a gate connected to the output terminal of the execution means includes an on / off FET, the rectifying means, sub P polarity A first diode composed of a PN junction portion between the straight and the N well, and a PN junction portion between the high concentration P layer formed on the N well and the N well. The connection point where the high-concentration P layer and the high-concentration N layer formed on the upper part of the N well are connected is connected to one end of the antenna unit. A first diode composed of a PN junction portion between a polar substrate and a P well, and a second diode composed of a PN junction portion between a high-concentration N layer formed on the P well and the P well. The connection point where the high-concentration N layer and the high-concentration P layer formed on the top of the P-well are connected is connected to one end of the antenna unit, and the rectifying means, generating means, and execution The means and the FET are formed on a semiconductor integrated circuit which is a one-chip CMOS.

The semiconductor integrated circuit according to the present invention is a diode having a grounding structure for rectifying the output current of an antenna unit using a P-polar or N-polar substrate of the semiconductor integrated circuit, or a well having the same polarity as the substrate as one pole of a PN junction A generating means for generating a signal to be a power supply voltage from the output of the rectifying means, an executing means for executing a predetermined process corresponding to the output of the rectifying means, and a source on the substrate And a FET having a drain connected to the antenna section via a capacitor and turned on / off in response to a voltage applied to a gate connected to the output terminal of the execution means . A first diode composed of a PN junction portion between the substrate and the N well, and a PN junction portion between the high concentration P layer formed on the N well and the N well And a connection point where the high-concentration P layer and the high-concentration N layer formed on the N well are connected to one end of the antenna unit, or A first diode composed of a PN junction portion between an N-polar substrate and a P well, and a first diode composed of a PN junction portion between a high-concentration N layer formed on the P well and the P well. And a connection point where the high-concentration N layer and the high-concentration P layer formed on the top of the P-well are connected to one end of the antenna unit, and a rectifying unit, a generation unit, The execution means and the FET are configured on a semiconductor integrated circuit which is a one-chip CMOS.

In the present invention, a P-polarized or N-polar substrate of a semiconductor integrated circuit, or a well having the same polarity as that of the substrate is used as one pole of a PN junction, and is composed of a diode with a grounded structure that rectifies the output current of the antenna unit. Rectifying means, generating means for generating a signal to be a power supply voltage from the output of the rectifying means, execution means for executing a predetermined process corresponding to the output of the rectifying means, and a source connected to the substrate, An FET whose drain is connected to the antenna portion via a capacitor and turned on / off in response to a voltage applied to the gate connected to the output terminal of the execution means is on a semiconductor integrated circuit which is a one-chip CMOS. It is configured. Further, the rectifying means includes a first diode composed of a PN junction portion between a P-polar substrate and an N well, and a PN junction between a high-concentration P layer formed on the N well and the N well. A connection point between the high-concentration P layer and the high-concentration N layer formed on the upper portion of the N-well is connected to one end of the antenna unit. Or a first diode composed of a PN junction portion of an N-polar substrate and a P well, and a PN junction portion of a high-concentration N layer formed on the P well and the P well. In addition to the second diode, a connection point where the high concentration N layer and the high concentration P layer formed above the P well are connected is connected to one end of the antenna unit.

  According to the present invention, for example, an IC card or the like can be configured on a one-chip CMOS, so that the size and cost can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. As preparations for the previous stage, diodes that can be realized on a CMOS will be described.

  Here, the description is limited to the case where the polarity of the CMOS substrate is the P channel. However, the polarity of the CMOS substrate may be N-channel, in which case all the polarities in the following description are reversed.

  Further, since the potential of the substrate should be set to the lowest potential, here, description will be made assuming that the substrate is at the ground level (the substrate is grounded). However, when the polarity of the substrate is N channel, the potential needs to be set to the maximum potential.

1 to 3 show diodes that can be realized on a CMOS process when the substrate is a P-channel. First, in the CMOS shown in FIG. 1A, an N layer well (Nwell) 2 and a high-concentration P layer (P ⁺ ) are formed on an upper part of a P layer substrate (P substrate) (Psub) 1. 3 is formed, and a high-concentration N layer (N ⁺ ) 4 is formed above the N well 2. A diode formed by attaching electrodes (terminals) T1 or T2 to the high-concentration P layer 3 or the high-concentration N layer 4 of the CMOS, respectively, is represented by a symbol shown in FIG. When the parameters necessary for explanation in the CMOS shown in FIG. 1 are modeled, the result is as shown in FIG.

  That is, in this case, the diode 5 is formed at the PN junction between the P substrate 1 and the N well 2, and the cathode is connected to the terminal T 2 via the high concentration N layer 4. The anode of the diode 5 is connected to the terminal T1 via the P substrate 1 (as described above, the potential is the ground level) and the high concentration P layer 3. The resistor 6 between the diode 5 and the terminal T2 is a so-called bulk resistor formed between the N well 2 and the high concentration N layer 4.

Next, in the CMOS shown in FIG. 2A, a P layer well (P well) 11 and a high-concentration P layer 3 are formed on the P substrate 1, and further on the P well 11. The high concentration N layer 4 and the high concentration P layer (P ⁺ ) 12 are formed. When the electrodes (terminals) T1, T2, or T3 are attached to the high-concentration P layer 3, the high-concentration N layer 4, or the high-concentration P layer 12, respectively, this CMOS has the symbol shown in FIG. It is represented by

  That is, in this case, the diode 13 is formed by the PN junction between the P well 11 and the high concentration N layer 4, and the cathode is connected to the terminal T 2 via the high concentration N layer 4. The anode is connected to the P substrate 1. Further, the anode is connected to the terminal T3 via the high concentration P layer 12 and also to the terminal T1 via the P substrate 1 and the high concentration P layer 3.

  Next, the CMOS shown in FIG. 3A has the same configuration as the CMOS shown in FIG. 2A except that a P well 2 is formed instead of the P well 11. This CMOS is represented by a symbol shown in FIG.

  That is, in this case, a diode is formed by the PN junction portion between the P substrate 1 and the N well 2 and the PN junction portion between the high concentration P layer 12 and the N well 2. Since the P substrate 1, the N well 2, and the concentration P layer 12 have a PNP structure, a PNP transistor (parasitic transistor) 21 is formed.

  The base of this transistor is connected to the terminal T2 through the bulk resistor 6 and the high-concentration N layer 4 described in FIG. 1, and the emitter is connected to the terminal T3 through the high-concentration P layer 12. Has been. Further, the collector is connected to the terminal T 1 through the P substrate 1 and the P substrate 1 and the high-concentration P layer 3.

  Next, it will be described whether the diode 83 for rectification and detection of the IC card in FIG. 15 described above can be replaced with a diode that can be configured in the above-described CMOS.

  First, when the diode 5 shown in FIG. 1B is used, since the anode thereof is connected to the P substrate 1, the potential thereof must be set to the ground level. Further, since there is a bulk resistor 6 between the diode 5 and the terminal T2, a loss occurs in the bulk resistor 6 when the diode 5 is in the ON state. Therefore, it is not preferable to employ the diode 5 in the IC card as a diode for rectification and detection.

  Next, when the diode 13 shown in FIG. 2B is used, since the anode is connected to the P substrate 1, the potential of the anode must still be at the ground level. Furthermore, since the diode 13 is a diode composed of the PN junction portion between the P well 11 and the high concentration N layer 4 as described above, the breakdown voltage (breakdown voltage) is low (breakdown voltage is It is determined by the lower concentration of the P and N layers constituting the PN junction, and the lower the concentration of the lower concentration layer, the higher the breakdown voltage). Therefore, it is used as a diode for rectification and detection. Is not preferred.

  Next, considering the case where the PN junction between the emitter and the base of the transistor 21 shown in FIG. 3B is used as a diode, for example, this case is the same as in FIG. A loss occurs in the bulk resistor 6. However, in this case, since neither the emitter nor the base is connected to the P substrate 1, the potential of the anode or cathode of the diode corresponding to the emitter or base, respectively, is not limited.

  Therefore, when the diode 83 of the IC card is replaced with the transistor 21, the collector is forcibly grounded because it is connected to the P substrate 1, and the configuration is as shown in FIG. In the figure, portions corresponding to those in the IC card of FIG. 15 are denoted by the same reference numerals. Further, in the figure, illustrations other than the loop antenna 31, the capacitor 32, and the transistor 21 are omitted. The illustration of the bulk resistor 6 in the transistor 21 is also omitted.

  In this case, rectification and detection can be performed by the PN junction constituted by the emitter and base of the transistor 21 as in the case of the diode 83. However, when current flows from the emitter to the base, the transistor 21 amplifies the current. A loss current considerably larger than the current flows from the emitter to the collector. Since the loss caused by this current is considerably larger than the loss caused by the bulk resistor 6, the method of using the transistor 21 as shown in FIG. 4 is not preferable.

  The diode whose potential of the anode and the cathode is not limited is only the PN junction portion formed by the emitter and base of the transistor 21 shown in FIG. 3B, and this diode is used as described above. Next, consider the case where the potential of the anode, for example, the anode, is limited to the potential of the P substrate 1 because it is not preferable.

  As a diode whose potential taken by the anode is limited to the potential of the P substrate 1, in addition to those shown in FIGS. 1 and 2, for example, between the collector and base of the transistor 21 shown in FIG. As shown in FIG. 3C, the diode is configured between the emitter and base of the transistor 21 when the terminal T3 of the circuit shown in FIG. 3B is connected to the P substrate 1. For example, as shown in FIG. 3D, there is a diode constituted between a collector and a base of a transistor 21 in which a base (terminal T2) and an emitter (terminal T3) are connected.

  First, since the diode formed between the collector and base of the transistor 21 shown in FIG. 3B corresponds to the PN junction between the P substrate 1 and the N well 2, the breakdown voltage is low. Although high, a loss occurs in the bulk resistor 6 as in FIG.

  Next, the diode formed between the emitter and base of the transistor 21 shown in FIG. 3C is substantially the same as the case shown in FIG. 1, and further, in this case, from the emitter to the base. When a reverse current flows after a large current that saturates the transistor 21 flows, the transistor 21 does not turn off immediately, and therefore a reverse current flows from the base to the emitter for a predetermined period. Therefore, when this is used in place of the diode 83 of FIG. 15, a reverse current flows into the capacitor 35 at the subsequent stage. In the capacitor 35, the current supplied thereto is integrated, and a voltage that is the integrated value is input to the constant voltage regulator 37. Therefore, when a reverse current flows into the capacitor 35, the current is supplied to the constant voltage regulator 37. Therefore, it is difficult to supply a stable voltage as a power source to the amplifier 41 and the digital signal processing unit 42.

  Therefore, when considering a diode formed between the collector and the base in the transistor 21 in which the terminals T2 and T3 shown in FIG. 3D are connected, the terminal T1 is rectified by the diode. , P substrate 1, collector, base, bulk resistor 6, and current flows through the terminal T 2. Therefore, according to the current flowing through this path, a loss due to the bulk resistor 6 still occurs.

  Here, even when the collector and the emitter are used in the reverse manner, that is, when the current flows from the collector of the transistor 21 which is a PNP transistor to the base as shown in FIG. Due to the current amplification action, a large current i ′ (amplified current i) flows from the collector to the emitter.

  However, in this case, since the terminals T2 and T3 are connected (FIG. 3D), a large current i 'flows through the terminal T2 without passing through the bulk resistor 6. Since the current i ′ is obtained by amplifying the current flowing from the collector of the transistor 21 to the base, it is equivalent to being rectified. Therefore, the current i flowing through the collector of the transistor 21 is the current i ″ flowing from the collector to the base. Then, the current i 'flowing from the collector to the emitter is divided and rectified.

  In this case, the current i ′ is considerably larger than the current i ″. Therefore, the current i ″ flowing through the bulk resistor 6 is smaller than that in the case of FIG. It becomes.

  From the above, it is best to use the transistor 21 shown in FIG. 3D as the diode used in place of the diode 83.

  By the way, the transistor 21 in FIG. 3D has a collector corresponding to the anode of the diode connected to the P substrate 1, so that it is necessary to ground and use the collector as an input terminal to which current is input. Therefore, it cannot be provided at the position of the diode 83 shown in FIG.

  Therefore, in order to enable rectification (and detection) in a state where the collector potential is set to the ground level as a predetermined reference level, the transistor 21 provided in place of the diode 83, that is, a diode having a grounding structure is provided. Are arranged as shown in FIG. 6 to constitute an IC card. In FIG. 6, illustrations other than the resonance circuit including the loop antenna 31 and the capacitor 32 and the transistor 21 are omitted. The illustration of the bulk resistor 6 in the transistor 21 is also omitted.

  That is, the collector (the output terminal that outputs the rectified current) of the transistor 21 in which the base corresponding to the terminal T2 and the emitter corresponding to the terminal T3 are short-circuited is grounded, and the connection point between the base and the emitter is connected to the resonance circuit. The loop antenna 31 and the capacitor 32 to be configured are connected to a point D out of two connection points C or D.

  In this way, the transistor 21 as a diode for rectifying and detecting the output of the resonance circuit composed of the loop antenna 31 and the capacitor 32 can be configured on the CMOS process, and further generated by the bulk resistor 6. Loss can be made minute.

  By the way, the capacitor 38 for changing the resonance frequency of the resonance circuit composed of the loop antenna 31 and the capacitor 32 shown in FIG. 15 is more resonant than the transistor 21 as a diode for rectifying and detecting the output of the resonance circuit. It is necessary to provide it on the circuit side (if the capacitor 38 is provided in the subsequent stage of the transistor 21, the resonance frequency does not change by turning on / off the FET 39). Therefore, when the transistor 21 is used in place of the diode 83, the IC card has a connection point between the base and the emitter of the transistor 21 and a connection between the drain of the FET 39 and the capacitor 32, as shown in FIG. Must be configured by connecting to points. In FIG. 7, illustrations other than the transistor 21, the loop antenna 31, the capacitors 32 and 38, and the FET 39 are omitted.

  Here, FIG. 8 and FIG. 9 show the configuration of the FET realized on the CMOS. 8 shows the configuration of the N-channel FET, and FIG. 9 shows the configuration of the P-channel FET.

As shown in FIG. 8A, the N-channel FET has a P well (Pwell) and a high concentration P layer (P ⁺ ) formed on the P substrate (Psub), and further on the P well. Two high-concentration N layers (N ⁺ ) and one high-concentration P layer (P ⁺ ) are formed, and a high-concentration P layer formed on the P substrate and a high concentration formed on the P well. The P layer is connected, and an electrode is arranged on the upper part of the P well so as to be sandwiched between two high-concentration N layers.

  This FET has an electrode as a gate (G), one of two high-concentration N layers as a drain (D), and the other as a source (S), and is represented by a symbol shown in FIG. Is done. As shown in the figure, in the N-channel FET, a parasitic diode is formed between the P substrate and each of the source or drain in such a direction that current flows from the P substrate to the source or drain. Is done.

Next, as shown in FIG. 9A, in the P-channel FET, an N well (Nwell) is formed on the P substrate (Psub), and two high-concentration P layers are formed on the N well. (P ⁺ ) and one high-concentration N layer (N ⁺ ) are formed, and electrodes are arranged on the upper portion of the N well so as to be sandwiched between two high-concentration P layers.

  This FET has an electrode as a gate (G), one of two high-concentration P layers as a drain (D), the other as a source (S), and a high-concentration N layer as a back gate (BG). ) As a symbol shown in FIG. As shown in the figure, in the P-channel FET, a parasitic diode is formed between the back gate and the source or drain in such a direction that current flows from the source or drain to the back gate. .

  Note that parasitic capacitance is also formed in the N-channel and P-channel FETs, but the illustration thereof is omitted in FIGS.

  Since the FET 39 shown in FIG. 15 is an N-channel FET, when this is replaced with an N-channel FET that can be configured on the CMOS of FIG. 8, the IC card shown in FIG. As shown in FIG.

  Since the anode of the parasitic diode is connected to the P substrate as shown in FIG. 8B, the anode of the parasitic diode is also connected to the collector of the transistor 21 as shown in FIG. 7B. Therefore, in this case, the transistor 21 and the parasitic diode (the lower one of the two parasitic diodes in FIG. 7B) whose cathode is connected to the source of the FET are connected in parallel.

  Since the breakdown voltage of the parasitic diode is generally as low as about 5 V, even if the breakdown voltage against the reverse voltage of the transistor 21 as a diode, that is, the breakdown voltage is high, the connection point between the base and emitter of the transistor 21 is high. When a high reverse voltage is applied to the connection point with the source of the FET, current flows from the cathode to the anode of the parasitic diode, and as a result, rectification is not performed.

  Therefore, in order to prevent the parasitic diode from being connected in parallel with the transistor 21, as shown in FIG. 10, one end of the capacitor 38 that is not connected to the FET 39 is connected to the capacitor 32 and the transistor 21. By connecting to the point and connecting the source of the FET 39 to the ground, that is, the P substrate, the IC card is configured so that the capacitor 38 is connected only in parallel with the capacitor 32 in parallel. In FIG. 10, illustrations other than the transistor 21 (and the bulk resistor 6), the loop antenna 31, the capacitors 32, 35, and 36, the constant voltage regulator 37, the capacitor 38, and the FET 39 are omitted.

  In this case, considering the path of FET 39, P substrate, points H and F, capacitor 35, and points E and C when FET 39 is turned on, the path is short-circuited in terms of alternating current. Further, since the capacitance of the smoothing capacitor 35 is sufficiently large, the capacitor 38 is equivalent to being connected in parallel with the capacitor 32 in an AC manner. Therefore, in this case, the resonance frequency can be changed by turning on / off the FET 39.

  Next, a description will be given of a case where the diode groups 81 and 82 constituting the IC card protection circuit in FIG. 15 described above are replaced with the diodes that can be constituted by the CMOS shown in FIGS.

  The diode groups 81 and 82 are applied in the forward direction with a certain level of voltage required to protect the IC card (here, it is set to 3.5 V as described above, and this voltage is hereinafter referred to as a protection voltage as appropriate). It is necessary to turn on only in the case of a single diode, and further, the voltage drop of one diode (voltage drop when a current flows in the forward direction) is about 0.7 V. It is difficult to connect a plurality of diodes in series. Therefore, the diodes used for the diode groups 81 and 82 need to have an anode and a cathode that can take a potential different from the potential of the P substrate.

  A diode composed of CMOS, whose anode and cathode can take a potential different from that of the P substrate, is only the one shown in FIG. 3 (B) described above. Consider a group of connected diodes.

  In the case where the transistor 21 illustrated in FIG. 3B can be a diode in which the potential of the anode and the cathode is not limited, as described above, the PN junction between the emitter and the base is used as the diode. Is the case. Thus, when a plurality of PNP transistors 21 are prepared and the bases of the transistors 21 are connected to the emitters of the other transistors 21 to connect the transistors 21 in multiple stages, the result is as shown in FIG. In FIG. 11, illustration of the bulk resistor 6 is omitted.

  FIG. 11A shows the case where the transistor group 82 in FIG. 15 is configured by a plurality of transistors 21, and FIG. 11B shows the case where the transistor group 81 in FIG. 15 is configured by a plurality of transistors 21. Shows the case. Note that, as shown in FIG. 3B, the collector of the transistor 21 needs to be at the potential of the P substrate. Therefore, the collectors of the transistors 21 constituting the transistor group shown in FIG. It is set to the potential of the substrate (here, it is grounded).

  In the case shown in FIG. 11A, the voltage at the terminal Ti (terminal connected to the emitter of the transistor 21 at the front stage) with respect to the terminal To (terminal connected to the base of the transistor 21 at the last stage) is the transistor When the number of transistors 21 connected in multiple stages is equal to the voltage drop (for example, about 0.7 V) generated between the emitter and base of the transistor 21, the terminal Ti is connected via the emitter and base of the transistor 21 connected in multiple stages. Thus, a current (bypass current) flows through the terminal To, and the voltage at the terminal Ti with respect to the terminal To is equal to or lower than the protection voltage (= voltage drop generated between the emitter and base of the transistor 21 × the number of transistors 21 connected in multiple stages). Limited to

  In this case, since the transistor 21 is turned on, a current flows from the emitter to the collector, and a loss occurs in the bulk resistor 6 (not shown in FIG. 11A). There is no problem because it is.

  On the other hand, in the case shown in FIG. 11B, as indicated by an arrow in the figure, the terminal To is connected from the P substrate through the collector and base of the transistor 21 at the final stage, that is, through one PN junction. A path through which current can flow is formed. Therefore, in this case, when the potential of the terminal To becomes lower than the ground level by a voltage drop (for example, about 0.7 V) between the collector and base of the transistor 21 at the final stage, the voltage of the terminal Ti with respect to the terminal To. Even if the voltage is not higher than the protection voltage (in this case, about 3.5 V here), the current flows from the P substrate to the terminal To, so that the protection works at a voltage that does not require protection. Loss will occur.

  From the above, the diode group shown in FIG. 11A can be used in place of the diode group 82 in FIG. 15, but the diode group shown in FIG. 11B is replaced with the diode group 81 in FIG. It is not preferable to use them.

  By the way, in the IC card, as shown in FIG. 15, diode groups 81 and 82 constituting a protection circuit are provided after the resonance circuit including the loop antenna 31 and the capacitor 32 (protecting in combination with the resonance circuit). Circuit is provided).

  In the case shown in FIG. 15, the positive or negative polarity output current of the resonance circuit composed of the loop antenna 31 and the capacitor 32 is bypassed by the diode group 82 or 81, that is, the resonance circuit of the resonance circuit. By bypassing both positive and negative polarities of the output current, the peak value of the output voltage is limited to a predetermined value or less. Even when only one of the positive and negative polarities is bypassed, the voltage of the other polarity as well as the voltage of the other polarity is subordinately limited.

  Therefore, limiting the output voltage of the resonant circuit to the protection voltage or less can be performed by providing either one of the diode groups 81 and 82 shown in FIG. 15 or not.

  Therefore, here, instead of the diode groups 81 and 82 in FIG. 15, the diode group (transistor group) shown in FIG. 11A that bypasses only the positive polarity output current of the resonance circuit is provided. To. By doing in this way, the diode group which comprises the protection circuit which restrict | limits the output voltage of the resonance circuit comprised by the loop antenna 31 and the capacitor | condenser 32 to below a protection voltage can be comprised by CMOS.

  Next, in place of the diode groups 81 and 82 in FIG. 15, as described above, the transistor group 34 similar to the diode group (transistor group) shown in FIG. 11A (however, the bulk resistance is not shown). The IC card provided with is as shown in FIG. In the figure, illustrations other than the loop antenna 31, capacitor 32, resistor 33, transistor group 34, and diode 83 are omitted.

  In this case, the transistor group 34 is provided after the resonance circuit composed of the loop antenna 31 and the capacitor 32 and before the rectification / detection diode 83. The applied voltage is an AC voltage. Therefore, even if the voltage at the point I with respect to the point J is not equal to or higher than the protection voltage, as shown by the arrows in FIG. And a loss current flows through the collector.

  In order to prevent this, a protection circuit composed of the resistor 33 and the transistor group 34 may be provided in the subsequent stage of the diode 83 so that the voltage applied thereto becomes a DC voltage.

  FIG. 13 shows the configuration of the first embodiment of the IC card configured to satisfy the above conditions. In the figure, portions corresponding to those in FIG. 15 are denoted by the same reference numerals.

  The collector of the transistor 21 connected to the base and the emitter, which is provided in place of the rectifying / detecting diode 83 in FIG. 15, is grounded, and the connection point between the base and the emitter is the loop antenna 31. It is connected to a connection point D with the capacitor 32. Further, one end of a capacitor 38 for changing the resonance frequency of the resonance circuit composed of the loop antenna 31 and the capacitor 32 is connected to the point D, and the drain of the FET 39 is connected to the other end. The source of the FET 39 is grounded (connected to the P substrate), and its gate is connected to the digital signal processing unit 42 as in FIG.

  A protection circuit composed of a resistor 33 and a transistor group 34 instead of the protection circuit composed of the resistor 33 and the diode groups 81 and 82 in FIG. 15 is provided in the subsequent stage of the rectifying and detecting transistor 21, and one end of the resistor 33 is The connection point C or D between the loop antenna 31 and the capacitor 32 is connected to a point C (I). The other end of the resistor 33 is connected to the emitter of the foremost transistor (PNP transistor) constituting the transistor group 34, and the base of the final stage transistor (PNP transistor) is grounded.

  Note that, for example, a voltage drop of 0.7 V is generated between the emitter and base of each transistor constituting the transistor group 34, and the transistor group 34 is constituted by, for example, five transistors (PNP transistors). Has been. Accordingly, the protection circuit constituted by the resistor 33 and the transistor group 34 is connected to the connection points C and D of the loop antenna 31 and the capacitor 32 similarly to the protection circuit constituted by the resistor 33 and the diode groups 81 and 82 in FIG. It is designed to limit the potential difference between the two.

  In the IC card configured as described above, for example, when an electromagnetic wave is radiated from a reader / writer as shown in FIG. 15, the loop antenna 31 has a magnetic flux linked to the electromagnetic field (magnetic flux). Counter electromotive force is generated in accordance with the change in the magnetic field (change in the magnetic field). Of the voltages generated in this manner, a voltage in a predetermined frequency band centered on the resonance frequency of the resonance circuit constituted by the loop antenna 31 and the capacitor 32 is efficiently passed to the subsequent block.

  Then, the signal that has passed through the resonance circuit composed of the loop antenna 31 and the capacitor 32 is rectified without causing a large loss through the transistor 21, and the ripple is removed through the smoothing capacitor 35. The The signal from which the ripple has been removed is supplied to the constant voltage regulator 37, where it is stabilized to a predetermined constant voltage VDD. The voltage VDD is supplied to the amplifier 41 and the digital signal processing unit 42 as a power source.

  As described above, after the power is supplied to the amplifier 41 and the digital signal processing unit 42 and the operation becomes possible, the signal that has passed through the resonance circuit including the loop antenna 31 and the capacitor 32 is converted into a transistor The signal is detected by passing through 21 and output to the digital signal processing unit 42 via the capacitor 40 and the amplifier 41. Thereafter, the digital signal processing unit 42 performs the same processing as in FIG. 15 described above.

  When the data read process is performed, a voltage is applied to the gate of the FET 39 corresponding to the data read from the nonvolatile memory 43 as in the case described above. In this case, the FET 39 Is turned on, one end of the capacitor 38 connected to the FET 39 is connected to the capacitor 32 via the FET 39, the substrate, the point F, the capacitor 35, the points F, and I that are AC-shorted. Is connected to a point C which is one end of the. That is, in this case, the capacitor 38 is equivalent to being connected in parallel with the capacitor 32 in an AC manner. Therefore, the resonance frequency of the resonance circuit composed of the loop antenna 31 and the capacitor 32 is changed.

  In addition, when the IC card is brought extremely close to the reader / writer, and a large current is output from the resonance circuit composed of the loop antenna 31 and the coil 32, that is, between the points I and J, the protection voltage is exceeded. Is applied, current flows from the emitter to the base of each transistor constituting the transistor group 34 (and current also flows from the emitter to the collector), and the peak value of the output voltage of the resonance circuit is limited. Is done. That is, when a large current is output from the resonance circuit including the loop antenna 31 and the coil 32, a part of the current flows as a bypass current to the resistor 33 and the transistor group 34, and the peak value of the output voltage of the resonance circuit. Is limited.

  Next, FIG. 14 shows the configuration of the second embodiment of the IC card of the present invention. In the figure, portions corresponding to those in FIG. 13 are denoted by the same reference numerals. That is, this IC card is provided with a P-channel FET 51 instead of the N-channel FET 39, and its source is not grounded but is connected to the output terminal of the constant voltage regulator 37. It is constructed in the same way as the card.

  In this case, considering the path of FET 51, point G, capacitor 36, points H and F, capacitor 35, and points E, I and C when FET 51 is turned on, this path is short-circuited in terms of alternating current. Since the capacitance of the bypass capacitor 36 is sufficiently large like the smoothing capacitor 35 described with reference to FIG. 10, the capacitor 38 is connected in parallel with the capacitor 32 in an AC manner. Become equivalent. Accordingly, also in this case, the resonance frequency can be changed by turning on / off the FET 51.

  As described above, the transistor 21 as the diode for rectification and detection and the transistor group 34 as the diode group constituting the protection circuit can be realized on the CMOS, so that the IC card is configured by a single chip CMOS. It becomes possible to do.

  The IC card of the present invention has been described above. This IC card is a system for managing input / output to a room, for example, a commuter pass in an automatic ticket gate system, and a system for managing visitors at a lift landing at a ski resort. It is applicable to others.

  In this embodiment, the IC card is provided with the constant voltage regulator 37 and is supplied with power from the reader / writer. However, the IC card can also be provided with built-in power. is there.

  In the present embodiment, the case where the polarity of the CMOS substrate is the P channel has been described. However, the polarity may be the N channel. In this case, as described above, the polarity described above is the polarity. Are all reversed.

  That is, for example, the voltage VDD output from the constant voltage regulator 37 is a positive voltage in the case of FIGS. 13 and 14, but a negative voltage when the polarity of the substrate is N channel.

  Further, the transistors constituting the transistor group 34 constituting the protection circuit are PNP transistors in the case of FIG. 13 and FIG. 14, but are NPN transistors when the substrate polarity is N channel, and therefore the loop antenna 31. By bypassing only the negative polarity output current of the resonance circuit composed of the capacitor 32, the peak value of the output voltage is limited to a predetermined value or less.

  The rectifying / detecting transistor 21 is a PNP transistor in the case of FIGS. 13 and 14, but is an NPN transistor when the polarity of the substrate is N-channel.

It is a figure which shows the 1st diode realizable on the process of CMOS at the time of making a substrate into P channel. It is a figure which shows the 2nd diode realizable on the process of CMOS at the time of making a substrate into P channel. It is a figure which shows the 3rd diode realizable on the process of CMOS at the time of making a substrate into P channel. It is a circuit diagram which shows the structural example of an IC card at the time of using the circuit of FIG.3 (B). FIG. 4 is a diagram for explaining rectification performed in the circuit of FIG. It is a circuit diagram which shows the structural example of an IC card at the time of using the circuit of FIG.3 (D). It is a circuit diagram for demonstrating the position where the parasitic diode parasitizes when FET39 is comprised by CMOS. It is a figure which shows the structure of N channel FET. It is a figure which shows the structure of P channel FET. It is a circuit diagram which shows the structural example of the IC card which is not influenced by the parasitic diode of FET39. FIG. 4 is a diagram illustrating a transistor group in which the transistors in FIG. 3B are connected in multiple stages. FIG. 6 is a diagram for explaining a loss current that flows when a protection circuit including a resistor 33 and a transistor group is provided in the previous stage of a diode 83; It is a circuit diagram which shows the structure of 1st Example of the IC card of this invention. It is a circuit diagram which shows the structure of 2nd Example of the IC card of this invention. It is a figure which shows the structure of an example of the conventional non-contact card system (IC card and reader / writer). 16 is a flowchart for explaining the operation of the reader / writer of FIG. It is a flowchart explaining operation | movement of the IC card of FIG.

Explanation of symbols

  1 P substrate (P layer substrate), 2 N well, 3 High concentration P layer, 4 High concentration N layer, 5 Diode, 6 Bulk resistance, 11 P well, 12 High concentration P layer, 13 Diode, 21 PNP Transistor, 31 loop antenna, 32 capacitor, 33 resistor, 34 transistor group, 35, 36 capacitor, 37 constant voltage regulator, 38 capacitor, 39 N channel FET, 40 capacitor, 41 amplifier, 42 digital signal processing unit, 43 nonvolatile memory , 51 P-channel FET, 81, 82 diode group, 83 diode, 91 host computer, 92 digital signal processor, 93 carrier generator, 94 amplifier, 95 resistor, 96 capacitor, 97 Puantena, 98 diodes, 99 a capacitor, 100 an amplifier

Claims (3)

In an IC card having an antenna unit for receiving electromagnetic waves and a semiconductor integrated circuit connected to the antenna unit,
Rectification constituted by a diode having a grounding structure for rectifying the output current of the antenna unit using a P-polarity or N-polarity substrate of the semiconductor integrated circuit or a well having the same polarity as the substrate as a PN junction. Means,
Generating means for generating a signal to be a power supply voltage from the output of the rectifying means;
Execution means for executing predetermined processing in response to the output of the rectifying means;
A FET having a source connected to the substrate, a drain connected to the antenna unit via a capacitor, and an ON / OFF switch corresponding to a voltage applied to a gate connected to the output terminal of the execution means. ,
The rectifying means includes
A first diode composed of a PN junction portion of a P-polar substrate and an N well, and a PN junction portion of a high-concentration P layer formed on the N well and the N well. A connection point between the high-concentration P layer and the high-concentration N layer formed on the N well is connected to one end of the antenna unit.
Or a first diode composed of a PN junction portion of an N-polar substrate and a P well, and a PN junction portion of a high-concentration N layer formed on the P well and the P well. A connection point between the high concentration N layer and the high concentration P layer formed on the P well is connected to one end of the antenna unit.
The IC card, wherein the rectifying means, the generating means, the executing means, and the FET are configured on the semiconductor integrated circuit which is a one-chip CMOS. The IC card according to claim 1, wherein the antenna unit includes a resonance circuit in which an antenna and a capacitor are connected in parallel. In a semiconductor integrated circuit connected to an antenna unit that receives electromagnetic waves,
Rectification constituted by a diode having a grounding structure for rectifying the output current of the antenna unit using a P-polarity or N-polarity substrate of the semiconductor integrated circuit or a well having the same polarity as the substrate as a PN junction. Means,
Generating means for generating a signal to be a power supply voltage from the output of the rectifying means;
Execution means for executing predetermined processing in response to the output of the rectifying means;
A FET having a source connected to the substrate, a drain connected to the antenna unit via a capacitor, and an ON / OFF switch corresponding to a voltage applied to a gate connected to the output terminal of the execution means. ,
The rectifying means includes
A first diode composed of a PN junction portion of a P-polar substrate and an N well, and a PN junction portion of a high-concentration P layer formed on the N well and the N well. A connection point between the high-concentration P layer and the high-concentration N layer formed on the N well is connected to one end of the antenna unit.
Or a first diode composed of a PN junction portion of an N-polar substrate and a P well, and a PN junction portion of a high-concentration N layer formed on the P well and the P well. A connection point between the high concentration N layer and the high concentration P layer formed on the P well is connected to one end of the antenna unit.
The rectifying means, the generating means, the executing means, and the FET are configured on the semiconductor integrated circuit which is a one-chip CMOS.

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