JP3970186B2 - Integrated circuit device and processing device having reconfigurable circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit technology, and particularly to a technology of an integrated circuit device and a processing device provided with a reconfigurable circuit.
[0002]
[Prior art]
An FPGA (Field Programmable Gate Array) can design circuit configuration relatively freely by writing circuit data after the LSI is manufactured, and is used for designing dedicated hardware. The FPGA includes a lookup table (LUT) for storing a truth table of a logic circuit, a basic cell composed of an output flip-flop, and a programmable wiring resource connecting the basic cells. In the FPGA, a target logical operation can be realized by writing data stored in the LUT and wiring data. However, when an LSI is designed using an FPGA, the mounting area is very large and the cost is high compared to an ASIC (Application Specific IC) design. Thus, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the FPGA (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
JP-A-10-256383 (full text, Fig. 1-4)
[0004]
[Problems to be solved by the invention]
In satellite broadcasting, image quality may be adjusted by switching broadcast modes depending on the season. In the receiver, a plurality of circuits are built in hardware for each broadcast mode in advance, and the circuit is switched by a selector according to the broadcast mode for reception. Therefore, the other broadcast mode circuits of the receiver are idle during that time. When switching and using multiple dedicated circuits, such as mode switching, and the switching interval is relatively long, instead of creating multiple dedicated circuits, the LSI can be reconfigured instantaneously at the time of switching. The structure can be simplified to improve versatility, and at the same time the mounting cost can be reduced. In order to meet such needs, the manufacturing industry has attracted attention to dynamically reconfigurable LSIs. In particular, LSIs mounted on mobile terminals such as mobile phones and PDAs (Personal Data Assistants) must be downsized. If LSIs can be dynamically reconfigured and functions can be switched appropriately according to the application, Mounting area can be reduced.
[0005]
The FPGA has a high degree of design freedom in circuit configuration and is general-purpose. On the other hand, in order to enable connection between all the basic cells, it is necessary to include a large number of switches and a control circuit for controlling ON / OFF of the switches. This inevitably increases the mounting area of the control circuit. Further, since a complicated wiring pattern is used for the connection between the basic cells, the wiring tends to be long, and the delay is increased because many switches are connected to one wiring. For this reason, FPGA based LSIs are often used only for trial manufacture and experiments, and are not suitable for mass production in view of mounting efficiency, performance, cost, and the like.
[0006]
Further, in the FPGA, since it is necessary to send setting data to a large number of basic cells of the LUT method, it takes a considerable time to configure the circuit. Therefore, the FPGA is not suitable for an application that requires instantaneous switching of the circuit configuration. Therefore, even if an attempt is made to configure a satellite broadcast receiving circuit with an FPGA, the circuit configuration cannot be instantaneously switched, so the circuit reconfiguration function of the FPGA cannot be used, and in reality, a plurality of circuits and selectors are used. It must be formed on the hardware. In this way, when one of a plurality of circuits is selected and used, having all the circuits on the hardware even in a situation where the selected circuit is not frequently changed, This leads to an increase in power consumption due to the operation of unnecessary circuits.
[0007]
The present invention has been made in view of such circumstances, and an object thereof is to provide an integrated circuit device and a processing device including a reconfigurable circuit that contributes to a reduction in circuit scale.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, an aspect of the present invention provides a reconfigurable circuit having a logic circuit whose function can be changed and a plurality of patterns of setting data for configuring the reconfigurable circuit as an intended circuit. A storage unit for storing, a selection signal for specifying a circuit to be selected, a control unit for selecting setting data from a plurality of patterns stored in the storage unit, and a reconfiguration based on the selected setting data Provided is a processing device including a setting unit that sets a circuit configuration of a configurable circuit. According to the processing apparatus of this aspect, a circuit having a necessary function according to a situation is dynamically reconfigured into a reconfigurable circuit, so that the circuit scale can be reduced. In addition, since it is not necessary to configure a circuit that is not necessary, power consumption can be reduced. The setting data selected by the control unit is not limited to one pattern, and may be a plurality of patterns if necessary.
[0009]
The selection signal received by the control unit may be instructed by the user. The control unit may accept status information of the broadcast data signal as a selection signal. The broadcast data signal switches the broadcast mode according to the season, etc., and the broadcast data signal includes state information indicating the mode state at that time. Conventionally, one of a plurality of circuits built on the LSI has been selected based on this state information. In the processing apparatus of this aspect, a new one is selected based on the state information. The circuit will be reconfigured. By appropriately changing the circuit configured on the reconfigurable circuit based on the selection signal, the circuit scale can be reduced and the power consumption can be reduced as compared with the case where a plurality of circuits are built in advance. Is possible.
[0010]
The reconfigurable circuit includes a multi-stage arrangement of logic circuits each capable of selectively executing a plurality of arithmetic functions, and a connection section that can set a connection relationship between the output of the preceding logic circuit and the input of the succeeding logic circuit. In addition, the setting unit may set functions and connection relationships of a plurality of logic circuits. The structure of the multistage arrangement of logic circuits is an arrangement in which a plurality of columns of logic circuits arranged in the horizontal direction are combined in the vertical direction, and there is no connection connection between the logic circuits in the horizontal direction, that is, in each column. A structure in which a connection for connection is provided between the output of the first logic circuit row and the input of the next-stage logic circuit row may be employed.
[0011]
Each logic circuit may be a circuit capable of relatively high-performance operations, for example, an arithmetic logic circuit (ALU (Arithmetic Logic Unit)) capable of selectively executing a plurality of types of multi-bit operations. Also good. The logic circuit has a selector for selecting a plurality of arithmetic functions, and the selector selects an arithmetic function according to setting data loaded from the outside. By making the arithmetic function of the logic circuit selectable by the selector, the function of the logic circuit can be switched instantaneously, and as a result, the function of the reconfigurable circuit can be set instantaneously.
[0012]
Another aspect of the present invention relates to a reconfigurable circuit having a logic circuit capable of changing functions, and setting data selected from a plurality of patterns of setting data for configuring the reconfigurable circuit as a desired circuit. An integrated circuit device including a setting unit for setting a circuit configuration of a reconfigurable circuit is provided.
[0013]
It should be noted that any combination of the above components and the expression of the present invention expressed as a method, apparatus, system, and computer program are also effective as an aspect of the present invention.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a configuration diagram of a processing apparatus 10 according to the embodiment. The processing device 10 includes an integrated circuit device 16 and an external control device 26. The integrated circuit device 16 has a function that makes it possible to reconfigure the circuit configuration. The external control device 26 creates setting data for setting the circuit configuration of the integrated circuit device 16 and supplies the setting data to the integrated circuit device 16. The integrated circuit device 16 is configured as one chip, and includes the reconfigurable circuit 12 and the setting unit 14. The external control device 26 includes a control unit 18, a compilation unit 20, a setting data generation unit 22, and a storage unit 24.
[0015]
The reconfigurable circuit 12 includes a logic circuit whose function can be changed. Specifically, the reconfigurable circuit 12 has a configuration in which a plurality of logic circuits capable of selectively executing a plurality of arithmetic functions are arranged in a plurality of stages, and an output of a preceding logic circuit string and an input of a succeeding logic circuit string The connection part which can set the connection relation of is included. The function of each logic circuit and the connection relationship between the logic circuits are set based on setting data 32 supplied by the setting unit 14. The setting data 32 is generated by the following procedure.
[0016]
Various programs 28 to be realized by the integrated circuit device 16 are held in the storage unit 24. The program 28 is a description of a signal processing circuit or a signal processing algorithm that does not operate simultaneously in a high-level language such as C language. The compiling unit 20 compiles the program 28 stored in the storage unit 24, converts it into a data flow graph 30, and stores it in the storage unit 24. The data flow graph 30 expresses the flow of calculation of input variables and constants in a graph structure.
[0017]
The setting data generation unit 22 generates setting data 32 from the data flow graph 30 and stores it in the storage unit 24. The setting data 32 is data for mapping the data flow graph 30 to the reconfigurable circuit 12 and determines the function of the logic circuit in the reconfigurable circuit 12 and the connection relationship between the logic circuits. By executing this procedure for each program 28, the storage unit 24 stores a plurality of patterns of setting data 32 for configuring the reconfigurable circuit 12 as an intended circuit.
[0018]
FIG. 2 is a configuration diagram of the reconfigurable circuit 12. The reconfigurable circuit 12 includes a plurality of stages of logic circuits 40 arranged in a plurality of stages. A connection unit 42 provided at each stage outputs an output of a preceding logic circuit string and an input of a subsequent logic circuit string. Has a structure that can be arbitrarily connected by setting. Here, an ALU is shown as an example of the logic circuit 40. Each ALU can selectively execute a plurality of types of multi-bit operations such as logical sum, logical product, and bit shift by setting. Each ALU has a selector for selecting a plurality of arithmetic functions.
[0019]
As shown in the figure, the reconfigurable circuit 12 is configured as an ALU array in which Y ALUs in the horizontal direction and X ALUs in the vertical direction are arranged. Input variables and constants are input to the first-stage ALU11, ALU12,..., ALU1Y, and a set predetermined calculation is performed. The calculation result output is input to the second-stage ALU 21, ALU 22,..., ALU 2 Y according to the connection set in the first-stage connection unit 42. In the first stage connection section 42, the connection is configured so that an arbitrary connection relationship can be realized between the output of the first ALU column and the input of the second ALU column. The connection is effective. Thereafter, the configuration is the same up to the (X-1) -th stage connecting section 42, and the X-th stage ALU column as the final stage outputs the final result of the calculation.
[0020]
FIG. 3 is a diagram illustrating an example of the data flow graph 30. The setting data generation unit 22 generates setting data 32 for mapping the data flow graph 30 to the reconfigurable circuit 12. In the data flow graph 30, the flow of calculation of input variables and constants is expressed step by step in a graph structure. In the figure, operators are indicated by circles. In order to realize the calculation flow by the data flow graph 30 on the circuit, the setting data 32 specifies the logic circuit to which the calculation function is assigned, defines the connection relationship between the logic circuits, and further defines input variables, input constants, and the like. Data. Therefore, the setting data 32 includes selection information supplied to a selector that selects the function of each logic circuit 40, connection information for setting the connection of the connection unit 42, necessary variable data, constant data, and the like.
[0021]
Returning to FIG. 1, the control unit 18 receives a selection signal for specifying a circuit to be selected, and selects one pattern of the setting data 32 stored in the storage unit 24 based on the selection signal. If necessary, the selected setting data 32 may be two or more patterns. The selection signal may be instructed by the user, or may be status information included in a broadcast data signal or the like. Although the state information will be described later, it is information necessary for decoding by the receiver, and corresponds to setting information such as the mode and modulation method of the data signal to be broadcast, for example. The control unit 18 supplies the selected setting data 32 to the setting unit 14.
[0022]
The setting unit 14 sets the selected setting data 32 in the reconfigurable circuit 12 and reconfigures the circuit of the reconfigurable circuit 12. Thereby, the reconfigurable circuit 12 can execute a new expected operation. By configuring the reconfigurable circuit 12 and the setting unit 14 on the same chip, the circuit contents of the reconfigurable circuit 12 can be changed at high speed. The setting unit 14 includes a cache memory and other types of memory, and may store a plurality of setting data 32 in advance. In this case, the control unit 18 supplies a selection signal to the setting unit 14, and the setting unit 14 can instantaneously set the desired setting data 32 in the reconfigurable circuit 12 based on the selection signal. In the present embodiment, the control unit 18 is arranged in the external control device 26, but the control unit 18 may exist in the integrated circuit device 16.
[0023]
As described above, according to the processing device 10 in the present embodiment, it is not necessary to have a plurality of circuits that do not operate at the same time on the hardware, and the necessary circuits are configured by the reconfigurable circuit 12 instantaneously. be able to. For example, even when the mode is switched at the time of broadcast reception, the storage unit 24 holds circuit setting data 32 in advance for each mode, so that the circuit on the reconfigurable circuit 12 is reconfigured according to the mode. It can respond by doing. Thereby, the circuit scale of the processing apparatus 10 can be reduced, and power consumption can also be reduced.
[0024]
FIG. 4 is an explanatory diagram for explaining the operation of the processing apparatus 10 of the present invention. In this example, three types of data for configuring the circuit A, the circuit B, and the circuit C are prepared as the setting data 32, and the setting unit 14 loads the setting data 32 of the circuit A into the reconfigurable circuit 12. In this state, the reconfigurable circuit 12 has the function of the circuit A. As a matter of course, when the setting unit 14 loads another setting data 32, for example, the setting data 32 of the circuit B, into the reconfigurable circuit 12, the reconfigurable circuit 12 has the function of the circuit B. .
[0025]
FIG. 5 is an explanatory diagram for explaining the operation of the processing apparatus 10 of the present invention. In this example, data for configuring an FIR filter circuit using three types of filter coefficient D, filter coefficient E, and filter coefficient F is prepared as setting data 32, and the setting unit 14 uses the filter coefficient E. By loading the setting data 32 of the FIR filter circuit to be loaded into the reconfigurable circuit 12, the reconfigurable circuit 12 has a function of the FIR filter circuit using the filter coefficient E. As a matter of course, when the setting unit 14 loads another setting data 32, for example, setting data 32 of an FIR filter circuit using the filter coefficient F, into the reconfigurable circuit 12, the reconfigurable circuit 12 uses the filter coefficient. The function of the FIR filter circuit using F is provided.
[0026]
The processing apparatus 10 of this Embodiment can be used for various uses. In particular, when a plurality of circuit functions that are not used at the same time are necessary and the circuit to be used is changed according to the situation, it is used for designing a circuit device that does not frequently change the circuit. The processing device 10 is very suitable. Such an example is shown below.
[0027]
<Example 1>
In the case of Japanese terrestrial digital broadcasting In Japan terrestrial digital broadcasting, there are mainly the following seven types of parameters that are not changed so much once they are determined by a transmission company. Information specifying these parameters is referred to as “state information”. The state information is included in the broadcast data signal.
[0028]
“Transmission mode”: There are three types of modes with different OFDM carrier intervals. The carrier interval is about 4 kHz in mode 1, about 2 kHz in mode 2, and about 1 kHz in mode 3. Mode 1 with the widest carrier spacing is the most resistant to transmission line noise, but the number of data that can be transmitted at a time is the smallest.
[0029]
“Guard Interval”: The output data after IFFT (Inverse Fast Fourier Transform) is obtained by adding data of a specified time length as it is before a valid symbol from the back side in time. Eliminate obstacles caused by multipath time differences such as ghost interference. Four types of guard intervals are prepared for each of the three types of modes. The larger the guard interval ratio, the stronger the multipath, but the longer the signal processing time.
[0030]
“Modulation scheme”: There are four types of modulation schemes: DQPSK, QPSK, 16QAM, and 64QAM. For noise, DQPSK is the strongest and 64QAM is the weakest in this order of arrangement. On the other hand, the amount of information sent at a time is the smallest in DQPSK and the largest in 64QAM in this order.
[0031]
“Inner code (convolutional code) coding rate”: indicates the ratio of the number of bits before coding to the number of bits after convolutional coding. For the above four types of modulation schemes, there are five types of coding rates of 1/2, 2/3, 3/4, 5/6, and 7/8, respectively. With respect to noise, in the order of the arrangement, the coding rate is 1/2 strongest, and the coding rate is 7/8 weakest. On the other hand, the amount of information sent at a time is the smallest when the coding rate is 1/2 and the largest when the coding rate is 7/8.
[0032]
“Hierarchical transmission designation”: OFDM segment groups subjected to different transmission path coding are simultaneously transmitted. Up to 3 levels can be specified.
[0033]
“Segment length”: Designates the number of segments in each layer to be used among 13 segments.
[0034]
“Time interleaving length”: The symbol data after modulation is dispersed in time to improve anti-fading performance. The time interleave length is specified independently for each hierarchy.
[0035]
These parameters are changed, for example, in response to changes in the transmission state due to changes in the ionosphere depending on the season, and since it is a mixed digital / analog broadcast, it does not affect analog broadcast. Although the transmission power is reduced, there may be a case where the transmission power is increased when only digital broadcasting is performed in the future.
[0036]
In the processing apparatus 10 including the reconfigurable circuit 12, the storage unit 24 stores circuit setting data 32 required in accordance with changes in these parameters in advance. When the processing device 10 supports terrestrial digital broadcasting, the circuit corresponding to each parameter is not mapped to the reconfigurable circuit 12 at the same time, but only when the parameter is changed, the corresponding circuit is reconfigured. Set to the configurable circuit 12. Referring to FIG. 1, specifically, control unit 18 detects state information included in a broadcast data signal and supplies corresponding setting data 32 to setting unit 14. The setting unit 14 reconfigures the reconfigurable circuit 12 based on the setting data 32. The data portion of the broadcast data signal is sent to the reconfigurable circuit 12, and the reconfigurable circuit 12 executes a desired process. According to this processing apparatus 10, since only necessary circuits are mapped from time to time, the circuit scale can be reduced and the power consumption can be reduced.
[0037]
<Example 2>
In the case of Japanese BS digital broadcasting In Japanese BS digital broadcasting, there are mainly the following six types of parameters that are not changed so much once they are determined by the transmission company. Information specifying these parameters is referred to as “state information”. The state information is included in the broadcast data signal.
[0038]
"Transmission mode (modulation method)": There are seven types of modes 1 to 7, including BPSK (1/2), QPSK (1/2), QPSK (2/3), QPSK (3/4), and QPSK. (5/6), QPSK (7/8), and TC8PSK (2/3). However, () indicates the coding rate.
[0039]
“Inner code coding rate”: As shown in “Transmission mode (modulation method)”, there are five coding rates of 1/2, 2/3, 3/4, 5/6, and 7/8. .
[0040]
“Hierarchical transmission designation”: Within a total of 48 slots, a maximum of 4 types can be arranged and transmitted in a frame from slot numbers 1 to 48 in descending order of the number of phases, such as TC8PSK, QPSK, BPSK, in descending order of coding rate .
[0041]
“Relative TS / slot information”: TS transmitted in each slot in order from slot 1 is expressed using a relative TS number. A maximum of 8 TS can be transmitted within one modulated wave.
[0042]
“Relative TS / TS number correspondence table”: shows a correspondence table for converting the relative TS number used in the item of relative TS / slot information into TS_ID of the MPEG2 system.
[0043]
“Transmission / reception control information”: a signal for receiver activation control in emergency alert broadcasting and a control signal for switching an uplink station.
[0044]
In the processing apparatus 10 including the reconfigurable circuit 12, the storage unit 24 stores circuit setting data 32 required in accordance with changes in these parameters in advance. When the processing device 10 supports BS digital broadcasting, all the circuits corresponding to the respective parameters are not mapped to the reconfigurable circuit 12 at the same time, but only when the parameters are changed, the corresponding circuit is reconfigured. Set to the blue circuit 12. Referring to FIG. 1, specifically, control unit 18 detects state information included in a broadcast data signal and supplies corresponding setting data 32 to setting unit 14. The setting unit 14 reconfigures the reconfigurable circuit 12 based on the setting data 32. The data portion of the broadcast data signal is sent to the reconfigurable circuit 12, and the reconfigurable circuit 12 executes a desired process. According to this processing apparatus 10, since only necessary circuits are mapped from time to time, the circuit scale can be reduced and the power consumption can be reduced.
[0045]
For example, the receiver activation control circuit in emergency alert broadcasting only needs to operate during emergency alert broadcasting, and does not need to operate normally. Therefore, the processing apparatus 10 does not usually have a receiver activation control circuit, and only needs to map the receiver activation control circuit to the reconfigurable circuit 12 at the time of emergency warning broadcasting. When the emergency warning broadcast is completed, a normal video signal processing circuit may be re-mapped to the reconfigurable circuit 12. Thus, the processing apparatus 10 does not need to have a receiver activation control circuit and a signal processing circuit that do not operate simultaneously.
[0046]
As described above, the reconfigurable circuit 12 included in the processing apparatus 10 uses an ALU having high-performance computing capability as a basic cell, and the reconfigurable circuit 12 and the setting unit 14 are configured on one chip. Therefore, the configuration can be realized at high speed, for example, with one clock. Therefore, even when the broadcast data is received, by loading the setting data 32, the circuit can be reconfigured instantaneously, and the viewer can view the video without interruption.
[0047]
The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. .
[0048]
For example, the array of ALUs in the reconfigurable circuit 12 is not limited to a multistage array that allows connection only in the vertical direction, but may be a mesh-like array that allows connection in the horizontal direction. In the above description, the connection for connecting the logic circuits by skipping the stages is not provided, but the connection connection for skipping such stages may be provided.
[0049]
In addition, the example in which the processing device 10 is applied to a satellite broadcast receiving decoder has been described, but the application is not limited to this, and it is possible to use the processing device 10 in, for example, an in-vehicle audio device or a portable terminal. That is understood by the contractor.
[0050]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the integrated circuit device and processing apparatus provided with the reconfigurable circuit which contributes to reduction of a circuit scale can be provided.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a processing apparatus according to an embodiment.
FIG. 2 is a configuration diagram of a reconfigurable circuit.
FIG. 3 is a diagram illustrating an example of a data flow graph.
FIG. 4 is an explanatory diagram for explaining the operation of the processing apparatus.
FIG. 5 is an explanatory diagram for explaining the operation of the processing apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Processing apparatus, 12 ... Reconfigurable circuit, 14 ... Setting part, 16 ... Integrated circuit device, 18 ... Control part, 20 ... Compile part, 22 ... Setting Data generation unit, 24 ... storage unit, 26 ... external control device, 28 ... program, 30 ... data flow graph, 32 ... setting data, 40 ... logic circuit, 42 ... -Connection part.

Claims (1)

A processing device for receiving and processing broadcast data signals,
A reconfigurable circuit having a logic circuit capable of changing functions;
A storage unit for storing setting data for configuring the reconfigurable circuit;
When the status information included in the broadcast data signal is changed, a control unit that selects setting data corresponding to the changed status information from the storage unit ;
A setting unit configured to perform a setting for changing a part of the configuration of the reconfigurable circuit based on the selected setting data;
The processing apparatus , wherein the setting data is based on a data flow graph .

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