JP3971144B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device using the same, and more particularly, to a method of reducing pattern conversion difference caused by density of device patterns formed on a semiconductor substrate, and a semiconductor device manufactured using the method. It is to provide.
[0002]
[Prior art]
In a conventional method for manufacturing a semiconductor device, a film made of a material to be processed is formed on a semiconductor substrate, a photoresist is applied on the film, a resist film is patterned using a photomask, and the photoresist film is formed. Some masks form a pattern by etching a film made of a material to be processed.
[0003]
In general-purpose DRAMs and memory / logic mixed DRAMs, the processing of wiring layers such as the gates of MOS transistors is performed by DRAM memory cell array sections in which lines and spaces are arranged at equal intervals, and DRAM peripheral circuits and logic circuits composed of isolated patterns. It is performed on the subject.
[0004]
At this time, in the isolated portion and the end of the memory cell array,
(1) In order to avoid pattern jumping (disappearance of fine parts due to pattern conversion differences) in the exposure process, the resist film of the fine parts is formed thicker.
(2) When anisotropically etching the material to be processed, a taper angle is generated in the cross-sectional shape of the processed portion due to the micro loading effect (change in the etching state due to the pattern shape around the processed portion).
Therefore, in the isolated portion and the end portion of the memory cell array, the shape of the processed portion is usually formed to be about 20 nm thicker than a desired dimension. For example, if the gate length of the transistor deviates from a desired dimension, the operation speed of the transistor is reduced.
[0005]
The above problem will be described more specifically with reference to FIG. In FIG. 5, the process of forming the gate electrode of the MOS transistor will be described as an example. However, this problem does not necessarily depend on the level of the wiring layer, and is common to pattern formation at an arbitrary level.
[0006]
As shown in FIG. 5A, a gate oxide film 2 (SiO ₂ ) is formed on a silicon substrate 1, and then a polysilicon film 3 having a thickness of about 100 nm as a material for a gate electrode, and a hard mask. A silicon nitride film (SiN) having a thickness of about 200 nm is formed as a material.
[0007]
Next, a photoresist film is applied onto the silicon nitride film and exposed, and the silicon nitride film is processed using the patterned photoresist film as a mask. FIG. 5A shows the cross-sectional shapes of the silicon nitride films 4a, 4b, and 4c patterned on the polysilicon film 3 in this way.
[0008]
Here, the silicon nitride film 4a is, for example, a mask for processing the polysilicon gate of the MOS transistor in the memory cell array, the silicon nitride film 4b is a mask for processing the polysilicon gate of the MOS transistor in the memory cell array end, and the silicon nitride film 4c is a mask for processing the polysilicon gate of the MOS transistor in the isolated portion such as a peripheral circuit of the memory cell array.
[0009]
Next, as shown in FIG. 5B, the polysilicon gates 3a, 3b, and 3c are formed by anisotropic etching using Reactive Ion Etching (RIE) using the silicon nitride films 4a, 4b, and 4c as a mask. Form. At this time, for the reasons (1) and (2) above, for example, when the polysilicon gate 3a in the memory cell array is finished to a 130 nm line & space, the polysilicon gate 3c in the isolated portion has a minimum line width of about 150 nm or more. Can only be realized.
[0010]
Thus, in the conventional lithography process, it is very difficult to set the line width of the isolated portion to a desired value independently of the line width inside the memory cell array.
[0011]
[Problems to be solved by the invention]
As described above, the conventional lithography process reduces the line width of the isolated portion in the sparse part of the pattern shape such as the inside of the peripheral circuit independently of the line width in the dense part of the pattern shape such as the inside of the memory cell array. It was very difficult to set the desired value.
[0012]
The present invention has been made to solve the above problems, and a method for reducing the line width of an isolated portion in a sparse part of a pattern shape while maintaining the line width in a dense part of the pattern shape, and a semiconductor using the same An object is to provide an apparatus.
[0013]
[Means for Solving the Problems]
In the method for manufacturing a semiconductor device of the present invention, for example, a silicon nitride film for forming a hard mask is formed on a polysilicon film, the silicon nitride film is processed using a resist mask, and then used as a hard mask for a slimming process. By forming a silicon oxide film and selectively removing the silicon oxide film by using isotropic etching, the silicon oxide film is left only in a dense portion having a pattern shape, for example, inside the memory cell array.
[0014]
In this state, the silicon nitride film is selectively isotropically etched so that only the hard mask made of the silicon nitride film for forming the edge of the memory cell array and the isolated pattern is slimmed, for example. If the polysilicon film is anisotropically etched using the silicon nitride film that has undergone such a slimming process as a mask, a difference in pattern conversion caused by pattern density can be reduced.
[0015]
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a pattern of a second film on a first film formed on a semiconductor substrate so as to have a sparse part and a dense part ; so as to cover the second layer, the first step and, when removing the third film in the sparse portion simultaneously the dense portion that form a large third film etching rate than the second film The first etching step for selectively removing the third film in the step until the second film is exposed, and the third film remaining in the dense part in the first etching step as a mask. A step of selectively removing the surface of the second film; a step of removing the third film remaining in the dense portion in the first etching process; and the first film using the second film as a mask. And a second etching step for etching the film. .
[0016]
The semiconductor device of the present invention includes a first film which is patterned on the semiconductor substrate, and a second film made form on said first layer, said first, third covering the second film The pattern of the first and second films is composed of a sparse part and a dense part, and the second film patterned in the dense part has corners around the upper part removed. It is characterized by that.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0018]
<First Embodiment>
1 and 2 are views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 1 and 2 will be described by taking as an example a process of forming a gate electrode of a MOS transistor constituting a semiconductor memory.
[0019]
On the silicon substrate 1, a polysilicon film 3 (first film in claim 1) having a thickness of about 100 nm serving as a gate electrode is formed via a silicon oxide film 2 (SiO ₂ ) serving as a gate insulating film. Further, a silicon nitride film (SiN; second film in claim 1) having a thickness of about 200 nm is formed as a hard mask for pattern formation using the polysilicon film 3 as a gate electrode.
[0020]
Next, using the photoresist film as a mask, for example, the silicon nitride films 4a, 4b, and 4c serving as a hard mask for forming a gate electrode are anisotropically etched using RIE, and then the photoresist film is removed. The steps up to here are the same as the conventional manufacturing steps described above with reference to FIG. At this time, it is assumed that the desired gate length of the MOS transistor in the cell array of the semiconductor memory is, for example, 130 nm.
[0021]
Next, the oxide film 5 having excellent step coverage such as Boron-Phosphorus-Silicate glass (BPSG) having a thickness of about 85 nm so as to sufficiently fill the cell array (third film according to claim 1; hereinafter referred to as BPSG oxide film) Called). At this time, as shown on the left side of FIG. 1B, the thickness of the BPSG oxide film 5 is such that the silicon nitride films 4a and 4b serving as hard masks for forming gate electrodes arranged in a line & space manner are densely arranged. The thickness is sufficiently filled, that is, 50% to 100% of the space width inside the cell array.
[0022]
Next, as shown on the left side of FIG. 1C, by selectively removing the BPSG oxide film 5 using an isotropic etching process such as normal wet etching, the silicon nitride film 4a inside the cell array, The BPSG oxide film 5a buried between 4b is left, for example, with a thickness of about 150 nm. At this time, the BPSG oxide film 5a is completely removed from the peripheral portion of the silicon nitride film 4c for forming an isolated gate in the peripheral circuit region arranged on the right side of FIG. 1C, and the silicon nitride film 4c is exposed. It becomes a state.
[0023]
Next, by using an isotropic etching process such as wet etching with heated phosphoric acid, the silicon nitride films 4a, 4b, and 4c shown in FIG. Is slimmed as indicated by 4b 'and 4c' in FIG. Here, 4b ″ and 4c ″ indicate side walls of the silicon nitride films 4b and 4c removed in the slimming process.
[0024]
This slimming amount is adjusted in accordance with the pattern conversion difference. In the isotropic etching process using heated phosphoric acid, when the thickness of 4b ″ and 4c ″ is 20 nm, the slimming amount is removed in about 6 minutes. The amount is highly controllable. At this time, the tops of the silicon nitride films 4a ′ and 4b ′ are also removed by the slimming amount, and at the same time, the corners of the upper peripheral region of the tops are removed. As a hard mask for forming the gate electrode, Since the removal of the top does not have any influence, there is no problem in the gate electrode formation process.
[0025]
Next, a wet etching process using hydrofluoric acid is used to selectively remove the BPSG oxide film 5a shown in FIG. 2D, and the silicon nitride films 4a ', 4b' and 4c 'are used as hard masks and RIE is used. If the polysilicon film 3 is anisotropically etched, as shown in FIG. 2E, the gate length of the polysilicon 3a inside the cell array and the gate length of the polysilicon 3c 'inside the peripheral circuit are set to the polysilicon inside the cell array. The gate length of 3a can be set to an independent value.
[0026]
In FIG. 2E, the slim amount of the polysilicon 3b 'is about halfway between the polysilicons 3a and 3c'. Thus, the MOS transistor at the end of the cell array as a dummy transistor has a particularly high speed inside the cell array. What is necessary is just to use for the part which does not require switching operation.
[0027]
<Second Embodiment>
Next, with reference to FIG. 3, a second embodiment will be described. In the second embodiment, as an application example of the first embodiment, a case where the above-described slimming process is used for manufacturing a semiconductor memory will be described more specifically. FIG. 3 is a diagram showing a cross-sectional structure along the bit line direction of a cell array of a semiconductor memory in which trench capacitors and switching transistors are regularly arranged.
[0028]
In the cross-sectional structure of the cell array shown in FIG. 3, a trench (DT) is formed in a silicon substrate using RIE anisotropic etching, a dielectric film 6 of a trench capacitor is formed so as to cover the inner wall, and a dielectric A storage electrode 7 of a memory cell made of polysilicon is formed so as to fill the inside of the trench covered with the film 6. This storage electrode 7 is connected to the source of the switching transistor through an N ⁺ region 8 formed in the upper part of the trench.
[0029]
2 is a gate insulating film (SiO ₂ ) of the switching transistor, 3a is a gate electrode (polysilicon) of the switching transistor, and 4a ″ is a hard mask for forming a gate electrode made of the silicon nitride film (SiN) shown in FIG. This is a silicon nitride film including a gate side wall insulating film formed so as to cover the upper and side walls of 4a 'and the side wall of the gate electrode 3a.
[0030]
A bit line (Mφ; hereinafter φ is a symbol meaning zero) is a self-resonant film formed between the gate electrodes 3a using the silicon nitride film 4a ″ including the gate sidewall insulating film as an etching protective film (mask). It is connected to the drain of the switching transistor through an align contact (CB).
[0031]
As described above with reference to FIG. 2E, the silicon nitride film 4a ′ has been described in which the top is etched and the corners around the top are removed in the slimming process. Therefore, as shown in FIG. 3, the silicon nitride film 4a ″ including the gate sidewall insulating film also has a structure in which corners around the upper part are removed. This structure is based on the following device configuration. Produces the advantage of
[0032]
That is, in the next step of forming the interlayer insulating film 9, problems such as abnormal growth are usually likely to occur at the corners, and the stress distribution becomes non-uniform in the vicinity, which causes defects, but the silicon nitride film 4a By removing the corners around the upper portion of ″, the stress concentration at the corners is alleviated, and the generation of defects in the vicinity of the corners can be suppressed.
[0033]
It goes without saying that such an advantage is also effective when another material film is directly laminated on the silicon nitride film 4a ′ shown in FIG. The removal of the corners around the upper portion of the silicon nitride film 4a ″ has no adverse effect on the self-aligned contact (CB) formation process between the gate electrodes 3a.
[0034]
<Third Embodiment>
Next, a third embodiment will be described with reference to FIG.
In the third embodiment, the mutual arrangement state between the memory cell portion in which the switching transistors are densely formed in the semiconductor memory and the transistors formed in isolation in the sense amplifier portion included in the peripheral circuit, and the first A use state of the dummy transistor formed at the end portion of the memory cell portion described in the embodiment will be described.
[0035]
FIG. 4 shows a memory cell unit in which switching transistors and trench capacitors that have undergone the slimming process described in the first and second embodiments are regularly arranged in a row direction and a column direction, and a memory cell unit via a bit line. 2 is a diagram illustrating a planar structure of a sense amplifier unit that exchanges stored information with each other. FIG.
[0036]
The planar structure of the semiconductor memory shown in FIG. 4 includes a trench DT, a gate electrode (GC) in which a gate electrode of a switching transistor is continuously formed, a source / drain diffusion layer (AA) of the switching transistor, and a second layer. A wiring (Mφ), a self-aligned contact (CB) that connects the source of the switching transistor and the second layer wiring (Mφ), and a contact that connects the gate electrode (GC) and the second layer wiring (Mφ) ( Cφ), and contacts (CA) connecting the source / drain diffusion layers (AA) and the second-layer wiring (Mφ).
[0037]
In the memory cell portion of FIG. 4, the gate electrodes (GC) formed continuously in the row direction are connected as word lines to the row decoder via the second layer wiring (Mφ). In addition, the bit line formed of the second layer wiring (Mφ) connected to the source of the switching transistor via the self-aligned contact (CB) is drawn in the column direction of the memory cell portion, and constitutes a sense amplifier Connected to.
[0038]
In FIG. 4, between a memory cell portion in which a continuous dense gate electrode (GC) is formed in a line & space shape and a sense amplifier portion in which one gate electrode (GC) is formed as an isolated pattern. Inevitably causes a large pattern conversion difference based on the micro-loading effect of RIE.
[0039]
At this time, if the slimming process of the present invention is used, the target pattern dimension is matched with the minimum dimension pattern, the dimension on the mask and the process conditions are strictly set, and the pattern conversion difference in other parts is reduced in a short time. It can be easily solved by adding a simple wet etching process.
[0040]
At this time, the amount of slimming at the end of the memory cell portion is about ½ of the isolated pattern, and the gate length is somewhat uncertain compared to the gate electrode (GC) inside the memory cell portion set strictly. As shown as a dummy in FIG. 4, if this is used as the gate of the select transistor grounded through the well, the operation speed of the semiconductor memory is not adversely affected.
[0041]
In addition, this invention is not limited to said embodiment.
In each of the above-described embodiments, the case where the slimming process of the present invention is applied to the gate electrode forming process of the MOS transistor has been described. However, the invention does not necessarily depend on the level of the wiring layer, and the wiring layer of any level is used. The same can be applied to this.
[0042]
In addition, the present invention is always effective when a certain difference is imparted with good controllability to the processing dimensions of the dense and sparse portions of the pattern shape. For example, in a memory / logic mixed LSI, an excellent effect is exhibited even when the gate length of a logic circuit portion that requires high speed operation is smaller than the gate length of a memory cell portion.
[0043]
In each of the embodiments described above, the case where polysilicon is used as the material for the gate electrode on the silicon substrate and the silicon nitride film is used as the hard mask material for forming the gate electrode has been described. However, the present invention is not limited to these materials. Is not to be done. For example, as a material for the gate electrode, a polysilicon film or a metal film or a laminated film of a polysilicon film and a metal film can be used.
[0044]
In addition to the silicon nitride film, a silicon oxide film, a stacked film of a silicon nitride film and a silicon oxide film, and a silicon oxynitride film can be used as a hard mask material for forming the gate electrode. As a buried oxide film used in the hard mask slimming process, PSG (Phosphorous-
Silicate-Glass) can be used.
[0045]
Thus, the slimming process of the present invention can be applied to the manufacture of any device that combines materials that are selective to dry etching and wet etching. In addition, various modifications can be made without departing from the scope of the present invention.
[0046]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, a pattern conversion difference caused by the density of device patterns formed on a semiconductor substrate can be easily reduced by adding a short wet etching process. Is possible.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 is a process cross-sectional view illustrating the continuation of the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 3 is a cross-sectional view showing a structure of a memole cell portion of a semiconductor memory according to a second embodiment.
FIG. 4 is a plan view showing a layout of a semiconductor memory according to a third embodiment.
FIG. 5 is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Gate oxide film 3 ... Polysilicon film 3a, 3b, 3c, 3b '... Polysilicon gate 4a, 4b, 4c, 4a', 4b ', 4c' ... Silicon nitride film mask 4b ", 4c" ... Slim amount 5 ... BPSG film 5a ... Residual BPSG film 6 ... Capacitor dielectric film 7 ... Polysilicon buried storage electrode 8 ... N ⁺ connection region 9 ... Interlayer insulating film DT ... Trench GC ... Gate electrode CB ... Self-aligned contact Mφ ... Second-layer wiring AA ... Source / drain diffusion layer CA ... Mφ-AA contact Cφ ... GC-Mφ contact

Claims (7)

Forming a pattern of the second film so as to have a sparse part and a dense part on the first film formed on the semiconductor substrate;
The first, so as to cover the second layer, comprising the steps that form the first, high etch rate than the second layer a third layer,
A first etching step of removing the third film in the sparse part and simultaneously removing the third film in the dense part until the second film is exposed ;
Selectively removing the surface of the second film using the third film remaining in the dense portion in the first etching step as a mask;
Removing the third film remaining in the dense part in the first etching step;
A second etching step of etching the first film using the second film as a mask;
A method for manufacturing a semiconductor device, comprising:   In the step of forming the third film, the thickness of the third film in the sparse part of the pattern of the second film is the first film formed in the step of etching the first film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the space width is 50% to 100% of the dense portion of the pattern shape. The pattern of the second film is a line pattern having a constant width, and the width of the isolated pattern in the sparse part of the line pattern formed on the semiconductor substrate is the density of the line pattern formed on the semiconductor substrate. the method according to claim 1, wherein the equivalent der Rukoto the width in section. The line pattern is a line pattern forming a gate of a MOS transistor on the semiconductor substrate,
The first film is a polysilicon film, a metal film, or a laminated film of the polysilicon film and the metal film formed on a semiconductor substrate through a gate insulating film, and the second film is a silicon nitride film 4. A film, a silicon oxide film, a laminated film of a silicon nitride film and a silicon oxide film, or a silicon oxynitride film, and the third film is a PSG film or a BPSG film. Manufacturing method of the semiconductor device. Comprising a first film which is patterned on the semiconductor substrate, and a second film made form on said first layer, said first and a third layer covering the second layer,
The pattern of the first and second films consists of a sparse part and a dense part,
The second film patterned in the dense part has a corner around its upper part removed.   6. The semiconductor device according to claim 5, wherein a memory cell array is formed in a dense portion of the pattern, and a peripheral circuit of the memory cell array is formed in a sparse portion of the pattern.   7. The semiconductor device according to claim 6, wherein a logic device mixedly mounted on the same chip as the semiconductor memory device including the memory cell array and the peripheral circuit is further formed in the sparse part of the pattern.

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