JP3971509B2 - Processor - Google Patents

Description

このプログラム例では、左から命令アドレス、命令、コメントを示している。
命令アドレスは３２ビットアドレス中の下位１６ビットのみを１６進数で、命令はニーモニック形式で、コメントは；以下に命令内容の簡単な説明を記している。
【００３６】
このプログラムでは、登録命令（setlb）の次の命令（add a,b,c）から高速ループ命令（lcc L）までの処理は、３回繰り返されるループ処理になっている。
図７では、横軸をサイクル単位の時間軸とし、縦軸のＩＦ（ステージ）欄は、ＦＩＢ１４２に保持されている先頭命令を示している。ただし、サイクル８、９、１３、１４ではＢＩＲ１７１に保持されている先頭命令を示している。ＤＥＣ（ステージ）欄は、ＤＩＢ１５２に保持されている解読中の命令を示す。ＥＸ（ステージ）欄は、命令実行部１６において実行中の命令を示している。
【００３７】
同図において、分岐先登録命令（setlb）が解読されると（サイクル３）、解読ステージ（サイクル３）において、ＦＩＢ１４２からＢＩＲ１７１に４バイト分の命令コード（add命令とmul命令）が転送され、さらに実行ステージ（サイクル４）においてＤＩＣ１５１からＢＡＲ１７２に（解読中の命令アドレス）＋４というアドレスが転送される。このとき、ＢＡＲ１７２には、1007（1003＋4）つまり、(add i,1,i)のアドレスが格納される。
【００３８】
この後、高速ループ命令（lcc）が解読されると（サイクル８）、その実行ステージ（サイクル９）において、ＢＩＲ１７１からＤＩＢ１５２に４バイト分の命令コードが転送され、ＢＡＲ１７２からＦＩＣ１４１にアドレスが転送される。これにより、ＦＩＣ１４１には、ＢＩＲ１７１の４バイト分に命令コードに後続する命令のアドレスが格納される。
【００３９】
また、サイクル１３における高速ループ命令についても同様である。
このように、本プロセッサでは、ＤＩＣ１５１は、常に解読中の命令のアドレスに４を加算したアドレスを保持しているため、登録命令（setlb）の実行に際して、分岐先のフェッチアドレスを求めるのに４を加算する加算器を不要にしている。
【００４０】
また、高速ループ命令（lcc）による分岐に際して、ＦＩＣ１４１とＤＩＣ１５１はいずれもＢＡＲ１７２からの同じアドレスが転送されるので、ＦＩＣ１４１とＤＩＣ１５１とに対して個別にアドレス計算を行なう必要がないので、ここでも加算器（減算器）を不要にしている。
＜第２の実施形態＞
図８は、本発明の第２の実施形態におけるプロセッサの構成を示すブロック図である。
【００４１】
同図の構成は、図１と比べてＦＩＣ（フェッチ命令カウンタ）１４１の代わりにＦＩＣ２４１を、ＤＩＣ１５１の代わりにＤＩＣ２５１を備える点が異なっている。この差異により、同図の構成は、アドレス指定を伴う命令を実行した場合に、図１の構成では命令実行部１６によってＤＩＣ１５１に保持されるべきアドレスを算出していたのに対して、命令実行部１６ではなく命令フェッチ部２４においてＤＩＣ１５１に保持されるべきアドレスを計算するように構成されている。これ以外は第１の実施形態と同じなので、以下異なる点を中心に説明する。
＜フェッチ命令カウンタ２４１の詳細構成＞
図９は、フェッチ命令カウンタ２４１及び解読命令カウンタ２５１の詳細な構成を示すブロック図である。
【００４２】
フェッチ命令カウンタ２４１は、加算器９１、ラッチ９２、セレクタ９３から構成される。
加算器９１、ラッチ９２、セレクタ９３からなるループ回路は、４ずつカウントアップするカウンタを構成している。命令フェッチ部２４は、ＦＩＢ１４２に４バイト以上の空きが存在する場合に、４バイト分の命令コードのフェッチを行い、ＦＩＣ１４１をカウントアップする。
【００４３】
セレクタ９３は、通常（分岐しない場合）は、加算器９１の加算結果を選択し、高速ループ命令以外の分岐命令が実行された場合は実行部１６から供給される分岐先アドレスを、高速ループ命令が実行された場合にはＢＡＲ１７２から供給されるフェッチアドレスを選択し、加算器９１に出力する。ラッチ９２の出力は、フェッチアドレスとして外部メモリ１１に供給される。
＜解読命令カウンタ２５１の詳細構成＞
図９において、ＤＩＣ２５１は、加算器１０１、ラッチ１０２、セレクタ１０３、セレクタ１０４から構成される。
【００４４】
加算器１０１、セレクタ１０３、ラッチ１０２からなるループ回路は、解読ステージ毎に、解読された命令語長ずつカウントアップするカウンタを構成している。
加算器１０１は、解読ステージの後半で、ラッチ１０２の内容に解読された命令語長を加算し、ＤＩＣ２５１を参照する命令（高速分岐命令以外の分岐命令など）の実行時には、ラッチ１０２の内容に”−４”を加算した値を出力する。
ラッチ１０２は、解読中の命令アドレスとシフト値”４”との和を保持する。また、ラッチ１０２は、初期化時には、ＦＩＣ２４１から与えられる（スタートアドレス＋４）を保持する。
【００４５】
セレクタ１０３は、通常は命令解読部２５から与えられる命令語長を選択し、相対アドレス指定を伴う命令やサブルーチンコール命令の実行時には、シフト値の調整用の”−４”を選択する。
セレクタ１０４は、通常は加算器１０１の加算結果を選択し、高速分岐命令の実行に際してＢＡＲ１７２の出力を選択し、他の分岐命令の実行に際してＦＩＣ２４１からの出力（加算器９１からの（分岐先アドレス＋４））を選択する。
＜分岐先アドレスの計算＞
図１０は、アドレス指定を伴う命令のオペレーション内容を示す図である。同図では、図６と同様に単純分岐命令（branch abs_adrs）、サブルーチンコール命令（call abs_adrs）、サブルーチンからのリターン命令（ret）を、単純分岐命令（branch rel_adrs）記してある。なお、図１０中の破線より上のオペレーションは解読ステージにおいて、破線より下のオペレーションは実行ステージにおいて実行されることを意味する。
【００４６】
単純分岐命令（branch abs_adrs）の場合、命令実行部１６が、絶対アドレス（abs_adr）をＦＩＣ２４１に格納し（オペレーション１００１）、さらに命令フェッチ部２４内の加算器９１がＦＩＣ２４１に一定数４を加算し、その加算値をＤＩＣ２５１に格納する（１００２）。このように、絶対アドレスで分岐先が指定される分岐命令に対しては、命令フェッチ部２４内の加算器９１を利用してシフト値”４”を加算しするように構成されている。
【００４７】
サブルーチンコール命令の場合、命令実行部１６は絶対アドレス（abs_adr）をＦＩＣ２４１に格納し（１００３）、加算器１０１は、ＤＩＣ２５１に命令語長を加算（１００４）した後ＤＩＣ２５１の値から４を減算し、命令実行部１６がその減算値をスタックにプッシュし（１００５）、さらに加算器９１においてＦＩＣ２４１に一定数４を加算した値をＤＩＣ２５１に格納する（１００６）。このように、スタックにプッシュする戻り先アドレスの計算におけるシフト値”４”の調整は、ＤＩＣ２５１内の加算器１０１を利用し、ＤＩＣ２５１の更新におけるシフト値の調整は、ＦＩＣ２４１内の加算器９１を利用している。
【００４８】
リターン命令の場合、命令実行部１６は、スタックからサブルーチンコール命令の次の命令のアドレスをポップし（１００７）、そのアドレスをＦＩＣ２４１に格納し、さらにそのアドレスに４を加算し、加算値をＤＩＣ２５１に格納する（１００８）。このように、リターン命令に対しては、シフト値”４”の調整は、ＦＩＣ２４１内の加算器９１を利用している。
【００４９】
また、相対アドレス指定を伴う単純分岐命令（branch rel_adrs）の場合、命令実行部１６は、加算器１０１によりＤＩＣ２５１に”−４”加算された値と、命令で指定された相対アドレス（abs_adr）とを加算し、その加算結果をＦＩＣ２４１に格納し（１００９）、さらに、加算器９１によりＦＩＣ２４１に”４”加算された値をＤＩＣ２５１格納する（１０１０）。このように、相対アドレスで分岐先が指定される分岐命令に対するシフト値の調整は、ＤＩＣ２５１内の加算器１０１と、ＦＩＣ２４１内の加算器９１とを利用している。
【００５０】
上記のように、本実施例のプロセッサは、図１０における１００２、１００６、１００８、１０１０のオペレーションは、ＦＩＣ２４１内の加算器９１を利用してシフト値”４”の加算を行い、１００５、１００９のオペレーションはＤＩＣ２５１内の加算器１０１を利用してシフト値”４”の減算を行っている。
＜分岐タイミング＞
図１１は、相対分岐命令（branch rel_adrs）の動作タイミングを示すタイムチャートである。
【００５１】
同図においてサイクルＴ１、Ｔ２はそれぞれ上記相対分岐命令（branch rel_adrs）の命令解読ステージ、命令実行ステージに相当する。また、サイクルＴ３、Ｔ４は、それぞれ分岐先命令の命令フェッチステージ、命令解読ステージに相当する。
サイクルＴ１において、加算器１０１は（ＤＩＣ２５１−４）を計算し、さらに、サイクルＴ２において命令実行部１６はその計算結果に相対アドレス（rel_adrs）を加算することにより分岐先アドレス（ＢＡ）を算出する。
【００５２】
サイクルＴ３において、ＦＩＣ２４１には分岐先アドレス（ＢＡ）が外部メモリ１１に出力され、分岐先の命令コード（３２ビット分）がフェッチされる。サイクルＴ３の後半で加算器９１は（ＦＩＣ２４１＋４）を計算する。
サイクルＴ４において、加算器９１の計算結果がＤＩＣ２５１及びＦＩＣ２４１に格納される。
【００５３】
なお、上記各実施形態におけるプロセッサは、処理単位を３２ビットとして説明したが、本発明を適用するには、１６ビットでも６４ビットでもよい。また、ＢＩＲ１７１のサイズを４バイト（３２ビット）としたが、このサイズは、高速ループ命令による分岐後にそのサイズ分の命令コードを解読し終えるまでに、少なくとも１命令をフェッチするだけのサイクルを保証できればよい。
【００５４】
また、上記各実施形態では、プログラムが可変語長命令から構成されることを前提としたが、固定語長のプログラムであってもよい。その場合、ＤＩＣ１５１、選択部１４３はより簡単な構成にすることができる。
また、図４に示したＢＩＲ１７１の構成ではキュー１７１ａ（リングバッファ）を用いているが、ＢＩＲ１７１に格納された４バイト分の命令コードのうち、任意のバイトを先頭として出力する構成としてもよい。この場合のキュー１７１ａの他の構成例を図１２に示す。同図では、図４のＢＩＲ１７１においてキュー１７１ａの代わりに４バイトのレジスタ１２０とセレクタ１２１ａ〜１２１ｄとを備える構成としている。セレクタ１２１ａ〜１２１ｄの選択論理を図１３に示す。図１２、１３に示すように、レジスタ１２０に４バイトの命令コード（Ａ、Ｂ、Ｃ、Ｄ）が格納されている場合、有効バイト数が４であれば、セレクタ１２１ａ〜１２１ｄは、Ａ、Ｂ、Ｃ、Ｄと配列された３２ビットを出力する。この３２ビットは、図４に示したセレクタ１４３ａ〜１４３ｄを介してＤＩＢ１５２に格納される。
【００５５】
また例えば、有効バイト数が３であれば、セレクタ１２１ａ〜１２１ｄは、ＢＣＤＡと配列された３２ビットを出力する。この出力は、図４に示したセレクタ１４３ａ〜１４３ｄによって有効バイト（３バイトＢＣＤ）のみが選択される。このとき、セレクタ１４３ａ〜１４３ｄは、この３バイト（ＢＣＤ）を上位側とし、ＦＩＢ１４２から１バイトを下位側とした４バイトを出力する。また、有効バイト数が２、１の場合も同様である。
【００５６】
図１２の構成は、図４と比べてシフト動作の代わりに選択動作をすることになるので、より高速な動作が可能である。
【００５７】
【発明の効果】
本発明のプロセッサは、メモリからコードをフェッチするフェッチ部と、フェッチされたコード中の命令を解読する解読部と、解読された命令を実行する実行部とを有し、プログラムループの直前に配置された登録命令と、プログラムループの末尾に配置されたループ命令とを用いて、高速にループ処理を実行するプロセッサであって、
前記解読部は、解読中の命令を指すポインタとして、解読中の命令のアドレスに一定のシフト値を加算した値を保持及び更新する解読命令カウンタを備え、
前記実行部は、解読部により前記登録命令が解読された場合に、フェッチ部によりプリフェッチされたプログラムループ先頭のコードを第１バッファに、解読命令カウンタに保持されているポインタを第２バッファに登録する登録手段と、解読部により前記ループ命令が解読されかつ分岐が成立する場合に、第２バッファに登録されたポインタをフェッチアドレスとして前記フェッチ部にフェッチさせ、第１バッファに登録されたコードを解読部に解読させる高速分岐手段とを備え、
前記シフト値は、第２バッファに格納されたポインタが、第１バッファに格納されたコードに後続するコードのアドレスを指すように定められている。
【００５８】
ここで、前記一定のシフト値は、第１バッファの記憶領域サイズに等しい構成としてよい。
ここで、前記解読命令カウンタは、初期化時には、スタートアドレスと前記シフト値とを和を保持するようにしてもよい。
この構成によれば、解読命令カウンタに実際に解読中の命令のアドレスに所定の値を加算したポインタを格納することによって、従来必要だった分岐情報登録命令実行時のアドレス加算と、ループ命令実行時のアドレス減算の処理が不要になり、これらの処理に必要な加算器および減算器も不要になり、その結果ハードウェア規模を削減できるという効果がある。分岐情報登録命令及びループ命令実行時にアドレス計算が不要であるため、これらの実質的な処理時間を短縮することができる。
【００５９】
ここで、前記実行部は、さらに、絶対アドレス指定を伴う分岐命令が解読部により解読された場合、当該絶対アドレスをフェッチ命令カウンタに転送し、当該絶対アドレスに前記シフト値を加えた値を解読命令カウンタに転送する分岐手段を備える構成としてもよい。
また、前記分岐手段は、さらに、相対アドレス指定を伴う分岐命令が解読部により解読された場合、当該相対アドレスと解読命令カウンタに保持されたポインタとを加算した値を解読命令カウンタに転送し、その加算値から前記シフト値を減算した値をフェッチ命令カウンタに転送するように構成してもよい。
【００６０】
この構成によれば、解読命令カウンタに保持されたポインタを用いて、絶対アドレスまたは相対アドレス指定を伴う分岐命令を実行する。
ここで前記フェッチ命令カウンタは、フェッチアドレスを保持するレジスタと、レジスタの値をインクリメントする加算器とを含み、前記分岐手段は、絶対アドレス指定を伴う分岐命令が解読部により解読された場合に、前記絶対アドレスに前記シフト値を加えた値の計算を、前記フェッチ命令カウンタ内の加算器に実行させ、その加算結果を解読命令カウンタに転送するようにしてもよい。
【００６１】
この構成によれば、絶対アドレス指定を伴う分岐命令に対して、解読命令カウンタに格納すべきポインタの算出を、実行部の資源を占有しないで、フェッチ命令カウンタ内の加算器を用いて行なうことができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態におけるプロセッサの構成を示すブロック図である。
【図２】解読命令カウンタの詳細な構成を示す図である。
【図３】命令実行ステージにおける処理内容を示すフローチャートである。
【図４】選択部１４３および分岐先命令記憶部１７１の詳細な構成を示すブロック図である。
【図５】選択部１４３の選択制御論理を示す図である。
【図６】アドレスを伴う命令のオペレーション内容を示す図である。
【図７】プロセッサによってループ処理を実行した場合のパイプラインの状態を示す図である。
【図８】本発明の第２の実施形態におけるプロセッサの構成を示すブロック図である。
【図９】フェッチ命令カウンタ２４１及び解読命令カウンタ２５１の詳細な構成を示すブロック図である。
【図１０】アドレス指定を伴う命令のオペレーション内容を示す図である。
【図１１】相対分岐命令（branch rel_adrs）の動作タイミングを示すタイムチャートである。
【図１２】図４のキューの他の構成例を示す。
【図１３】図１２におけるセレクタの選択論理を示す。
【符号の説明】
１１ 外部メモリ
１３ プロセッサ
１４ 命令フェッチ部
１５ 命令解読部
１６ 命令実行部
１７ 分岐先情報記憶部
２４ 命令フェッチ部
２５ 命令解読部
３１ 加算器
３２ レジスタ
３３ セレクタ
９１ 加算器
９２ ラッチ
９３ セレクタ
１０１ 加算器
１０２ ラッチ
１０３ セレクタ
１０４ セレクタ
１２０ レジスタ
１２１ａ〜１２１ｄ セレクタ
１４１ フェッチ命令カウンタ
１４２ フェッチ命令バッファ
１４３ 選択部
１４３ａ〜１４３ｄ セレクタ
１５１ 解読命令カウンタ
１５２ 解読命令バッファ
１５３ 命令デコーダ
１７１ 分岐先命令記憶部
１７１ａ キュー
１７１ｂ 選択制御部
１７２ 分岐先フェッチアドレス記憶部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a processor that executes a machine language instruction sequence by pipeline processing, and more particularly to a processor that executes branch processing at high speed.
[0002]
[Prior art]
Pipeline processing is one of the basic technologies for speeding up processing in a CPU (hereinafter referred to as a processor). Pipeline processing is a technique for improving the processing speed by dividing the processing process of one instruction into a plurality of small processing units (pipeline stages) and performing the processing of each stage in parallel. However, when a branch instruction is executed in loop processing or the like, pipeline installation (disturbance) occurs, and the effective performance of the pipeline processing falls below the ideal performance. This phenomenon is called a branching hazard.
[0003]
The following is a specific example of a program in which a branch hazard occurs. ; Comment below.
(Instruction 1) mov 0, i; 0 is transferred to i
L :; Label indicating the branch destination
(Instruction 2) add a, b, c; Store the sum of a and b in c
(Instruction 3) mul a, b, d; Stores a product of b in d
(Command 4) add i, 1, i; Add 1 to i
(Command 5) cmp i, 3; Compare i and 3
(Instruction 6) bcc L; Comparison result is i If <3, branch to L
The above program describes a loop process in which the processes from instruction 2 to instruction 5 are repeated three times. In this program, the instruction 2 is newly fetched in the next cycle in which the instruction 6 (bcc) is executed, the instruction 2 is further decoded in the next cycle, and the instruction 2 is executed in the next cycle. As a result, a two-cycle branch hazard occurs between the execution of instruction 6 and instruction 2.
[0004]
As a technique for avoiding such a branch hazard, there is a processor disclosed in Japanese Patent Laid-Open No. 8-314719.
In this processor, immediately before the start of the loop processing, the program code at the head of the loop processing is registered in the buffer. Further, at the time of branching from the instruction at the end of the loop to the head of the loop in the loop processing, the program code at the head of the loop processing is taken out from the buffer, and is decoded and executed. According to this, it is not necessary to newly fetch the program code at the beginning of the loop processing from the memory at the time of branching from the end of the loop processing to the beginning, so that the branch hazard is successfully avoided.
[0005]
[Problems to be solved by the invention]
However, according to the above-described conventional processor, a special circuit for avoiding the branch hazard is required, so that there is a problem that the circuit scale is large.
Specifically, first, the processor registers the program code at the head of the loop process in the buffer immediately before the start of the loop process, and at the same time, calculates the address following the program code as a new fetch address. Therefore, a dedicated adder was required. The fetch address calculated by the adder is stored in the address buffer.
[0006]
Second, when the processor branches from the end of the loop processing to the head, the fetch address is fetched from the address buffer, and at the same time, a dedicated subtractor is used to calculate the instruction address being decoded from the fetch address. Needed.
As described above, the conventional processor requires a dedicated adder and subtracter, which increases the hardware scale.
[0007]
An object of the present invention is to provide a pipeline processor that realizes reduction of branch hazards with a small circuit scale.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, a processor of the present invention includes a fetch unit that fetches a code from a memory, a decryption unit that decrypts an instruction in the fetched code, and an execution unit that executes the decrypted instruction. A processor that executes loop processing at high speed using a registration instruction arranged immediately before the program loop and a loop instruction arranged at the end of the program loop,
The decoding unit includes a decoding instruction counter that holds and updates a value obtained by adding a certain shift value to the address of the instruction being decoded as a pointer to the instruction being decoded,
The execution unit registers, in the first buffer, the code at the head of the program loop prefetched by the fetch unit in the first buffer and the pointer held in the decoding instruction counter when the registration command is decoded by the decoding unit. When the loop instruction is decoded by the decoding unit and the branch is taken, the fetch unit uses the pointer registered in the second buffer as a fetch address to fetch the code registered in the first buffer. A high-speed branching means for causing the decoding unit to decode,
The shift value is determined so that the pointer stored in the second buffer points to the address of the code following the code stored in the first buffer.
[0009]
Here, the fixed shift value may be equal to the storage area size of the first buffer.
Here, the decoding instruction counter may hold the sum of the start address and the shift value at the time of initialization.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
<First Embodiment>
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a processor according to an embodiment of the present invention. In addition to the processor, FIG. 1 also shows an external memory 11 that stores an instruction sequence (program) to be processed by the processor.
[0011]
The processor 13 fetches an instruction from the external memory 11, decodes and executes the instruction one by one, and in particular, loop processing specified by a combination of a branch destination information registration instruction (hereinafter referred to as a registration instruction) and a high-speed loop instruction Is configured to process at high speed with a small hardware scale.
Here, the registration instruction is an instruction that is arranged immediately before the head instruction of the loop processing in the program and registers one or more instructions (or instruction codes) at the head of the loop processing in the processor. The high-speed loop instruction is an instruction that is arranged at the end of the loop processing and instructs to branch to the top instruction of the loop processing when the condition is satisfied using an instruction registered in the processor. The registration instruction and the high-speed loop instruction are expressed as “setlb” and “lcc” in mnemonic format, respectively.
[0012]
Therefore, the processor 13 includes an instruction fetch unit 14, an instruction decoding unit 15, an instruction execution unit 16, and a branch destination information storage unit 17. Each of these units operates in synchronization with a clock signal from a clock generator (not shown). The instruction fetch unit 14, the instruction decoding unit 15, and the instruction execution unit 16 constitute an instruction pipeline and operate in parallel in synchronization with a clock signal.
[0013]
The instruction fetch unit 14 fetches instructions from the external memory 11 and stores them in the fetch instruction buffer 142, and sends the stored instructions to the instruction decoding unit 15. The instruction fetch unit 14 further includes a fetch instruction counter (hereinafter abbreviated as FIC) 141, a fetch instruction buffer (hereinafter abbreviated as FIB) 142, and a selection unit 143.
The FIC 141 holds the address of the instruction to be fetched. This address is sent to the external memory 11, incremented when one fetch is completed, and updated to the address to be fetched next. However, in the execution stage of the above high-speed loop instruction, the fetch address sent from the branch destination information storage unit 17 is updated according to the control signal from the instruction decoding unit 15.
[0014]
The FIB 142 includes a FIFO (First In First Out) memory, and stores an instruction sequence fetched from the external memory 11.
The selection unit 143 selects the branch destination instruction registered in the branch destination information storage unit 17 only when the above high-speed loop instruction is executed, otherwise selects the instruction fetched to the FIB 142 and decodes the instruction. To the unit 15.
[0015]
The instruction decoding unit 15 decodes the instruction sent from the instruction fetch unit 14 and controls signals for controlling operations of the instruction fetch unit 14, the instruction decoding unit 15, the instruction execution unit 16, and the branch destination information storage unit 17. Is output as a decryption result. Therefore, the instruction decoding unit 15 includes a decoding instruction counter (hereinafter abbreviated as DIC) 151, a decoding instruction buffer (hereinafter abbreviated as DIB) 152, and an instruction decoder 153.
[0016]
The DIC 151 holds and updates a value obtained by adding a certain shift value (4 in this embodiment) to the address of the instruction currently being decoded. For this reason, the DIC 151 is initialized to a value obtained by adding the shift value 4 to the initial value (start address) at the time of resetting such as startup. The DIC 151 normally increments the code size of the instruction when decoding of the instruction is completed. As a result, it is updated to a value obtained by adding 4 to the address to be decoded next. However, in the execution stage of the high-speed loop instruction, the address is updated to the address sent from the branch destination information storage unit 17 in accordance with the control signal from the instruction decoding unit 15. The shift value is the same value as the storage size (number of bytes) of the branch destination instruction storage unit 171. If the storage size is 8 bytes, the DIC 151 holds a value obtained by adding 8 as a shift value to the address of the instruction currently being decoded.
[0017]
The DIB 152 includes a register, is sent from the FIB 142, and stores one instruction to be decoded.
The instruction decoder 153 decodes the instruction stored in the DIB 152 and outputs various control signals for controlling the instruction fetch unit 14, the instruction decoding unit 15, the instruction execution unit 16, and the branch destination information storage unit 17 according to the decoding result. . When the decoded instruction uses the address of the DIC 151, the instruction decoder 153 controls the instruction execution unit 16 to adjust (add or subtract) the value of 4 according to the type of instruction. However, this adjustment is not necessary for high-speed loop instructions.
[0018]
The instruction execution unit 16 includes an arithmetic operation circuit (ALU), a shifter, and the like. The instruction execution unit 16 controls an operation designated by the instruction of the processor 13 and each unit according to a control signal sent from the instruction decoding unit 15, and Input / output a connected control signal (not shown).
The branch destination information storage unit 17 stores the branch destination information when the instruction decoding unit 15 decodes the branch destination information registration instruction. Therefore, the branch destination information storage unit 17 includes a branch destination instruction storage unit 171 (hereinafter abbreviated as BIR) and a branch destination fetch address storage unit (hereinafter referred to as BAR) 172.
[0019]
The BIR 171 includes a register. When the instruction decoding unit 15 decodes the branch destination information registration instruction, the BIR 171 reads a 4-byte instruction sequence from the FIB 142 and stores it in the next cycle. As a result, the first 4 bytes of the instruction sequence for loop processing are registered in the BIR 171. The BIR 171 is also called a loop instruction buffer.
The BAR 172 includes a register. When the instruction decoding unit 15 decodes the branch destination information registration instruction, the address is read from the DIC 151 and stored in the next cycle. Since this address is a value obtained by adding the storage size (number of bytes) of the BIR 171 to the address of the instruction being decoded, it means the address of the instruction sequence following the stored contents of the BIR 171. In other words, the stored contents of the BAR 172 are pointers indicating where the instruction fetch unit 14 should fetch after branching by a high-speed loop instruction. The BAR 172 is also called a loop address buffer.
<Detailed configuration of decoding instruction counter>
FIG. 2 shows a specific configuration example of the DIC 151. As shown in the figure, the DIC 151 includes an adder 31, a register 32, and selectors 33 and 34.
[0020]
At initialization by resetting or the like, the adder 31 adds the value (start address) of the reset register 32 and a certain number “4”. The register 32 is initialized by holding the added value.
Normally, the adder 31 adds the instruction word length (number of bytes) and the current value of the register 32 after the instruction decoding unit 15 decodes the instruction. The register 32 is updated to ((address of the next decoding instruction) +4) by holding the added value.
[0021]
When a branch instruction (including a high-speed loop instruction) is executed, the register 32 is updated to a branch destination address input via the selector 33.
<Processing contents of registered instruction and high-speed loop instruction>
FIG. 3 is a flowchart showing processing contents such as a registration command and a high-speed loop command.
[0022]
In the figure, the processing contents are shown separately for a registration instruction arranged immediately before the loop processing, a high-speed loop instruction arranged at the end of the loop processing, and other instructions.
In the figure, when the result of decoding by the instruction decoder 153 indicates a registered instruction (setlb) (step 31), the processor 13 transfers an instruction code for 4 bytes from the head of the FIB 142 to the BIR 171 (step 32). The address held in the DIC 151 is transferred to the BAR 172 (step 33), and when the execution stage cycle ends, execution of the next instruction is started. Thus, the BIR 171 holds the instruction code for the first 4 bytes of the loop process, and the BAR 172 holds the address of the instruction following the 4 bytes of the loop process head.
[0023]
When the result of decoding by the instruction decoder 153 indicates a high-speed loop instruction (lcc) (step 31), the processor 13 branches from the BIR 171 to the DIB 152 at the head of the loop process when branching according to the condition (step 35). The instruction is transferred (step 37), and the address is transferred from the BAR 172 to the DIC 151 and the FIC 141. As a result, the FIC 141 holds the address of the instruction subsequent to the first 4 bytes of the loop processing as the fetch address, and the DIC 151 holds the address of the instruction being decoded plus four. In this case, the instruction fetch unit 14 does not need to newly fetch the instruction at the head of the loop processing that is the branch destination, so that no branch hazard occurs. In addition, the FIC 141 can obtain the address of the instruction following the first 4 bytes of the loop processing by only transferring without requiring any special calculation.
<Detailed Configuration of Selection Unit 143 and Branch Destination Instruction Storage Unit 171>
FIG. 4 is a block diagram showing a detailed configuration of the selection unit 143 and the branch destination instruction storage unit 171.
[0024]
In the figure, in addition to the selection unit 143 and the BIR 171, the FIB 142 is also illustrated. The instructions in the program are assumed to have a variable word length (an integer multiple of 8 bits).
The FIB 142 is configured as a queue (preferably about 16 stages) that shifts the fetched instruction code in units of 8 bits. The FIB 142 outputs the 4 bytes at the head of the queue via the selection unit 143 to the DIB 152 at each cycle of the decoding stage, and the instruction word length (from the head of the 4 bytes) from the instruction decoding unit 15 that has decoded the 4 bytes. Is deleted by shifting the instruction code corresponding to the instruction word length at the head of the queue. As a result, the first byte of the queue usually matches the first byte of one instruction (not necessarily immediately after branching by a fast loop instruction).
[0025]
The BIR 171 includes a queue 171a and a selection control unit 171b.
The queue 171a is configured as a queue (four stages) that shifts in a ring shape in units of 8 bits, stores the first 4 bytes of the FIB 142 when executing the registration instruction, and holds 4 bytes when executing the high-speed loop instruction Is output to the DIB 152 via the selection unit 143, and the instruction word length (the number of bytes from the beginning of the 4 bytes) is given via the selection control unit 171b from the instruction decoding unit 15 that has decoded the 4 bytes. The instruction code for the instruction word length is shifted in a ring shape. This shift operation is repeated after a total of 4 bytes have been shifted and then stopped, and the original state stored by the registration command is restored. In this state, when a branch due to a high-speed loop instruction is made again, the same operation as described above is performed.
[0026]
The selection control unit 171b controls the selection unit 143 to output the 4-byte instruction code stored in the queue 171a instead of the instruction code of the FIC 141 immediately after branching by the high-speed loop instruction. Specifically, in the decoding stage immediately after the branch by the high-speed loop instruction, all 4 bytes are output via the selection unit 143, the queue 171a is shifted according to the instruction word length notified from the instruction decoding unit 15, and the post-shift The number of valid bytes of the instruction code in the queue 171a is counted. Further, in the next decoding stage, the selection unit 143 is controlled according to the number of valid bytes.
[0027]
The selection unit 143 includes selectors 143a to 143d. Immediately after execution of the high-speed loop instruction, the instruction code held in the queue 171a and the instruction code held in the subsequent FIB 142 are combined into 4 bytes. Select as follows.
FIG. 5 shows the selection logic of each of the selectors 143a to 143d. According to this selection logic, the selectors 143a to 143d have a 4-byte portion obtained by concatenating the effective instruction code of the queue 171a and the instruction code of the subsequent FIB 142 in accordance with the number of effective bytes instructed from the selection control unit 171b. Output the instruction code. In FIG. 5, four 8-bit five-input one-output (5to1) selectors are used, but four selectors of 2to1, 3to1, 4to1, and 5to1 may be used.
<Branch instruction processing>
Since the DIC 151 holds a value obtained by adding a fixed number “4” to the instruction address currently being decoded as described above, it is necessary to adjust the fixed number “4” by addition / subtraction for an instruction to read or write the value of the DIC 151. There is. This adjustment is necessary for an instruction other than the high-speed loop instruction and accompanied by addressing.
[0028]
FIG. 6 is a diagram showing the operation contents of an instruction with address designation. In the figure, typical instructions with absolute addressing include simple branch instructions (branch abs_adrs), subroutine call instructions (call abs_adrs), and return instructions from subroutines (ret). A simple branch instruction (branch rel_adrs) is written as an instruction. In the figure, abs_adr indicates a 32-bit absolute address, and rel_adrs indicates an 8- or 16-bit relative address.
[0029]
In the case of a simple branch instruction (branch abs_adrs), the instruction execution unit 16 stores the absolute address (abs_adr) in the FIC 141 (operation 601), adds a fixed number 4 to the absolute address (abs_adr), and adds the added value to the DIC 151. Store (602). As a result, fetching, decoding, and execution are started from the instruction of the designated absolute address. Thus, for a branch instruction whose branch destination is specified by an absolute address, control is performed so that a value obtained by adding 4 to the absolute address is set in the DIC 151.
[0030]
In the case of a subroutine call instruction, the instruction execution unit 16 stores the absolute address (abs_adr) in the FIC 141 (603), adds the instruction word length to the DIC 151, subtracts 4 from the value of the DIC 151, and adds the subtraction value to the stack. Push (604), and store the value obtained by adding a fixed number 4 to the absolute address (abs_adr) in the DIC 151 (605). Here, the subtraction value indicates the address of the instruction being decoded at the time of execution of the subroutine call instruction, that is, the instruction next to the subroutine call instruction. In this way, for the subroutine call instruction, control is performed so that a value obtained by subtracting 4 from the address of the DIC 151 is saved in a stack outside the figure.
[0031]
In the case of a return instruction, the instruction execution unit 16 pops the address of the instruction next to the subroutine call instruction from the stack (606), stores the address in the FIC 141, further adds 4 to the address, and adds the added value to the DIC 151. (607). As described above, for the return instruction, control is performed so as to restore a value obtained by adding 4 to the value saved in the stack (not shown).
[0032]
In the case of a simple branch instruction (branch rel_adrs) with relative address designation, the instruction execution unit 16 adds the relative address (abs_adr) designated by the instruction and the value of the DIC 151 (608), and the addition result is obtained. Further, “−4” is added to the addition result in the DIC 151 and the addition result is stored in the FIC 141 (609). In this way, for a branch instruction whose branch destination is specified by a relative address, control is performed so that a value obtained by subtracting 4 from the value of DIC 151 is set in DIC 151. However, such subtraction is not required for high-speed loop instructions.
[0033]
As described above, for an absolute addressed branch instruction, the update of the DIC 151 may be made +4 to the absolute address, and the update of the FIC 141 may use the absolute address as it is.
In addition, for a branch instruction with a relative address, the DIC 151 can be updated by simply adding (DIC151) + (relative address), not by +4, and the FIC 141 can be updated by (DIC151) + ( Relative address) -4.
[0034]
In any of the above cases, the addition / subtraction of the fixed number 4 is executed by an ALU (Arithmetic Logical Unit) in the instruction execution unit 16. For instructions with address designation other than high-speed loop instructions, the instruction execution unit 16 performs address calculation in the same manner as described above.
<Description of operation>
The operation of the processor according to this embodiment configured as described above will be described using the following program example.
[0035]
FIG. 7 is a diagram illustrating a pipeline state when the following program example is executed.

In this program example, an instruction address, an instruction, and a comment are shown from the left.
Only the lower 16 bits of the 32-bit address are in hexadecimal, the instruction is in mnemonic format, and the comment is; a brief description of the instruction content is given below.
[0036]
In this program, the processing from the instruction (add a, b, c) following the registration instruction (setlb) to the high-speed loop instruction (lcc L) is a loop process that is repeated three times.
In FIG. 7, the horizontal axis is the time axis of the cycle unit, and the IF (stage) column on the vertical axis indicates the head instruction held in the FIB 142. However, in cycles 8, 9, 13, and 14, the first instruction held in the BIR 171 is shown. The DEC (stage) column indicates the instruction being decoded held in the DIB 152. The EX (stage) column indicates an instruction being executed in the instruction execution unit 16.
[0037]
In the figure, when the branch destination registration instruction (setlb) is decoded (cycle 3), the instruction code (add instruction and mul instruction) for 4 bytes is transferred from the FIB 142 to the BIR 171 at the decoding stage (cycle 3). Further, in the execution stage (cycle 4), an address of (instruction address being decoded) +4 is transferred from the DIC 151 to the BAR 172. At this time, 1007 (1003 + 4), that is, an address of (add i, 1, i) is stored in the BAR 172.
[0038]
After that, when the high-speed loop instruction (lcc) is decoded (cycle 8), in the execution stage (cycle 9), the 4-byte instruction code is transferred from the BIR 171 to the DIB 152, and the address is transferred from the BAR 172 to the FIC 141. The As a result, the address of the instruction following the instruction code is stored in the FIC 141 in 4 bytes of the BIR 171.
[0039]
The same applies to the high-speed loop instruction in cycle 13.
In this way, in this processor, the DIC 151 always holds an address obtained by adding 4 to the address of the instruction being decoded. Therefore, when executing the registered instruction (setlb), 4 is used to obtain the branch destination fetch address. The adder which adds is made unnecessary.
[0040]
Further, since the same address from the BAR 172 is transferred to both the FIC 141 and the DIC 151 at the time of branching by the high-speed loop instruction (lcc), it is not necessary to separately calculate the addresses for the FIC 141 and the DIC 151. This eliminates the need for a subtractor.
<Second Embodiment>
FIG. 8 is a block diagram showing a configuration of a processor according to the second embodiment of the present invention.
[0041]
The configuration of FIG. 6 differs from that of FIG. 1 in that an FIC 241 is provided instead of the FIC (fetch instruction counter) 141 and a DIC 251 is provided instead of the DIC 151. Due to this difference, the configuration shown in FIG. 1 executes the instruction execution when the instruction to be addressed is executed, whereas the instruction execution unit 16 calculates the address to be held in the DIC 151 in the configuration shown in FIG. The instruction fetch unit 24, not the unit 16, is configured to calculate an address to be held in the DIC 151. Since other than this is the same as that of the first embodiment, the following description will focus on differences.
<Detailed Configuration of Fetch Instruction Counter 241>
FIG. 9 is a block diagram showing a detailed configuration of the fetch instruction counter 241 and the decryption instruction counter 251.
[0042]
The fetch instruction counter 241 includes an adder 91, a latch 92, and a selector 93.
The loop circuit including the adder 91, the latch 92, and the selector 93 constitutes a counter that counts up by four. The instruction fetch unit 24 fetches an instruction code for 4 bytes and counts up the FIC 141 when the FIB 142 has a space of 4 bytes or more.
[0043]
The selector 93 normally selects the addition result of the adder 91 (when not branching), and when a branch instruction other than the high speed loop instruction is executed, the branch destination address supplied from the execution unit 16 is selected as the high speed loop instruction. Is executed, the fetch address supplied from the BAR 172 is selected and output to the adder 91. The output of the latch 92 is supplied to the external memory 11 as a fetch address.
<Detailed Configuration of Decoding Instruction Counter 251>
In FIG. 9, the DIC 251 includes an adder 101, a latch 102, a selector 103, and a selector 104.
[0044]
The loop circuit including the adder 101, the selector 103, and the latch 102 constitutes a counter that counts up by the decoded instruction word length for each decoding stage.
The adder 101 adds the decoded instruction word length to the content of the latch 102 in the latter half of the decoding stage, and when executing an instruction (such as a branch instruction other than the high-speed branch instruction) that refers to the DIC 251, A value obtained by adding “−4” is output.
The latch 102 holds the sum of the instruction address being decoded and the shift value “4”. The latch 102 holds (start address +4) given from the FIC 241 at the time of initialization.
[0045]
The selector 103 normally selects the instruction word length given from the instruction decoding unit 25, and selects "-4" for adjusting the shift value when executing an instruction accompanied by relative address designation or a subroutine call instruction.
The selector 104 normally selects the addition result of the adder 101, selects the output of the BAR 172 when executing the high-speed branch instruction, and outputs from the FIC 241 (execution of the branch destination address from the adder 91 when executing another branch instruction). +4)) is selected.
<Calculation of branch destination address>
FIG. 10 is a diagram showing the operation contents of an instruction with address designation. In this figure, as in FIG. 6, a simple branch instruction (branch abs_adrs), a subroutine call instruction (call abs_adrs), and a return instruction (ret) from the subroutine are described as simple branch instructions (branch rel_adrs). In FIG. 10, an operation above the broken line means that the operation is executed at the decoding stage, and an operation below the broken line is executed at the execution stage.
[0046]
In the case of a simple branch instruction (branch abs_adrs), the instruction execution unit 16 stores the absolute address (abs_adr) in the FIC 241 (operation 1001), and the adder 91 in the instruction fetch unit 24 adds a fixed number 4 to the FIC 241. The added value is stored in the DIC 251 (1002). As described above, the shift value “4” is added to the branch instruction whose branch address is specified by the absolute address using the adder 91 in the instruction fetch unit 24.
[0047]
In the case of a subroutine call instruction, the instruction execution unit 16 stores the absolute address (abs_adr) in the FIC 241 (1003), and the adder 101 adds the instruction word length to the DIC 251 (1004) and then subtracts 4 from the value of the DIC 251. The instruction execution unit 16 pushes the subtraction value onto the stack (1005), and further stores the value obtained by adding a fixed number 4 to the FIC 241 in the adder 91 in the DIC 251 (1006). As described above, the adjustment of the shift value “4” in the calculation of the return destination address pushed to the stack uses the adder 101 in the DIC 251, and the adjustment of the shift value in the update of the DIC 251 uses the adder 91 in the FIC 241. We are using.
[0048]
In the case of a return instruction, the instruction execution unit 16 pops the address of the instruction next to the subroutine call instruction from the stack (1007), stores the address in the FIC 241, adds 4 to the address, and adds the added value to the DIC 251. (1008). Thus, for the return instruction, the shift value “4” is adjusted using the adder 91 in the FIC 241.
[0049]
Further, in the case of a simple branch instruction (branch rel_adrs) with relative address designation, the instruction execution unit 16 adds the value obtained by adding “−4” to the DIC 251 by the adder 101 and the relative address (abs_adr) designated by the instruction. The addition result is stored in the FIC 241 (1009), and the value obtained by adding “4” to the FIC 241 by the adder 91 is stored in the DIC 251 (1010). As described above, the adjustment of the shift value for the branch instruction whose branch destination is specified by the relative address uses the adder 101 in the DIC 251 and the adder 91 in the FIC 241.
[0050]
As described above, in the processor of this embodiment, the operations 1002, 1006, 1008, and 1010 in FIG. 10 add the shift value “4” using the adder 91 in the FIC 241, and the operations of 1005 and 1009 The operation uses the adder 101 in the DIC 251 to subtract the shift value “4”.
<Branch timing>
FIG. 11 is a time chart showing the operation timing of a relative branch instruction (branch rel_adrs).
[0051]
In the figure, cycles T1 and T2 correspond to the instruction decoding stage and the instruction execution stage of the relative branch instruction (branch rel_adrs), respectively. Cycles T3 and T4 correspond to the instruction fetch stage and instruction decode stage of the branch destination instruction, respectively.
In cycle T1, adder 101 calculates (DIC251-4), and in cycle T2, instruction execution unit 16 calculates a branch destination address (BA) by adding a relative address (rel_adrs) to the calculation result. .
[0052]
In cycle T3, the branch destination address (BA) is output to the FIC 241 to the external memory 11, and the branch destination instruction code (for 32 bits) is fetched. In the second half of the cycle T3, the adder 91 calculates (FIC241 + 4).
In cycle T4, the calculation result of the adder 91 is stored in the DIC 251 and the FIC 241.
[0053]
The processor in each of the above embodiments has been described with the processing unit being 32 bits. However, in order to apply the present invention, it may be 16 bits or 64 bits. The size of BIR 171 is 4 bytes (32 bits), but this size guarantees a cycle that fetches at least one instruction before decoding the instruction code for that size after branching by a high-speed loop instruction. I can do it.
[0054]
In each of the above embodiments, it is assumed that the program is composed of variable word length instructions, but may be a fixed word length program. In that case, the DIC 151 and the selection unit 143 can have a simpler configuration.
Further, although the queue 171a (ring buffer) is used in the configuration of the BIR 171 shown in FIG. 4, an arbitrary byte may be output from the 4-byte instruction code stored in the BIR 171 as the head. Another configuration example of the queue 171a in this case is shown in FIG. In FIG. 4, the BIR 171 shown in FIG. 4 includes a 4-byte register 120 and selectors 121a to 121d instead of the queue 171a. The selection logic of the selectors 121a to 121d is shown in FIG. As shown in FIGS. 12 and 13, when a 4-byte instruction code (A, B, C, D) is stored in the register 120, if the number of valid bytes is 4, the selectors 121a to 121d 32 bits arranged as B, C, and D are output. These 32 bits are stored in the DIB 152 via the selectors 143a to 143d shown in FIG.
[0055]
For example, if the number of valid bytes is 3, the selectors 121a to 121d output 32 bits arranged as BCDA. For this output, only valid bytes (3-byte BCD) are selected by the selectors 143a to 143d shown in FIG. At this time, the selectors 143a to 143d output 4 bytes with the 3 bytes (BCD) as the upper side and the FIB 142 with 1 byte as the lower side. The same applies when the number of valid bytes is 2 or 1.
[0056]
Since the configuration of FIG. 12 performs a selection operation instead of the shift operation as compared with FIG. 4, a higher speed operation is possible.
[0057]
【The invention's effect】
The processor of the present invention has a fetch unit for fetching code from a memory, a decryption unit for decrypting an instruction in the fetched code, and an execution unit for executing the decrypted instruction, and is arranged immediately before the program loop. A processor that executes loop processing at high speed using a registered instruction and a loop instruction arranged at the end of a program loop,
The decoding unit includes a decoding instruction counter that holds and updates a value obtained by adding a certain shift value to the address of the instruction being decoded as a pointer to the instruction being decoded,
The execution unit registers, in the first buffer, the code at the head of the program loop prefetched by the fetch unit in the first buffer and the pointer held in the decoding instruction counter when the registration command is decoded by the decoding unit. When the loop instruction is decoded by the decoding unit and the branch is taken, the fetch unit uses the pointer registered in the second buffer as a fetch address to fetch the code registered in the first buffer. A high-speed branching means for causing the decoding unit to decode,
The shift value is determined so that the pointer stored in the second buffer points to the address of the code following the code stored in the first buffer.
[0058]
Here, the fixed shift value may be equal to the storage area size of the first buffer.
Here, the decoding instruction counter may hold the sum of the start address and the shift value at the time of initialization.
According to this configuration, by storing a pointer obtained by adding a predetermined value to the address of the instruction that is actually being decoded in the decoding instruction counter, it is possible to add an address when executing a branch information registration instruction and execute a loop instruction. This eliminates the need for the time address subtraction process, and eliminates the need for the adder and subtracter necessary for these processes, resulting in the effect of reducing the hardware scale. Since the address calculation is not required when the branch information registration instruction and the loop instruction are executed, the substantial processing time can be shortened.
[0059]
Here, the execution unit further transfers the absolute address to the fetch instruction counter when the branch instruction accompanied by the absolute address designation is decoded by the decoding unit, and decodes the value obtained by adding the shift value to the absolute address. A branching means for transferring to the instruction counter may be provided.
Further, the branch means further transfers a value obtained by adding the relative address and the pointer held in the decode instruction counter to the decode instruction counter when the decode instruction is decoded by the decoding unit, A value obtained by subtracting the shift value from the added value may be transferred to the fetch instruction counter.
[0060]
According to this configuration, a branch instruction with an absolute address or relative address designation is executed using the pointer held in the decoding instruction counter.
Here, the fetch instruction counter includes a register that holds a fetch address and an adder that increments the value of the register, and the branching unit is configured such that when a branch instruction with absolute address designation is decoded by a decoding unit, Calculation of a value obtained by adding the shift value to the absolute address may be executed by an adder in the fetch instruction counter, and the addition result may be transferred to the decoding instruction counter.
[0061]
According to this configuration, for a branch instruction with an absolute address specification, the pointer to be stored in the decoding instruction counter is calculated using the adder in the fetch instruction counter without occupying the resources of the execution unit. Can do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a processor according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a detailed configuration of a decryption instruction counter.
FIG. 3 is a flowchart showing processing contents in an instruction execution stage.
4 is a block diagram showing a detailed configuration of a selection unit 143 and a branch destination instruction storage unit 171. FIG.
FIG. 5 is a diagram showing selection control logic of a selection unit 143;
FIG. 6 is a diagram showing the operation content of an instruction with an address.
FIG. 7 is a diagram illustrating a pipeline state when a loop process is executed by a processor;
FIG. 8 is a block diagram illustrating a configuration of a processor according to a second embodiment of the present invention.
9 is a block diagram showing a detailed configuration of a fetch instruction counter 241 and a decryption instruction counter 251. FIG.
FIG. 10 is a diagram showing the operation contents of an instruction with address designation.
FIG. 11 is a time chart showing the operation timing of a relative branch instruction (branch rel_adrs).
12 shows another configuration example of the queue of FIG.
13 shows selection logic of the selector in FIG.
[Explanation of symbols]
11 External memory
13 processor
14 Instruction fetch section
15 Instruction decoding part
16 Instruction execution part
17 Branch destination information storage unit
24 Instruction fetch section
25 Instruction decoding part
31 Adder
32 registers
33 Selector
91 Adder
92 Latch
93 Selector
101 adder
102 Latch
103 selector
104 selector
120 registers
121a to 121d selector
141 Fetch instruction counter
142 Fetch instruction buffer
143 selection part
143a to 143d selector
151 Decoding instruction counter
152 Decoding Instruction Buffer
153 instruction decoder
171 Branch destination instruction storage unit
171a Queue
171b Selection control unit
172 Branch destination fetch address storage unit

Claims (13)

A program loop having a fetch unit for fetching a code from the memory, a decoding unit for decoding an instruction in the fetched code, an execution unit for executing the decoded instruction, a first buffer, and a second buffer; A processor that executes a loop process at high speed using a registration instruction placed immediately before and a loop instruction placed at the end of the program loop,
The decoding unit is
As a pointer to an instruction in decode, it includes a decoded instruction counter that a value obtained by adding a fixed shift value to the address of the instruction in the decode Soo coercive,
The execution unit is
When the registering instruction is decoded by the decoding unit, the head code of the program loop fetched by the fetching unit is registered in the first buffer, and the pointer held in the decoding instruction counter is registered in the second buffer. Registration means to
When the decoding unit decodes the loop instruction and a branch is taken, the instruction pointed to by the pointer registered in the second buffer is fetched by the fetch unit, and the code registered in the first buffer is High-speed branching means for causing the decoding unit to decode ;
Branching means for transferring the absolute address to the fetch instruction counter and transferring the absolute address plus the shift value to the decoding instruction counter when a branch instruction with absolute address designation is decoded by the decoding unit; Prepared,
The shift value is determined so that, when the registration instruction is decoded, a pointer registered in the second buffer by the registration unit indicates an address of a code subsequent to a code registered in the first buffer. A processor characterized by being. The processor according to claim 1, wherein the constant shift value is equal to a storage area size of the first buffer. The decoded instruction counter, when initialized, the processor of claim 2, wherein the holding the sum of the shift value as a start address. The fetch unit includes an incrementer that updates the fetch address by the same number as the shift value, and the decoding instruction counter outputs an output from the incrementer as the pointer when the fetch address is initialized to a start address. The processor according to claim 3, wherein the processor is held. Further, when a branch instruction with relative address designation is decoded by the decoding unit, the branching means transfers a value obtained by adding the relative address and the pointer held in the decoding instruction counter to the decoding instruction counter, and adds the same. The processor according to claim 1, wherein a value obtained by subtracting the shift value from a value is transferred to a fetch instruction counter. The fetch instruction counter includes a register that holds a fetch address and an adder that increments the value of the register, and the branch unit is configured to output the absolute instruction when a branch instruction with absolute address designation is decoded by a decoding unit. 2. The processor according to claim 1 , wherein a calculation of a value obtained by adding the shift value to an address is executed by an adder in the fetch instruction counter, and a result of the addition is transferred to a decoding instruction counter. Pipeline processing comprising at least three stages, including a fetch unit for fetching code in the fetch stage, a decryption unit for decrypting the fetched instruction in the decryption stage, and an execution unit for executing the decrypted instruction in the execution stage A processor that executes loop processing at high speed using a registration instruction placed immediately before the program loop and a loop instruction placed at the end of the program loop,
The fetch unit
A fetch instruction counter that counts fetch addresses; and a fetch instruction buffer that holds fetched code;
The decoding unit is
An instruction in the fetched code that holds the instruction being decoded;
Holding a pointer to the instruction being decoded , said pointer having a decoding instruction counter which is the sum of the address of the instruction held in the decoding instruction register and a constant shift value;
The execution unit is
A first buffer having an area for holding a code; a second buffer having an area for holding an address; and a code held in a fetch instruction buffer when the registration instruction is decoded by a decoding unit. Registration means for registering the pointer held in the decryption instruction counter in the second buffer;
High-speed branching means for transferring the pointer registered in the second buffer to the fetch instruction counter and transferring the code at the head of the program loop from the first buffer to the decoding instruction register when the loop instruction is decoded and a branch is taken ;
Branching means for transferring the absolute address to the fetch instruction counter and transferring the absolute address plus the shift value to the decoding instruction counter when the branch instruction with the absolute address designation is decoded by the decoding unit. And
The code registered in the first buffer includes the head code of the program loop, the shift value is equal to the size of the first buffer, and the pointer registered in the second buffer is stored in the first buffer. A processor characterized by pointing to the address of a code that follows the code. The processor according to claim 7 , wherein the decoding instruction counter holds a sum of an initial value and the shift value at the time of initialization. The fetch unit includes an incrementer that updates the fetch address by the same number as the shift value, and the decoding instruction counter outputs an output from the incrementer as the pointer when the fetch address is initialized to a start address. The processor according to claim 8, wherein the processor is held. The program loop is composed of instructions of variable word length, and the processor further selects a code corresponding to the size of the decoding instruction buffer from the code held in the fetch instruction buffer and the code held in the first buffer. Selection means for selecting and outputting to the decoding instruction buffer; and a selection control unit for controlling the selection means to select the code of the fetch instruction buffer following the code of the first buffer, and the high-speed branching means includes: A selection control unit is activated when the loop instruction is decoded and a branch is taken, and the selection unit selects a code of a fetch instruction buffer when the selection control unit is not activated. The processor of claim 8 . Further, when a branch instruction with relative address designation is decoded by the decoding unit, the branching means transfers a value obtained by adding the relative address and the pointer held in the decoding instruction counter to the decoding instruction counter, and adds the same. The processor according to claim 7, wherein a value obtained by subtracting the shift value from a value is transferred to a fetch instruction counter. The fetch instruction counter includes an address register that holds a fetch address and a first adder that increments the fetch address of the address register by a predetermined number, and the decoding instruction counter includes a pointer register that holds the pointer; A second adder that increments the pointer of the pointer register by the decoded instruction word length, and the branch means is held in the second register when a branch instruction with relative addressing is decoded. A pointer and a negative number of the shift value are added to the second adder, the sum of the addition result and the relative address is stored in the first register as a branch destination address, and the shift value is set as the predetermined number The branch destination address of the first register and the predetermined number are added to the first adder, and the addition result is The processor of claim 11, wherein the storing the Ntarejisuta. The fetch instruction counter includes a register that holds a fetch address, and an adder that increments the value of the register,
The branching unit causes the adder in the fetch instruction counter to calculate a value obtained by adding the shift value to the absolute address when a branch instruction with absolute address designation is decoded by a decoding unit, The processor according to claim 7, wherein the addition result is transferred to a decoding instruction counter.

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