JP3976573B2 - Timing signal generating circuit, signal transmission system, and timing signal generating method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a timing signal generation circuit, a signal transmission system, and a timing signal generation method, and more particularly to a signal transmission system that transmits and receives signals at high speed between LSIs (Large Scale Integration Circuits) or between devices. The present invention relates to a timing signal generation circuit.
[0002]
In recent years, large-capacity signal transmission has been performed between LSIs or between devices composed of a plurality of LSIs along with the high-speed operation of LSIs. However, in such a large-capacity signal transmission system, signal skew (skew) and jitter become a problem as the transmission speed increases, and if data is not received (captured) at an accurate timing, it is accurate. Signal transmission becomes difficult. Thus, there is a demand for providing a timing signal generation circuit capable of generating a timing signal for reliably receiving data.
[0003]
[Prior art]
In recent years, semiconductor memory devices such as DRAM (Dynamic Random Access Memory) and SDRAM (Synchronous DRAM) and MPU (Micro Processing Unit), or components constituting computers and other information processing equipment have greatly improved their performance. Along with this, it has become necessary to perform high-speed signal transmission / reception (transmission) between LSIs (LSI chips) or between circuit boards and devices composed of a plurality of LSIs.
[0004]
FIG. 1 is a block diagram schematically showing an example of a conventional signal transmission system. In FIG. 1, reference numeral 101 is a transmission side drive circuit (transmission side buffer) for clock CLK, 102 is a wiring for clock (clock signal line), 103 is a reception side drive circuit for clock (reception side buffer), 110 ˜11n are transmission side data fetch circuits (transmission side latches) for data D0 to Dn, 120 to 12n are transmission side drive circuits (transmission side buffers) for data D0 to Dn, and 130 to 13n are wirings for data (data (Signal lines), 140 to 14n are reception side drive circuits (reception side buffers) for data, and 150 to 15n are reception side data fetch circuits (reception side latches).
[0005]
As shown in FIG. 1, the signal transmission system in the case where the amount of data is large conventionally transmits signals using a plurality of signal lines 102 and 130 to 13n, for example. That is, the data (signals) D1 to Dn are transmitted to the reception side buffers 140 to 14n via the transmission side latches 110 to 11n, the transmission side buffers 120 to 12n, and the data signal lines 130 to 13n, respectively, and then the reception side latches 150 to 15n. For example, the clock CLK is supplied to the clock terminals (capture timing control terminals) of the respective transmission side latches 110 to 11n, and is transmitted to the reception side buffer 103 via the transmission side buffer 101 and the clock signal line 102, thereby receiving each reception. Supplied to the clock terminals of the side latches 150 to 15n.
[0006]
Thus, the conventional signal transmission system using a plurality of signal lines supplies the same clock CLK to the transmission side latches 110 to 11n and the reception side latches 150 to 15n, respectively, and controls the capture timing. .
[0007]
[Problems to be solved by the invention]
FIG. 2 is a timing chart for explaining an example of the operation in the signal transmission system of FIG.
[0008]
As shown in FIG. 2, for example, even if the data D0 to Dn are output at the same timing on the transmission side, the delay amount of the data transmitted via the signal lines 130 to 13n is not limited on the reception side. Slightly different. That is, in the conventional signal transmission system shown in FIG. 1 described above, the clock CLK and the plurality of data D0 to Dn are respectively supplied to the clock signal line and the plurality of signal lines 130 to 13n, and the buffers 101, 120 to 12n; Since 140 to 14n and the like are used, the amount of delay in the signal transmitted through each signal line is different, and the signal (data) transmitted through the signal line for each signal line (data signal line 130 to 13n) is different. ) Optimal capture timing will be different. Specifically, as shown in FIG. 2, for example, the data D0 and D1 can be taken in by the receiving side latches 150 and 151, but the delay amount differs for each signal line (skew: Skew). ), For example, if the data fetch timing for fetching data Dn comes in the data transition period (boundary), it becomes difficult to fetch the data Dn accurately by the receiving latch 15n.
[0009]
For example, this skew becomes a serious problem as the frequency of the clock CLK increases and high-speed operation (high-speed transmission) progresses, and the transmission-side latches 110 to 11n and the reception-side latches provided in the signal lines 130 to 13n. If a common strobe signal (clock CLK) is supplied to each of 150 to 15n and a signal (data) is taken in, the skew for each signal line cannot be dealt with.
[0010]
That is, if the difference in the optimum signal capture timing becomes extremely large in the reception side latches 150 to 15n of each signal line, all signals cannot be captured (received) correctly at the common timing (clock CLK). As a result, the transmission distance and transmission speed at which signals can be accurately transmitted are limited. Alternatively, in order to increase the transmission distance of the signal and increase the transmission speed (increase the bit rate), it is necessary to use an expensive cable with a specially adjusted skew, which not only increases the cost, The improvement of the transmission distance and transmission speed cannot be expected to be significant, and cannot be said to be a fundamental solution.
[0011]
FIG. 3 is a block diagram schematically showing another example of a conventional signal transmission system.
[0012]
The signal transmission system illustrated in FIG. 3 includes, for example, a first circuit (block A) 410 that uses the clock CLOCK-A, a second circuit (block B) 450 that uses the clock CLOCK-B, and these first circuits. An n-bit width signal transmission path (bus) 430 for transmitting a signal (data) between the circuit 410 and the second circuit 450 is provided. Here, for example, the first circuit 410 is a core circuit in an ASIC (Application Specific IC), and the second circuit 450 is a high-speed I / O circuit. The clock CLOCK-A and the clock CLOCK-B are clocks having different phases but the same frequency.
[0013]
That is, FIG. 3 shows another example of a signal transmission system including a clock transposing circuit between synchronous circuits (circuits 410 and 450). From the first circuit 410, n-bit data by the clock CLOCK-A is obtained. The n-bit data transmitted and received via the signal transmission path 430 is received by the second circuit 450 using the clock CLOCK-B.
[0014]
In the conventional signal transmission system shown in FIG. 3, even if the frequencies of the clocks CLOCK-A and CLOCK-B are equal, a non-zero phase difference is included between them. This phase difference is not a problem when it is sufficiently small with respect to the period of the synchronizing circuit, and this phase difference basically does not depend on the period or frequency.
[0015]
For this reason, in the conventional signal transmission system shown in FIG. 3, the ratio of the phase difference to the period increases as the period becomes shorter (as the frequency becomes higher), and it may become impossible to ignore the data and receive data correctly. .
[0016]
In view of the problems of the above-described conventional signal transmission system, the present invention generates a clock capable of reliably receiving data in consideration of a phase difference, and enables signal transmission at high speed without error. The purpose is to provide.
[0017]
[Means for Solving the Problems]
According to the first aspect of the present invention, there is provided a timing signal generation circuit for generating a reception timing signal which is a reference for taking in a reception signal transmitted based on an external clock, wherein a timing signal having a plurality of phases is obtained. A timing signal generation circuit to generate, and a plurality of determination timing signals used for determining whether the first timing signal and the first timing signal are used as the reception timing signal from the plurality of phase timing signals. A determination circuit that determines whether to use the first timing signal as the reception timing signal based on a first logic determined by the plurality of determination timing signals based on the external clock. And the determination circuit is determined by the plurality of determination timing signals with reference to the external clock. A logic different from the first logic A timing having a reception timing signal cancellation necessity determination circuit that determines whether the reception timing signal is fixed as the reception timing signal or canceled based on a second logic; A signal generation circuit is provided.
[0018]
According to the second aspect of the present invention, there is provided a timing signal generation method for generating a reception timing signal which is a reference for taking in a reception signal transmitted based on an external clock, wherein a timing signal having a plurality of phases is obtained. A first step to be generated, and a plurality of determination timing signals used for determining whether the first timing signal and the first timing signal are used as the reception timing signal from the plurality of phase timing signals. Whether to use the first timing signal as the reception timing signal is determined based on a second step to be selected and a first logic determined by the plurality of determination timing signals with reference to the external clock. 3. Determined by the plurality of determination timing signals based on the third step and the external clock A logic different from the first logic And a fourth step of determining whether to fix or release the reception timing signal as the reception timing signal based on a second logic. Provided.
[0019]
According to the third aspect of the present invention, the signal transmission includes: a transmission circuit that transmits data; a signal transmission path; and a reception circuit that receives data supplied from the transmission circuit via the signal transmission path. The reception circuit is a timing signal generation circuit that generates a reception timing signal that is a reference for capturing a reception signal transmitted based on an external clock, and generates a timing signal having a plurality of phases. And a plurality of timing signals for determination used to determine whether the first timing signal and the first timing signal are used as the reception timing signal from the timing signals of the plurality of phases. Then, based on the first logic determined by the plurality of determination timing signals with the external clock as a reference, the first type Comprising a determining circuit or said reception timing signal to ring signal, wherein the decision circuit, based on the said external clock is determined by the plurality of determination timing signal A logic different from the first logic A timing signal generation circuit having a reception timing signal release necessity determination circuit for determining whether the reception timing signal is fixed as the reception timing signal or released based on a second logic; A signal transmission system is provided.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a timing signal generation circuit, a signal transmission system, and a timing signal generation method according to the present invention will be described in detail with reference to the accompanying drawings.
[0021]
FIG. 4 illustrates an example of a timing signal generation method according to the present invention. Timing diagram FIG. 5 illustrates the timing signal generation method shown in FIG. Figure of It is. 4 and 5, reference symbol CLOCK-A indicates a clock used in a first circuit (for example, a core circuit in an ASIC), and CLOCK-B0 to CLOCK-B7 indicate a second circuit (for example, A high-speed I / O circuit in the ASIC indicates a clock used in data fetching and determination of a clock to be selected (fixed). Here, the clocks CLOCK-B0 to CLOCK-B7 are eight-phase clocks whose phases are different from each other by 45 °.
[0022]
As shown in FIG. 5, in the example of the timing signal generation method according to the present invention, first, in step ST11, a clock CLOCK-B5 (arbitrary candidate clock) is selected from a plurality of candidates, and the process proceeds to step ST12. Then, the clocks CLOCK-B0 and CLOCK-B1 are beaten by the clock CLOCK-A, that is, the levels of the clocks CLOCK-B0 and CLOCK-B1 are captured at the rising timing of the clock CLOCK-A. Further, the process proceeds to step ST13, and it is determined whether or not both of the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are the low level “L”.
[0023]
If it is determined in step ST13 that both the levels of the clocks CLOCK-B0 and CLOCK-B1 taken in at the rising timing of the clock CLOCK-A are the low level “L”, the process proceeds to step ST14, Similarly, the levels of the clocks CLOCK-B0 and CLOCK-B1 are captured again at the rising timing of the clock CLOCK-A, and the process proceeds to step ST15. In step ST15, as in step ST13, it is determined again whether the levels of the clocks CLOCK-B0 and CLOCK-B1 taken in at the rising timing of the clock CLOCK-A are both low.
[0024]
Also in step ST15, if it is determined that both of the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are the low level “L”, the candidate clock CLOCK-B5 is optimized. Fixed as a stable clock. That is, in the second circuit, the clock CLOCK-B5 is generated and used as a data capturing clock.
[0025]
On the other hand, if it is determined in step ST13 or ST15 that both the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are not the low level “L”, the candidate clock CLOCK-B5 is selected. Discard and select another clock (for example, clock CLOCK-B6) as a candidate clock (step ST 17 ) And repeat the same process.
[0026]
4 and FIG. 5, for example, two determination clocks (determination timing signals) CLOCK-B0 and CLOCK-B1 with respect to the candidate clock (reception timing signal) CLOCK-B5, for example. The determination clocks CLOCK-B0 and CLOCK-B1 are determined twice in steps ST13 and ST15, and it is determined whether or not they are fixed at the clock CLOCK-B5. Similarly, the candidate clock CLOCK- Whether two determination clocks CLOCK-B1 and CLOCK-B2 are defined for B6, whether these determination clocks CLOCK-B1 and CLOCK-B2 are determined twice in steps ST13 and ST15, and are fixed by the clock CLOCK-B6 To decide You have me.
[0027]
The combination of the candidate clock and the determination clock can be changed according to the frequency of the clock to be used. That is, when the clock frequency is relatively low (for example, about a few hundred tens of MHz or less), the data acquisition timing (rise timing) of the candidate clock with respect to the determination clock is approximately the center of the data (DATA) shown in FIG. Fc), and when the clock frequency is high (for example, several hundred MHz: about 625 MHz or more), as shown in FIG. 4, timing later than the center of the data (DATA) (for example, F−) b5) is preferred. This is because, when the frequency of the clock for transmitting data is increased, the setup time margin must be considered rather than the data hold time.
[0028]
Further, the number of determination clocks (determination timing signals: CLOCK-B0, CLOCK-B1) with respect to one candidate clock (reception timing signal: CLOCK-B5) is not limited to two. The number of determination processes (steps ST13 and ST15) using the clock for use is not limited to two.
[0029]
FIG. 6 is a diagram for explaining another example of the timing signal generating method according to the present invention. Timing diagram FIG. 7 illustrates the timing signal generation method shown in FIG. Figure of It is. Here, the timing signal generation method shown in FIG. 6 and FIG. 7 follows the timing signal generation method (clock selection and fixation) described with reference to FIG. 4 and FIG. And selection of a new clock.
[0030]
As shown in FIG. 6, in this timing signal generation method, the range in which the candidate clock (CLOCK-B5) is fixed in the determination process using the determination clocks (CLOCK-B0, CLOCK-B1) is determined by the determination clock. The fixed clock is narrower than the range in which the clock is not released (the range to be maintained).
[0031]
As shown in FIG. 7, in another example of the timing signal generating method according to the present invention, first, in step ST21, the state is fixed from the plurality of candidates with the clock CLOCK-B5, and then proceeds to step ST22. The clocks CLOCK-B0 and CLOCK-B1 are beaten with the clock CLOCK-A, that is, the levels of the clocks CLOCK-B0 and CLOCK-B1 are captured at the rising timing of the clock CLOCK-A. In step ST23, it is determined whether the levels of the clocks CLOCK-B0 and CLOCK-B1 taken in at the rising timing of the clock CLOCK-A are the high level “H” and the low level “L”, respectively.
[0032]
If it is determined in step ST23 that the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are the high level “H” and the low level “L” in sequence, the process proceeds to step ST24. Similarly to step ST22, the levels of the clocks CLOCK-B0 and CLOCK-B1 are captured again at the rising timing of the clock CLOCK-A, and the process proceeds to step ST25. Here, as shown in FIG. 4, the phase (rise timing) of the clock CLOCK-B0 is 45 ° ahead of the phase (rise timing) of the clock CLOCK-B1.
[0033]
In step ST25, it is determined whether or not the levels of the clocks CLOCK-B0 and CLOCK-B1 taken at the rising timing of the clock CLOCK-A are both high. If it is determined in step ST25 that both the levels of the clocks CLOCK-B0 and CLOCK-B1 taken in at the rising timing of the clock CLOCK-A are the high level “H”, that is, the fixed clock CLOCK-B5. When the phase of the clock CLOCK-B7 deviates in a direction in which the phase of the clock CLOCK-B5 greatly deviates (departs from the range P2 shown in FIG. 6), the clock CLOCK-B7 whose phase is delayed from the clock CLOCK-B5 is selected as the next candidate. If it is determined in step ST25 that both the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are not the high level “H”, the process returns to step ST22.
[0034]
On the other hand, if it is determined in step ST23 that the levels of the clocks CLOCK-B0 and CLOCK-B1 taken in at the rising timing of the clock CLOCK-A are not sequentially the high level “H” and the low level “L”, the process goes to step ST27. Then, similarly to step ST22, the levels of the clocks CLOCK-B0 and CLOCK-B1 are captured again at the rising timing of the clock CLOCK-A, and the process proceeds to step ST28. If it is determined in step ST28 that both the levels of the clocks CLOCK-B0 and CLOCK-B1 taken in at the rising timing of the clock CLOCK-A are the high level “H”, that is, the fixed clock CLOCK-B5. When the phase of the clock CLOCK-B3 deviates in the direction of a large delay (when it deviates from the range P2 shown in FIG. 6), the clock CLOCK-B3 whose phase is advanced from the clock CLOCK-B5 is selected as the next candidate. If it is determined in step ST28 that both the levels of the clocks CLOCK-B0 and CLOCK-B1 captured at the rising timing of the clock CLOCK-A are not the high level “H”, the process returns to step ST22.
[0035]
As described above, the range for releasing the fixed clock in the determination process using the determination clock (comparison condition for releasing) is set to be gentler than the comparison condition for holding (maintaining) the fixed clock. Thus, the clock selection (fixed or canceled) operation is stabilized by preventing the clock itself from being canceled due to jitter.
[0036]
In the above, the clock used for capturing and selecting (fixing) data in the second circuit is not limited to the eight-phase clock, and the determination clock and candidate clock used for the determination are Needless to say, the combination and the like can be changed in various ways.
[0037]
FIG. 8 is a block diagram schematically showing a first embodiment of a timing signal generation circuit (signal transmission system) according to the present invention, and shows a plurality of transmission circuits. In FIG. 8, reference numerals 160 to 16n are D-type flip-flops, 170 to 17n are transmission circuits, 181 is a clock transfer circuit, 182 is a PLL (Phase Locked Loop) circuit, 183 is a clock generation circuit, and 184 is a decoder. A multiplexer (DEMUX) is shown.
[0038]
Here, each of the flip-flops 160 to 16n corresponds to the clock transfer flip-flop 100, and each of the transmission circuits 170 to 17n corresponds to, for example, the transmission data processing unit 10 in FIG. For example, as described with reference to FIG. 1, each of the transmission circuits 170 to 17n converts 16-bit parallel data with a data rate of 156 bps to serial data with a data rate of 2.5 Gbps. It has a demultiplexer function.
[0039]
As shown in FIG. 8, in the timing signal generation circuit of the first embodiment, 16-bit parallel data DATA0 [15: 0] supplied to the transmission data processing units 170 to 17n (flip-flops 160 to 16n). -DATAn [15: 0] are all input in synchronization with one data input clock PCLK (common clock). By the way, since the data input clock PCLK synchronized with the parallel data is usually transmitted through the logic circuit, the phase variation (jitter) is large due to the characteristics of the logic circuit for clock propagation and the influence of noise. Become. Therefore, in the timing signal generation circuit of the first embodiment, the signal transmission clock CLK (for example, the frequency is 2.5 GHz) transmitted at a high speed is a reference clock REFCLK in which jitter is suppressed separately from the data input clock PCLK. Generate from.
[0040]
That is, the signal transmission clock CLK used for signal transmission is generated by the PLL circuit 182 by multiplying the frequency of the reference clock REFCLK. At this time, although the frequencies of the data input clock PCLK and the reference clock REFCLK are dependent, the phases of the data input clock PCLK and the reference clock REFCLK are out of phase. Therefore, the clock changing circuit 181 transfers the data input clock PCLK to the signal line transmission circuit driving clocks pll-clk0 to pll-clk3 (signal transmission clock CLK) generated by the PLL circuit 182. In the fourth embodiment, the PLL circuit 182 outputs, for example, four-phase clocks (pll-clk0 to pll-clk3) having a phase of 90 ° and a frequency of 625 MHz, and the four-phase clocks pll-clk0 to pll-clk0. For example, a signal transmission clock CLK having a frequency of 1.25 GHz is generated from the pll-clk3 by the demultiplexer 184.
[0041]
FIG. 9 is a diagram for explaining the operation of the timing signal generation circuit of FIG.
[0042]
As shown in FIG. 9, the clock changing circuit 181 uses the four-phase clocks pll-clk0 to pll-clk3 having a phase difference of 90 ° and having a phase difference of 90 ° output from the PLL circuit 182, and the frequency is A clock clka of 156 MHz, a clock clka-90 whose phase is advanced by 90 ° with respect to the clock clka, and a clock clka-135 whose phase is advanced by 135 ° with respect to the clock clka are generated. When the clock clka-90 and the clock clka-135 are both at the low level “L”, the rising edge of the data input clock PCLK is DATAn [15: inputted in synchronization with the data input clock PCLK. 0] (each 16-bit parallel input data DATA0 [15: 0] to DATAn [15: 0]) is taken in at the rising edge of the clock clka by the clock transfer flip-flop 16n (160 to 16n). That is, the clock clka is selected as an optimal clock (a clock with a sufficient margin for both setup / hold) and distributed to each channel (each clock transfer flip-flop 160 to 16n) as a common clock for the transmission circuit.
[0043]
Here, when the data input clock PCLK is not in a position satisfying the above-described conditions, the clock clkb-90 whose phase is advanced by 90 ° from the clock clkb with respect to clkb whose phase is delayed by 90 ° from the clock clka. And the clock clkb-135 whose phase is advanced by 135 ° from the clock clkb is generated, and the rising edges of the data input clock PCLK are both at the low level “L” position of the clock clkb-90 and the clock clkb-135. DATAn [15: 0] input in synchronization with the data input clock PCLK is captured at the rising edge of the clock clkb by the clock transfer flip-flop 16n.
[0044]
Further, when the data input clock PCLK is not in an optimum position with respect to the clock clkb, similarly, comparison processing is performed on the clocks clkc and clkd, and finally any one of the clocks clka to clkd is performed. The clock will be selected. That is, the four-phase clocks (clka, clkb, clkc, clkd) having the same frequency as the data input clock PCLK generated from the data input clock PCLK and the output of the PLL circuit 182 (clocks pll-clk0 to pll-clk3). ) And a clock (clka) having an optimum phase relationship for latching parallel data (DATAn [15: 0]) synchronized with the data input clock PCLK is selected, and this is a plurality of clock transposing flip-flops. The data is transmitted in synchronization with one clock via the plurality of signal lines 130 to 13n.
[0045]
Here, as shown in FIG. 9, each selected clock is a clock that rises at the timing of the approximate center (Fc) of the data, but for example, when the clock frequency is even higher ( For example, in the case of 800 MHz or the like, as described with reference to FIG. 4, since the setup time margin must be considered rather than the data hold time, the timing of the center of the data (Fc) A clock that rises at a later timing is selected.
[0046]
FIG. 10 is a circuit diagram showing an example of a PCLK position detection circuit that can be applied to the clock switching circuit in the timing signal generation circuit of FIG. The operation of the clock transfer circuit 181 described with reference to FIG. 9 can be realized by applying a PCLK position detection circuit 190 as shown in FIG.
[0047]
As shown in FIG. 10, the PCLK position detection circuit 190 includes two D-type flip-flops 191 and 192 and an OR gate 193. The data terminal D of the flip-flop 191 is supplied with the clock clka-90 whose phase is advanced by 90 ° from the clock clka, and the data terminal D of the flip-flop 192 is advanced by 135 ° with respect to the clock clka. The clock clka-135 is supplied, and the data input clock PCLK is input to the data fetch terminals of the flip-flops 191 and 192. Accordingly, the flip-flops 191 and 192 take in the clocks clka-90 and clka-135 at the rising edge of the data input clock PCLK. Further, the outputs of the flip-flops 191 and 192 are supplied to an OR gate 193. When the output of the OR gate 193 is at a low level "L", that is, the rising edge of the data input clock PCLK is changed to the clocks clka-90 and clka- When both 135 are at the position of the low level “L”, the selection signal SELa of the low level “L” is output to select the clock clka. Here, it goes without saying that the PCLK position detection circuit or the clock transfer circuit can be variously modified.
[0048]
FIG. 11 is a block diagram schematically showing a second embodiment of the timing signal generating circuit (signal transmission system) according to the present invention. In FIG. 11, reference numeral 510 denotes a first circuit (block A: transmission circuit), 550 denotes a second circuit (block B), and 530 denotes data between the first circuit 510 and the second circuit 550. An n-bit width data transmission path for performing transmission, 531 is a clock transmission path for transmitting a clock (CLOCK-A) from the first circuit 510 to the second circuit 550, and 532 is a first circuit from the second circuit 550. An error signal transmission path for transmitting the error signal ERR to 510, 551 indicates a receiving circuit, and 552 indicates a determination circuit.
[0049]
As shown in FIG. 11, in the timing signal generation circuit of the second embodiment, the determination circuit 552 includes m clocks CLOCK-B (for example, four-phase clocks) having different phases, a synchronous reset signal RESYNC, and The lock signal LOCK is supplied, and the clock CLOCK-A used in the first circuit 510 is supplied via the clock transmission line 531. The determination circuit 552 outputs an error signal ERR to the reception circuit 551 and also outputs an error signal ERR to the transmission circuit 510.
[0050]
That is, the determination circuit 552 should output an optimal clock from the supplied m clocks CLOCK-B having different phases to the reception circuit 551 as the reception clock (CLK) and release the fixed clock. Is determined, the error signal ERR indicating the cancellation of the clock is output to the transmission circuit 510 that is the data transmission source and the reception circuit 551 that receives (reproduces) the data. The operation of the determination circuit 552 is the same as that described with reference to FIGS. 4 to 7 or FIGS.
[0051]
Furthermore, the synchronization reset signal RESYNC and the lock signal LOCK are directly input to the determination circuit 552 from the outside, and the operation of the determination circuit 552 is forcibly re-executed by the synchronization reset signal RESYNC, and the determination circuit 552 It is configured so that the operation can be invalidated (forcedly fixed).
[0052]
FIG. 12 is a block diagram schematically showing a third embodiment of the timing signal generating circuit (signal transmission system) according to the present invention.
[0053]
As apparent from the comparison between FIG. 12 and FIG. 11, the timing signal generation circuit of the third embodiment includes the four-phase clocks ACLK [0], ACLK [1], ACLK [2], ACLK [ 3] is provided, and the outputs (four-phase clocks ACLK [0] to ACLK [3]) of the four-phase clock generation circuit 553 are supplied to the determination circuit 552. Yes. Note that the clock PCLK and the data PDATA in FIG. 12 correspond to the clock CLOCK-A and the data DATA in FIG.
[0054]
The first circuit (transmission circuit) 510 outputs data PDATA synchronized with the clock PCLK and supplies the data PDATA to the reception circuit 551 through the data transmission path 530. In the second circuit 550, the four-phase clock generation circuit 553 generates four-phase clocks ACLK [0] to ACLK [3] that are used to receive data based on the clock ACLK having a frequency twice that of the clock PCLK. Then, the determination circuit 552 determines the level of the determination clock based on the clock PCLK supplied from the transmission circuit 510, and supplies the corresponding candidate clock to the reception circuit 551 as a reception clock (CLK). The operation of the determination circuit 552 is the same as that described with reference to FIGS. 4 to 7 or FIGS.
[0055]
Further, also in this embodiment, the determination circuit 552 outputs the error signal ERRX to the transmission circuit 510 and the reception circuit 551 (the data reception unit in the second circuit 550) when the clock cannot be specified. Further, a lock signal LOCK for forcibly fixing the clock and a synchronous reset signal RESYNC for forcibly re-executing the selection operation are input from the outside. Here, the error signal ERRX is a low enable signal which is an inverted logic signal of the error signal ERR.
[0056]
13 is a circuit diagram illustrating an example of a four-phase clock generation circuit in the timing signal generation circuit of FIG. 12, and FIG. 14 is a circuit diagram illustrating an example of a determination circuit in the timing signal generation circuit of FIG. 15 is a diagram for explaining the operation of the timing signal generating circuit of FIG.
[0057]
As shown in FIG. 13, the four-phase clock generation circuit 553 includes two flip-flops 5531 and 5532. As shown in FIG. 15, the four-phase clock ACLK from the clock ACLK having a frequency twice that of the clock PCLK. [0] to ACLK [3] are generated. The flip-flops 5531 and 5532 are supplied with a preset signal PRESET. The four-phase clocks ACLK [0] to ACLK [3] generated by the four-phase clock generation circuit 553 are supplied to the determination circuit 552, and a predetermined candidate clock corresponding to the determination result of the determination clock is selected and clocked. It is supplied to the receiving circuit 551 as CLK.
[0058]
The determination circuit 552 includes a plurality of flip-flops 5211 to 5216, a plurality of NAND gates 5221 to 5226, an AND gate 523, a plurality of NOR gates 5241 to 5244, an inverter 52, and a clock selection circuit 526. Note that the four-phase clock generation circuit 553 and the determination circuit 552 shown in FIGS. 13 and 14 are merely one configuration example, and needless to say, various configurations can be employed.
[0059]
In the example of FIG. 14, two determination clocks (for example, clocks ACLK [0], ACLK [1]) are set for one candidate clock, and these determination clocks are fetched with the clock PCLK to perform determination. A candidate clock (for example, ACLK [3]) among the four-phase clocks ACLK [0] to ACLK [3] corresponding to the determination clock is selected by the selection signal SEL and output as the clock CLK used in the receiving circuit 551. To do.
[0060]
As shown in FIG. 14, the determination clocks ACLK [0] and ACLK [1] by the flip-flops 5211 and 5213 and the determination of the outputs of the flip-flops 5211 and 5213 by the flip-flops 5212 and 5214 are as follows: The selection signal SEL is output by determining the two determination clocks ACLK [0] and ACLK [1] twice in succession at the rising timing of the clock PCLK, and the clock CLK supplied to the receiving circuit 551 is fixed and released. Control. 14 outputs an error signal ERRX as an output of the NAND gate 5224, and can reset and lock (forcibly fix) the circuit from the outside by the synchronous reset signal RESYNC and the lock signal LOCK. It is configured.
[0061]
Here, as shown in FIG. 12, the error signal ERRX is supplied to the transmission circuit 510 and the reception circuit 551, and each of the predetermined processing, for example, the transmission circuit 510 stops or retransmits data, The receiving circuit 551 stops data reception or discards or recaptures received data. In the third embodiment, as shown in FIG. 15, the determination to fix the clock by the determination by the two determination clocks is performed within a range of 90 °, for example, while the fixed clock is used. The determination to cancel is performed within a range of 270 °, for example.
[0062]
FIG. 16 is a block diagram schematically showing a fourth embodiment of the timing signal generating circuit according to the present invention, and FIG. 17 is a circuit diagram showing an example of an eight-phase clock generating circuit in the timing signal generating circuit of FIG. FIG. 18 is a diagram for explaining the operation of the timing signal generation circuit of FIG.
[0063]
As is clear from the comparison between FIG. 16 and FIG. 12, in the timing signal generation circuit of the fourth embodiment, the phases are mutually different instead of the four-phase clock generation circuit 553 in the timing signal generation circuit of the third embodiment described above. An eight-phase clock generation circuit 554 that generates eight-phase clocks BCLKK [0] to BCLK [7] that differ by 45 ° is provided.
[0064]
As shown in FIG. 17, the eight-phase clock generation circuit 554 includes five flip-flops 5541 to 5545, and as shown in FIG. 18, the eight-phase clock BCLK from the clock BCLK having a frequency four times the clock PCLK. [0] to BCLK [7] are generated. Also, a preset signal PRESET is supplied to each of the flip-flops 5541 to 5545. The eight-phase clocks BCLK [0] to BCLK [7] generated by the eight-phase clock generation circuit 554 are supplied to the determination circuit 552, and a predetermined candidate clock corresponding to the determination result of the determination clock is selected and clocked. It is supplied to the receiving circuit 551 as CLK.
[0065]
The determination circuit 552 is similar to that shown in FIG. 14 described above, but the clock supplied to the clock selection circuit 526 is not the four-phase clocks ACLK [0] to ACLK [3] but the eight-phase clocks BCLK [0] to BCLK [7] and the determination clock is not the two clocks ACLK [0] and ACLK [1] of the four-phase clocks ACLK [0] to ACLK [3], but the eight-phase clocks BCLK [0] to Two clocks BCLK [0] and BCLK [1] of BCLK [7] are used.
[0066]
That is, as shown in FIG. 14, the determination circuit 552 determines the determination clocks BCLK [0] and BCLK [1] by the flip-flops 5211 and 5213, and the flip-flops 5211 and 5214 Depending on the output determination, that is, the determination signal BCLK [0], BCLK [1] is determined twice in succession at the rising timing of the clock PCLK, so that the selection signal SEL is output and supplied to the receiving circuit 551. The clock CLK to be fixed and released are controlled (the control described with reference to FIGS. 5 and 7). As described above, the determination circuit 552 of FIG. 14 outputs the error signal ERRX as the output of the NAND gate 5224, and resets and locks (forcibly fixed) from the outside by the synchronous reset signal RESYNC and the lock signal LOCK. ) Is possible.
[0067]
In the fourth embodiment, as shown in FIG. 18, the determination of fixing the clock by the two determination clocks is performed within a range of 135 °, for example, while the fixed clock is released. The determination is made in a range of 225 °, for example.
[0068]
FIG. 19 is a block diagram schematically showing a fifth embodiment of the timing signal generating circuit according to the present invention. In FIG. 19, reference numeral 520 is a first circuit, 560 is a second circuit, 530 is an n-bit width for transmitting data (including a clock) between the first circuit 520 and the second circuit 560. The data transmission path 532 and an error signal transmission path 532 for transmitting the error signal ERRX from the second circuit 560 to the first circuit 520 are shown. Further, reference numeral 561 indicates a receiving circuit, 562 indicates a determination circuit, 564 indicates an eight-phase clock generation circuit, and 565 indicates a clock recovery circuit.
[0069]
As shown in FIG. 19, in the timing signal generation circuit of the fifth embodiment, the clock transmission path (531) for transmitting the clock from the first circuit to the second circuit is not provided, and the data PDATA is stored in the data PDATA. Including transmission. In other words, the second circuit 560 is provided with a clock recovery circuit 565, and from the data PDATA transmitted through the data transmission path 530 to the clock DCLK (in FIG. 12, from the first circuit 510 to the clock transmission path 531). The second circuit 550 (corresponding to the clock PCLK transmitted to the determination circuit 552) is reproduced via the signal and supplied to the determination circuit 562. Note that data transmission including clock information from the first circuit 520 to the second circuit 560 includes, for example, run length 5 8B / 10B (or 10B / 8B), run length 72 SONET, and the like. Usually, the values within the above-described ranges are used as the actual data PDATA standard.
[0070]
20 and 21 are circuit diagrams showing an example of the clock recovery circuit in the timing signal generation circuit of FIG. 19, and FIG. 22 is a diagram for explaining the operation of the clock recovery circuit in the timing signal generation circuit of FIG. .
[0071]
20 and 21, the clock recovery circuit 565 includes a plurality of flip-flops 650 to 657 (FIG. 20 (a)) and a plurality of exclusive NOR (EXNOR) gates 660 to 667 (FIG. 20 (b)). ), A NOR gate 670, a plurality of NAND gates 671 to 674, inverters 675 and 676 (FIG. 21A), and selection circuits 681 and 682 (FIG. 21B).
[0072]
As shown in FIG. 20A, each of the flip-flops 650 to 657 is supplied with data PDATA and one of the eight-phase clocks BCLK [0] to BCLK [7], and the data PDATA is supplied to each of the eight-phase clocks BCLK. [0] to BCLK [7]. In practice, outputs (BD [0] to BD [7]) are obtained after being input to the flip-flop a plurality of times. Therefore, there is a boundary where data taken in any of the eight flip-flops 650 to 657 changes between the high level “H” and the low level “L”.
[0073]
As shown in FIG. 20B, the EXNOR gates 660 to 667 are for detecting the boundary, and the outputs (BD [0] and BD [1] of the two adjacent flip-flops 650 to 657 are used. BD [1], BD [2];... BD [7], BD [0]) and their outputs change between a high level “H” and a low level “L” ( Any one of the outputs EX01X to EX70X of the EXNOR gates 660 to 667 becomes a low level “L”).
[0074]
Thus, after generating EX [n, n + 1] X for all clocks (clocks BCLK [0] to BCLK [7]), latches (NAND gates 671, 672) as shown in FIG. And a latch composed of inverters 675 and 676, hold each state as a flag, and generate a reset signal RST 23 X by a logic circuit including a NOR gate 670 and NAND gates 673 and 674. FIG. 21A shows a case where there is a boundary between BCLK [2] and BCLK [3] among the eight-phase clocks, and actually there are eight similar blocks. Thus, flags EX01-F to EX70F are held, and reset signals RST01X to RST70X are generated. Note that one of the flags EX01-F to EX70F is set to a high level “H” and the others are all set to a low level “L”.
[0075]
Further, as shown in FIG. 21B, the flags EX01-F to EX70F held in the respective latches are supplied to the selection control terminals sel of the selection circuits 681 and 682 as selection signals. The selection circuit 681 selects one of the eight-phase clocks BCLK [0] to BCLK [7] input by the selection signal input and outputs it as the clock DCLK. In addition, the selection circuit 682 selects one of the reset signals RST01X to RST70X inputted by the selection signal input and outputs it as the reset signal RESETX.
[0076]
Specifically, as shown in FIG. 22, for example, when only the flag EX23 is at the high level “H”, the clock BCLK [0] is selected as the output signal (DCLK) and the reset signal ( Reset signal RST23X is selected as RESETX). The clock DCLK and the reset signal RESETX are supplied to the determination circuit 562.
[0077]
FIG. 23 is a circuit diagram showing an example of a determination circuit in the timing signal generation circuit of FIG.
[0078]
As is clear from the comparison between FIG. 23 and FIG. 14, the determination circuit 562 in the fifth embodiment adds a NOR gate 621 and an inverter 622 to the determination circuit 552 of FIG. The reset signal RESETX is supplied as an input, and the clock DCLK obtained by the clock recovery circuit 565 is used as the clock PCLK in the determination circuit 552 of FIG.
[0079]
FIG. 24 is a diagram for explaining the operation of the determination circuit in the timing signal generation circuit of FIG.
[0080]
Specifically, as shown in FIG. 24, two determination clocks BCLK [0] and BCLK [1] are determined twice in succession at the rising timing of the clock DCLK, and when all are at the low level “L”. For example, the clock BCLK [5] is selected (fixed) and is defined as a clock (reception clock) CLK supplied to the reception circuit 561. Note that, depending on the frequency of the clock used, the reception clock CLK supplied to the reception circuit 561 may be defined as the clock BCLK [4] or the clock BCLK [3] instead of the clock BCLK [5] as described above. It is. Further, when the four-phase clocks ACLK [0] to ACLK [3] are used instead of the eight-phase clocks BCLK [0] to BCLK [7], for example, the two determination clocks ACLK [0] at the rising timing of the clock DCLK. ], ACLK [1] are judged twice in succession, and when all are at the low level “L”, for example, the clock ACLK [3] is selected and set as the reception clock CLK.
[0081]
In each of the above embodiments, various configurations such as the determination circuit (552, 562), the clock generation circuit (553, 554), and the clock recovery circuit (565) can be used. The output is not limited to a four-phase clock and an eight-phase clock.
[0082]
As described above, according to each embodiment of the present invention, even when the phase difference between the clocks is not guaranteed in the transmission / reception circuits operating at the same frequency, or when the jitter included in the clock is not guaranteed, It becomes possible to transmit and receive data stably. Further, when a data error occurs, it is possible to improve the narrowing accuracy of the cause.
[0083]
(Supplementary Note 1) A candidate timing signal generation circuit that generates a plurality of candidate timing signals of different phases;
A timing signal generation circuit comprising: a reception timing signal control circuit that selects and holds a reception timing signal used for receiving data from the plurality of candidate timing signals according to a predetermined condition.
[0084]
(Supplementary Note 2) In the timing signal generation circuit according to Supplementary Note 1, the reception timing signal control circuit includes:
A determination timing signal comparison circuit that compares a predetermined determination timing signal with a comparison timing signal for each of the candidate timing signals;
And a reception timing signal selection / holding circuit for selecting and holding the reception timing signal in accordance with an output of the determination timing signal comparison circuit.
[0085]
(Supplementary Note 3) In the timing signal generation circuit according to Supplementary Note 2, a plurality of the determination timing signals are set for each of the candidate timing signals, and the determination timing signal comparison circuit includes the comparison timing signal and the comparison timing signal. A timing signal generation circuit that compares a plurality of timing signals for determination.
[0086]
(Supplementary Note 4) In the timing signal generation circuit according to Supplementary Note 3, the determination timing signal comparison circuit performs comparison between the comparison timing signal and the plurality of determination timing signals a plurality of times, and receives the reception timing. The signal selection holding circuit selects and holds the reception timing signal in accordance with a plurality of comparison outputs from the determination timing signal comparison circuit.
[0087]
(Supplementary Note 5) The timing signal generation circuit according to Supplementary Note 2, wherein the comparison timing signal is supplied in parallel with the received data.
[0088]
(Supplementary Note 6) The timing signal generation circuit according to Supplementary Note 2, wherein the comparison timing signal is supplied by being included in the received stream of data.
[0089]
(Supplementary note 7) In the timing signal generation circuit according to supplementary note 2, the reception timing signal control circuit further receives the selected and held reception timing signal in accordance with an output of the determination timing signal comparison circuit. A timing signal generation circuit comprising a reception timing signal cancellation circuit for cancellation.
[0090]
(Supplementary note 8) In the timing signal generating circuit according to supplementary note 7, the reception timing signal selection / holding circuit is configured such that when the reception timing signal is canceled by the reception timing signal cancellation circuit, the determination timing signal comparison circuit A timing signal generating circuit which selects and holds a new reception timing signal according to the output of the signal.
[0091]
(Supplementary Note 9) In the timing signal generation circuit according to Supplementary Note 7, when the reception timing signal control circuit further cancels the selected and held reception timing signal, the reception timing signal control circuit A timing signal generation circuit comprising a reception timing signal release notification circuit for notifying the release of the reception timing signal to the outside of the timing signal generation circuit.
[0092]
(Supplementary note 10) In the timing signal generating circuit according to supplementary note 7, the comparison condition in the determination timing signal comparison circuit for releasing the reception timing signal selected and held by the reception timing signal release circuit is A timing signal generation circuit characterized in that the reception timing signal selection / holding circuit is looser than a comparison condition in the determination timing signal comparison circuit for selecting and holding a reception timing signal.
[0093]
(Supplementary note 11) In the timing signal generation circuit according to any one of Supplementary notes 1 to 10, the reception timing signal control circuit further selects and holds a reception timing signal from the plurality of candidate timing signals. A timing signal generation circuit comprising a reception timing signal control stop circuit for stopping from the outside.
[0094]
(Supplementary note 12) In the timing signal generation circuit according to any one of supplementary notes 1 to 10, the reception timing signal control circuit further selects and holds a reception timing signal from the plurality of candidate timing signals. A timing signal generation circuit comprising a reception timing signal control re-execution circuit that is re-executed from outside.
[0095]
(Supplementary Note 13) A signal transmission system including a transmission circuit for transmitting data, a signal transmission path, and a reception circuit for receiving data supplied from the transmission circuit via the signal transmission path, wherein the reception circuit includes: A signal transmission system comprising the timing signal generation circuit according to any one of appendices 1 to 12.
[0096]
(Supplementary note 14) preparing a plurality of candidate timing signals of different phases,
A timing signal generation method comprising: selecting and holding a reception timing signal used for receiving data from the plurality of candidate timing signals according to a predetermined condition.
[0097]
(Supplementary note 15) In the timing signal generation method according to supplementary note 14, the selection and holding of the reception timing signal may include:
A timing signal for determination predetermined for each candidate timing signal is compared with a timing signal for comparison;
A timing signal generation method comprising: selecting and holding the reception timing signal according to a comparison result between the determination timing signal and the comparison timing signal for each candidate timing signal.
[0098]
(Supplementary Note 16) In the timing signal generation method according to supplementary note 15, a plurality of the determination timing signals are set for each of the candidate timing signals, and the comparison timing signal and the plurality of determination timing signals are compared. A timing signal generation method characterized by the above.
[0099]
(Supplementary Note 17) In the timing signal generation method according to Supplementary Note 16, the comparison between the comparison timing signal and the plurality of determination timing signals is performed a plurality of times, and the plurality of comparison timing signals and the determination timing signal are performed. And a timing signal generation method, wherein the reception timing signal is selected and held in accordance with the comparison result.
[0100]
(Supplementary note 18) The timing signal generation method according to supplementary note 15, wherein the comparison timing signal is supplied in parallel with the received data.
[0101]
(Supplementary note 19) The timing signal generating method according to supplementary note 15, wherein the comparison timing signal is supplied by being included in the received stream of data.
[0102]
(Supplementary note 20) In the timing signal generation method according to supplementary note 15, the selection and holding of the reception timing signal is performed according to a comparison result between the determination timing signal and the comparison timing signal for each of the candidate timing signals. A timing signal generating method comprising: canceling the selected and held reception timing signal.
[0103]
(Supplementary note 21) In the timing signal generation method according to supplementary note 20, when the reception timing signal is canceled, a determination timing signal predetermined for each candidate timing signal is compared with the comparison timing signal. And selecting and holding a new timing signal for reception.
[0104]
(Supplementary note 22) In the timing signal generation method according to supplementary note 20, when the selected and held reception timing signal is released, the release of the reception timing signal is notified to the outside. Timing signal generation method.
[0105]
(Supplementary note 23) In the timing signal generating method according to supplementary note 20, the comparison condition for releasing the selected and held reception timing signal is more than the comparison condition for selecting and holding the reception timing signal. A timing signal generation method characterized by being gradual.
[0106]
(Supplementary note 24) The timing signal generation method according to any one of supplementary notes 14 to 23, wherein selection and holding of reception timing signals from the plurality of candidate timing signals are stopped from the outside. How it occurs.
[0107]
(Supplementary Note 25) The timing signal generating method according to any one of Supplementary Notes 14 to 23, wherein the selection and holding of the reception timing signal from the plurality of candidate timing signals is re-executed from the outside. Signal generation method.
[0108]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to generate a clock capable of reliably receiving data in consideration of a phase difference, and to enable high-speed and error-free signal transmission.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing an example of a conventional signal transmission system.
FIG. 2 is a timing chart for explaining an example of the operation in the signal transmission system of FIG.
FIG. 3 is a block diagram schematically showing another example of a conventional signal transmission system.
FIG. 4 is a diagram for explaining an example of a timing signal generation method according to the present invention. Timing diagram It is.
FIG. 5 is a diagram for explaining the timing signal generation method shown in FIG. 4; Figure of It is.
FIG. 6 is a diagram for explaining another example of the timing signal generation method according to the present invention. Timing diagram It is.
7 is a diagram for explaining the timing signal generation method shown in FIG. 6; Figure of It is.
FIG. 8 is a block diagram schematically showing a first embodiment of a timing signal generating circuit according to the present invention.
9 is a diagram for explaining the operation of the timing signal generation circuit of FIG. 8;
10 is a circuit diagram showing an example of a PCLK position detection circuit that can be applied to a clock transposing circuit in the timing signal generation circuit of FIG. 8;
FIG. 11 is a block diagram schematically showing a second embodiment of the timing signal generating circuit according to the present invention.
FIG. 12 is a block diagram schematically showing a third embodiment of the timing signal generating circuit according to the present invention.
13 is a circuit diagram showing an example of a four-phase clock generation circuit in the timing signal generation circuit of FIG. 12. FIG.
14 is a circuit diagram showing an example of a determination circuit in the timing signal generation circuit of FIG. 12. FIG.
15 is a diagram for explaining the operation of the timing signal generation circuit of FIG. 12;
FIG. 16 is a block diagram schematically showing a fourth embodiment of the timing signal generating circuit according to the present invention.
17 is a circuit diagram showing an example of an eight-phase clock generation circuit in the timing signal generation circuit of FIG. 16. FIG.
18 is a diagram for explaining the operation of the timing signal generation circuit of FIG. 16;
FIG. 19 is a block diagram schematically showing a fifth embodiment of the timing signal generating circuit according to the present invention.
20 is a circuit diagram (part 1) illustrating an example of a clock recovery circuit in the timing signal generation circuit of FIG. 19;
FIG. 21 is a circuit diagram (part 2) illustrating an example of a clock recovery circuit in the timing signal generation circuit of FIG. 19;
22 is a diagram for explaining the operation of the clock recovery circuit in the timing signal generation circuit of FIG. 19;
23 is a circuit diagram showing an example of a determination circuit in the timing signal generation circuit of FIG.
24 is a diagram for explaining an operation of a determination circuit in the timing signal generation circuit of FIG. 19;
[Explanation of symbols]
110 to 11n: Transmission side data fetch circuit for data (transmission side latch)
120 to 12n: Data transmission side drive circuit (transmission side buffer)
130 to 13n: wiring for data (data signal line)
140 to 14n: Data receiving side driving circuit (receiving side buffer)
150 to 15n: Reception side data fetch circuit (reception side latch)
160 to 16n: flip-flop for clock replacement
170 to 17n: Transmission data processing unit (transmission side latch)
181: Clock transfer circuit
182 ... PLL circuit
183: Clock generation circuit
184 ... Demultiplexer
190 ... PCLK position detection circuit
510, 520 ... first circuit (block A: transmission circuit)
530 ... Data transmission path
531: Clock transmission path
532: Error signal transmission path
550, 560... Second circuit (block B)
551, 561 ... Receiving circuit
552, 562 ... judgment circuit
563 ... Four-phase clock generation circuit
564: Eight-phase clock generation circuit
565 ... Clock recovery circuit

Claims (6)

A timing signal generation circuit that generates a reception timing signal that serves as a reference for capturing a reception signal transmitted based on an external clock,
A timing signal generation circuit for generating a timing signal of a plurality of phases;
From the plurality of phase timing signals, a first timing signal and a plurality of determination timing signals used for determining whether the first timing signal is used as the reception timing signal are selected, and the external clock is used as a reference And a determination circuit that determines whether the first timing signal is the reception timing signal based on a first logic determined by the plurality of determination timing signals.
The determination circuit determines the reception timing signal based on a second logic that is different from the first logic and is determined by the plurality of determination timing signals with reference to the external clock. A timing signal generation circuit comprising: a reception timing signal cancellation necessity determination circuit for determining whether to fix or cancel a reception timing signal. The timing signal generation circuit according to claim 1,
The determination circuit receives the respective determination timing signals, and each of the plurality of flip-flops controlled by the external clock;
An AND circuit to which the outputs of the plurality of flip-flops are input;
A NOR circuit to which outputs of the plurality of flip-flops are input;
A latch to which the output of the AND circuit and the output of the NOR circuit are input,
The timing signal generation circuit, wherein the second logic is an output of the latch circuit. The timing signal generation circuit according to claim 1,
The determination circuit receives the respective determination timing signals, and each of the plurality of flip-flops controlled by the external clock;
A NAND circuit to which the outputs of the plurality of flip-flops are input;
An OR circuit to which the outputs of the plurality of flip-flops are input;
A latch to which the output of the NAND circuit and the output of the OR circuit are input,
The timing signal generation circuit, wherein the second logic is an output of the latch circuit. A timing signal generation method for generating a reception timing signal which is a reference for capturing a reception signal transmitted based on an external clock,
A first step of generating a plurality of phase timing signals;
A second step of selecting, from the plurality of phase timing signals, a first timing signal and a plurality of determination timing signals used for determining whether the first timing signal is the reception timing signal;
A third step of determining whether to use the first timing signal as the reception timing signal based on a first logic determined by the plurality of determination timing signals with reference to the external clock;
Based on the second logic different from the first logic, which is determined by the plurality of determination timing signals with the external clock as a reference, the reception timing signal is used as the reception timing signal. And a fourth step of determining whether to fix or release the timing signal. The timing signal generation method according to claim 4,
The second logic is a latch circuit that receives the respective determination timing signals, receives the outputs of a plurality of flip-flops controlled by the external clock, and inputs the outputs of the AND circuit and the NOR circuit. A timing signal generation method characterized by being an output. A signal transmission system comprising a transmission circuit for transmitting data, a signal transmission path, and a reception circuit for receiving data supplied from the transmission circuit via the signal transmission path,
The signal receiving system, wherein the receiving circuit includes the timing signal generating circuit according to claim 1.

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