JP3976643B2 - Vpp switch circuit, charge pump circuit and EEPROM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a Vpp switch circuit, a charge pump circuit, and an EEPROM using a MOS capacitor with improved frequency characteristics.
[0002]
[Prior art]
A conventional MOS capacitor is shown in FIGS. A polysilicon film 2 is formed on the surface of the P substrate 7 via a gate oxide film 8, and an oxide film 9 is formed on the polysilicon film 2. Aluminum electrode layers 3 and 5 are formed on oxide film 9. A part of the aluminum electrode layer 3 penetrates the oxide film 9 and is in contact with the polysilicon film 2 to form an aluminum contact 6. On the other hand, a part of the aluminum electrode layer 5 penetrates the oxide film 9 and contacts the N diffusion layer 10 formed on the surface of the P substrate 7 to form the field contact 4. The field contact 4 is arranged along one side 1 a of the rectangular field 1 partitioned on the surface of the P substrate 7 by the field oxide film 11.
[0003]
When a voltage V higher than the threshold Vth for channel formation is applied between the aluminum electrode layers 3 and 5, the N inversion layer 12 acting as a channel is gradually formed in the field 1 from the N diffusion layer 10 side. Electric charges are accumulated in the portion where the field 1 and the polysilicon film 2 overlap through the gate oxide film 8 and function as a capacitor. That is, as shown in the equivalent circuit of FIG. 14, many small capacitors are connected to each other through a resistor from one side 1 a of field 1 to the opposite side 1 b, and when voltage V is applied, In this state, the voltage is applied sequentially from the small capacitor on the side 1a side. Therefore, the small capacitor on the opposite side 1b side requires more time to store and discharge the charge than the small capacitor on the one side 1a side of the field 1. For this reason, when the voltage changes at a high frequency, the desired function as the capacitor cannot be performed.
[0004]
In the manufacturing process of the MOS capacitor, the threshold Vth for channel formation can be lowered by implanting capacitor dope into the surface portion of the P substrate 7 where the channel is formed. If the threshold value Vth is lowered in this way, the time required for charging and discharging is reduced even with a small capacitor on the opposite side 1b side of the field 1, so that a MOS capacitor capable of operating at a high frequency can be formed. it can.
[0005]
However, if such a MOS capacitor having a low threshold Vth is used in, for example, a Vpp switch circuit for selecting whether or not to supply the EEPROM write voltage Vpp, a leakage current increases, resulting in malfunction. It becomes easy to produce. Further, in the charge pump circuit for generating the write voltage Vpp of the EEPROM or the above-described Vpp switch circuit, the built-in capacitor exists even when the charge pump circuit or the Vpp switch circuit is not operated. The load capacity increases and the current consumption increases.
[0006]
[Problems to be solved by the invention]
As described above, the conventional MOS type capacitor has a problem that its function is reduced at a high frequency. Also, if the threshold value Vth is lowered so that it can operate at a high frequency, malfunctions are likely to occur when used in a Vpp switch circuit. Further, the Vpp switch circuit and the charge pump circuit using the conventional capacitor have a problem that the current consumption increases due to the load capacitance.
[0007]
The present invention has been made to solve such a problem, and an object of the present invention is to provide a Vpp switch circuit and a charge pump circuit using a highly reliable MOS capacitor that can operate even at a high frequency.
Another object of the present invention is to provide an EEPROM using such a Vpp switch circuit or charge pump circuit.
[0008]
[Means for Solving the Problems]
  The Vpp switch circuit according to claim 1 is:A first transistor having a drain connected to the write voltage Vpp, and a gate connected to the gate of the first transistor;A selection signal line for selecting whether or not to supply the write voltage Vpp;Second and third transistors connected in series between the gate and source of the first transistor, one end connected to the gate and drain of the second and third transistors, respectively, and the other end to the clock signal A pair of MOS capacitors each supplied with an inverted signal of the clock signal;WithA pair ofMOS capacitorEach ofIs formed on the surface of the semiconductor substrate so that the surface of the semiconductor substrate covers the partitioned field, and at least one opening is formed at a position corresponding to the inside of the field, and on the insulating film. A conductive layer having an opening corresponding to the opening of the insulating film, a first electrode layer electrically connected to the conductive layer, an opening of the conductive layer, and an opening of the insulating film And a second electrode layer electrically connected to the surface of the semiconductor substrate through the second inversion layer formed on the semiconductor substrate when the voltage of the first electrode layer exceeds a threshold voltage. By being electrically connected to this electrode layer, the capacitance of the MOS capacitor is formed between the first and second electrode layers.
[0009]
  The Vpp switch circuit according to claim 2 is the Vpp switch circuit according to claim 1, wherein each of the pair of MOS type capacitors isSecond andIt has a threshold value equal to or higher than that of the third transistor.
[0010]
The charge pump circuit according to claim 3 includes a plurality of MOS capacitors,
A plurality of transistors connected to the corresponding MOS type capacitors and connected in series to each other, each of the plurality of MOS type capacitors covering the field where the surface of the semiconductor substrate is partitioned An insulating film formed on the insulating film in which at least one opening is formed at a position corresponding to the inside of the field, and an opening formed on the insulating film and corresponding to the opening of the insulating film is formed. A conductive layer; a first electrode layer electrically connected to the conductive layer; and a second electrode layer electrically connected to the surface of the semiconductor substrate through the opening of the conductive layer and the opening of the insulating film The inversion layer generated on the semiconductor substrate when the voltage of the first electrode layer exceeds the threshold voltage is electrically connected to the second electrode layer, whereby the first and second Between electrode layers In which capacitance of the MOS capacitor is formed.
[0011]
  The EEPROM according to claim 4 is:bookA charge pump circuit for generating an input voltage Vpp, a memory cell array having a plurality of memory cells, andReA plurality of Vpp switch circuits for selectively supplying the write voltage Vpp generated by the large pump circuit to corresponding memory cells of the memory cell array,
  The charge pump circuit includes a plurality of MOS capacitors and a plurality of transistors connected to the corresponding MOS capacitors and connected in series to each other,
  Each Vpp switch circuit includes a first transistor having a drain connected to the write voltage Vpp, a selection signal line connected to the gate of the first transistor and for selecting whether to supply the write voltage Vpp, Second and third transistors connected in series between the gate and source of the first transistor, one end connected to the gate and drain of the second and third transistors, respectively, and the other end to the clock signal A pair of MOS capacitors to which an inverted signal of the clock signal is supplied,
  A plurality of MOS capacitors in the charge pump circuit and a pair of MOS capacitors in each Vpp switch circuitEach of the insulating film is formed on the surface of the semiconductor substrate so as to cover the field where the surface of the semiconductor substrate is partitioned, and at least one opening is formed at a position corresponding to the inside of the field, and the insulating film A conductive layer having an opening corresponding to the opening of the insulating film, a first electrode layer electrically connected to the conductive layer, an opening of the conductive layer, and the insulating film A second electrode layer electrically connected to the surface of the semiconductor substrate through the opening, and an inversion layer formed on the semiconductor substrate when the voltage of the first electrode layer exceeds a threshold voltage By being electrically connected to the second electrode layer, the capacitance of the MOS capacitor is formed between the first and second electrode layers.
[0012]
  The EEPROM according to claim 5 is the EEPROM according to claim 4, wherein the pair of MOS capacitors of each Vpp switch circuit includes a plurality of MOS capacitors and a plurality of transistors of the charge pump circuit, and each of the Vpp switch circuits.Second andIt has a threshold value equal to or higher than that of the third transistor.
[0013]
  2. The Vpp switch circuit according to claim 1, wherein at least one field contact is provided inside the field.A pair ofSince the MOS type capacitor is used, it can be operated at a high frequency and the drive capability is improved.
[0014]
  The Vpp switch circuit according to claim 2 is characterized in that in the Vpp switch circuit according to claim 1, the threshold values of the pair of MOS capacitors are respectivelySecond andSince it is set to a value equal to or higher than the threshold value of the third transistor, there is no fear that the level of the selection signal line is charged up by a leakage current, and erroneous selection of the selection signal line is prevented.
[0015]
In the charge pump circuit according to claim 3, since a plurality of MOS type capacitors each having at least one field contact are provided inside each field, the charge pump circuit can be operated at a high frequency and drive performance is improved. To do.
[0016]
  5. The charge pump circuit according to claim 4, wherein the charge pump circuit has a plurality of MOS capacitors each having at least one field contact provided inside the field.And a pair of MOS capacitors each provided with at least one field contact inside the field.Since a plurality of Vpp switch circuits are used, a highly reliable operation can be performed even at a high frequency.
[0017]
  In the EEPROM according to claim 5, in the EEPROM according to claim 4, the thresholds of the pair of MOS capacitors of each Vpp switch circuit are respectively the plurality of MOS capacitors, the plurality of transistors and the Vpp of the charge pump circuit. Switch circuitSecond andSince it is set to a value equal to or higher than the threshold value of the third transistor, there is no possibility that the level of the selection signal line in the Vpp switch circuit is charged up by the leakage current, and malfunction is prevented.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings.
1 and 2 show a MOS capacitor used in the present invention. A rectangular field 21 is defined on the surface of the P substrate 27 by a field oxide film 31. A polysilicon film 22 is formed on the field 21 via a gate oxide film 28, and an oxide film 29 is formed on the polysilicon film 22. Aluminum electrode layers 23 and 25 are formed on the oxide film 29. A part of the aluminum electrode layer 23 penetrates the oxide film 29 and is in contact with the polysilicon film 22 to form an aluminum contact 26. In addition, four openings 28 a are formed in the gate oxide film 28, and four openings 22 a are formed at positions corresponding to the polysilicon film 22. These openings 28 a and 22 a are uniformly arranged in the field 21. A part of the aluminum electrode layer 25 penetrates the oxide film 29, contacts the N diffusion layer 30 on the surface of the P substrate 27 through the opening 22 a of the polysilicon film 22 and the opening 28 a of the gate oxide film 28, A field contact 24 is formed here. That is, as shown in FIG. 1, four field contacts 24 are uniformly arranged inside the field 21, and these field contacts 24 are connected to the aluminum electrode layer 25.
[0019]
The P substrate 27 forms a semiconductor substrate, the gate oxide film 28 forms an insulating layer, the polysilicon film 22 forms a conductive layer, and the aluminum electrode layers 23 and 25 form first and second electrode layers, respectively.
[0020]
When a voltage V higher than the threshold Vth for channel formation is applied between the aluminum electrode layers 23 and 25, an N inversion layer 32 acting as a channel is formed in the field 21. Electric charges are accumulated in the portion where the field 21 and the polysilicon film 22 overlap through the gate oxide film 28, and function as a capacitor. In this MOS capacitor, the field contact 24 is arranged inside the field 21, so that the equivalent circuit is as shown in FIG. 3, and the electrodes are drawn from the center of many small capacitors. Therefore, the resistance is reduced, and it has been found that the frequency characteristics are improved as shown in FIG. 4 when compared with the conventional capacitor shown in FIGS. In the conventional capacitor, the capacitance is remarkably reduced as the frequency is increased. However, it is understood that the capacitor shown in FIGS. That is, normal operation can be performed at a higher frequency.
[0021]
Although the P substrate is used as the semiconductor substrate, a similar capacitor can be configured by using an N substrate.
[0022]
FIG. 5 shows a MOS capacitor in which eight field contacts 44 are arranged inside a rectangular field 41 in the same manner as the MOS capacitor shown in FIGS. A comparison with a conventional capacitor will be made using the capacitor of FIG. The size of the field 41 is 50 × 90 μm, the size of each of the eight openings 42a and 48a formed in the polysilicon film and the gate oxide film is 3.3 × 3.3 μm, and the sheet capacity of the gate is 0.3. Assuming 83 × 10 −15 F / μm 2, the static capacitance C1 of the capacitor in FIG. 5 is C1 = {(50 × 90) − (3.3 × 3.3 × 8)} × 0.83 × 10 −15 = 3.66 pF. On the other hand, in the conventional capacitor shown in FIG. 12 having the same size field as that of the capacitor of FIG. 5, the static capacitance C2 is C2 = 50 × 90 × 0.83 × 10−15 = 3.75 pF. Become. In the capacitor of FIG. 5, since eight field contacts 44 are arranged inside the field 41, the static capacitance is slightly reduced accordingly.
[0023]
Further, when the conductance β is calculated from the voltage distribution, L = (Lx + Ly) /2≈11.2 μm and W = {(22.5 × 25) / L} × 8≈401 μm in the capacitor of FIG. The conductance β1 is β1 = (W / L) × k≈35.8k, where k is a constant. On the other hand, in the conventional capacitor, L = 90 × 2 = 180 μm and W = 50/2 = 25 μm, so that the conductance β2 is β2 = 0.14k. By the way, since the resistance value is calculated as the reciprocal of conductance, the resistance value of the capacitor in FIG. 5 is about 1/250 compared to a conventional capacitor having the same size field.
[0024]
Further, an unnecessary load capacity is generated in the portion of the field 41 where the field contact 44 is disposed. In the capacitor of FIG. 5, since eight field contacts 44 are arranged, an unnecessary load capacity corresponding to the area S1 = 3.3 × 3.3 × 8 = 87.1 μm 2 is generated. On the other hand, in a capacitor having a conventional structure, a field contact is formed linearly along one side of a rectangular field. Therefore, along the short side of the field of 50 × 90 μm as in the second embodiment. When a field contact having a width of 3.3 μm is formed, an unnecessary load capacity corresponding to the area S2 = 3.3 × 50 = 165 μm2 is generated. That is, in the capacitor of FIG. 5, the unnecessary load capacity is reduced to about ½.
Also in a capacitor having a conventional structure, the resistance value can be lowered by implanting capacitor dope, but in this case, the entire field always operates as a capacity, and thus an unnecessary load capacity increases.
[0025]
In the MOS capacitor shown in FIG. 6, the field is divided into four fields 51, and a field contact 54 is formed at the center of each field 51. These four field contacts 54 are connected to one aluminum electrode layer 55. This capacitor has the same characteristics as the capacitors of FIGS. 1 and 2, but the field and the like are divided so that the characteristics such as capacitance and resistance can be easily simulated.
[0026]
In the MOS capacitor shown in FIG. 7, a single field contact 64 is formed at the center of the field 61, and this field contact 64 is connected to the aluminum electrode layer 65. As described above, even with a simple structure in which the field contact is provided only in the central portion of the field, similarly, the resistance value is reduced and unnecessary load capacitance is reduced, and the frequency characteristics are improved.
[0027]
Embodiment 1 FIG.
FIG. 8 shows a charge pump circuit according to Embodiment 1 of the present invention. A plurality of transistors 71 are connected in series, and the MOS capacitor 72 shown in FIGS. 1 to 7 is connected to each transistor 71. A clock signal CLK and an inverted signal of the clock signal CLK by the inverter circuit 73 are supplied to every other capacitor 72. With such a configuration, the voltage V supplied to the transistor 71 located at one end of the series connection._DDIs boosted to the voltage Vpp and output from the transistor 71 located at the other end of the series connection. The relationship between the clock signal CLK and the output voltage Vpp in this charge pump circuit is shown in the timing chart of FIG.
[0028]
The drive capability of the charge pump circuit is substantially determined by the frequency of the clock signal CLK and the capacitance of the capacitor used. In the first embodiment, since the capacitor 72 that can operate at a higher frequency than the conventional one is used, even if the charge pump circuit is formed with the same pattern area as the conventional one, a charge pump circuit having a better driving capability can be obtained. . Further, in the capacitor 72 according to the present invention, since the load capacity can be reduced, the margins of Vcc and Icc can be improved.
[0029]
Embodiment 2. FIG.
FIG. 10 shows a Vpp switch circuit according to the second embodiment. Transistors 82 and 83 are connected in series between the gate and source of the transistor 81, and the MOS capacitors 84 and 85 shown in FIGS. 1 to 7 are connected to the transistors 82 and 83, respectively. The capacitors 84 and 85 are supplied with the clock signal CLK and an inverted signal of the clock signal CLK from the inverter circuit 86. A selection signal line SEL for selecting whether or not to supply the write voltage Vpp is connected to the gate of the transistor 81. When the selection signal line SEL is at a high level, the voltage Vpp supplied to the drain of the transistor 81 is supplied to the selection signal line SEL. When the selection signal line SEL is at a low level, the voltage Vpp is not supplied to the selection signal line SEL.
[0030]
The drive capability of the Vpp switch circuit is substantially determined by the frequency of the clock signal CLK and the capacitance of the capacitor used. In the second embodiment, the capacitors 84 and 85 that can operate at a higher frequency than the conventional one are used. Therefore, even if the Vpp switch circuit is formed with the same pattern area as the conventional one, a circuit having a better driving capability can be obtained. . In addition, since the capacitors 84 and 85 according to the present invention can reduce the load capacity, the margins of Vcc and Icc can be improved.
[0031]
Embodiment 3 FIG.
  If the threshold value of the capacitor used in the Vpp switch circuit of the second embodiment, that is, the voltage level Vth necessary for forming the inversion layer is set to be equal to or higher than the threshold values of other transistors in the Vpp switch circuit. , Prevention of malfunctionStopCan be planned. When the selection signal line SEL of the Vpp switch circuit is at a low level, the voltage Vpp is not supplied to the capacitors 84 and 85, but the threshold value Vth of these capacitors is set lower than the threshold values of the transistors 82 and 83. There is a possibility that the level of the selection signal line SEL is inverted by being charged up by the leakage current. Thus, if the threshold value Vth of the capacitors 84 and 85 is set higher than the threshold values of the transistors 82 and 83 as in the third embodiment, erroneous selection of the selection signal line SEL can be prevented.
[0032]
Embodiment 4 FIG.
  FIG. 11 shows an EEPROM according to the fourth embodiment. The EEPROM uses the charge pump circuit shown in the first embodiment and the Vpp switch circuit shown in the second or third embodiment. A Vpp switch circuit group 93 is connected to a memory cell array 92 having a plurality of memory cells 91. Vpp switch circuit group 93 includes the plurality of Vpp switch circuits of the sixth or seventh embodiment provided corresponding to each bit line and each word line of memory cell array 92, respectively. That is, each Vpp switch circuit is provided with at least one field contact inside each field as shown in FIG.MOS type capacitors 84 and 85, a selection signal line SEL for selecting whether or not to supply the write voltage Vpp,, MTransistors 81 to 83 connected to the OS type capacitors 84 and 85 and turned on / off according to the level of the selection signal line are provided.
[0033]
  The charge pump circuit 94 shown in the first embodiment is connected to the Vpp switch circuit group 93. In other words, as shown in FIG. 8, the charge pump circuit 94 includes a plurality of charge pump circuits 94 each provided with at least one field contact inside the field.MA plurality of OS type capacitors 72 connected to the corresponding MOS type capacitors 72 and connected in series to each other.NoA transistor 71. Further, a clock generation circuit 95 is connected to the charge pump circuit 94. A control circuit 96 is connected to the Vpp switch circuit group 93. Since a plurality of Vpp switch circuits and charge pump circuits according to the present invention are used, a reliable operation can be performed at a high frequency and margins of Icc and Vcc can be improved.
[0034]
【The invention's effect】
  As described above, the Vpp switch circuit according to claim 1 isA first transistor having a drain connected to the write voltage Vpp, and a gate connected to the gate of the first transistor;A selection signal line for selecting whether or not to supply the write voltage Vpp;Second and third transistors connected in series between the gate and source of the first transistor, one end connected to the gate and drain of the second and third transistors, respectively, and the other end to the clock signal A pair of MOS capacitors each supplied with an inverted signal of the clock signal;WithA pair ofMOS capacitorEach ofIs formed on the surface of the semiconductor substrate so that the surface of the semiconductor substrate covers the partitioned field, and at least one opening is formed at a position corresponding to the inside of the field, and on the insulating film. A conductive layer having an opening corresponding to the opening of the insulating film, a first electrode layer electrically connected to the conductive layer, an opening of the conductive layer, and an opening of the insulating film And a second electrode layer electrically connected to the surface of the semiconductor substrate through the second inversion layer formed on the semiconductor substrate when the voltage of the first electrode layer exceeds a threshold voltage. Since the capacitance of the MOS capacitor is formed between the first and second electrode layers by being electrically connected to the first electrode layer, malfunction can be prevented even when operated at a high frequency. Can improve drive capacity. .
[0035]
  The Vpp switch circuit according to claim 2 is the Vpp switch circuit according to claim 1, wherein each of the pair of MOS type capacitors isSecond andSince it has a threshold value equal to or higher than the threshold value of the third transistor, there is no fear that the level of the selection signal line is charged up by a leakage current, and erroneous selection of the selection signal line is prevented to further improve reliability. Can be planned.
[0036]
The charge pump circuit according to claim 3 includes a plurality of MOS capacitors,
A plurality of transistors connected to the corresponding MOS type capacitors and connected in series to each other, each of the plurality of MOS type capacitors covering the field where the surface of the semiconductor substrate is partitioned An insulating film formed on the insulating film in which at least one opening is formed at a position corresponding to the inside of the field, and an opening formed on the insulating film and corresponding to the opening of the insulating film is formed. A conductive layer; a first electrode layer electrically connected to the conductive layer; and a second electrode layer electrically connected to the surface of the semiconductor substrate through the opening of the conductive layer and the opening of the insulating film The inversion layer generated on the semiconductor substrate when the voltage of the first electrode layer exceeds the threshold voltage is electrically connected to the second electrode layer, whereby the first and second Between electrode layers The capacitance of the MOS capacitor is formed, it is possible to improve the driving capability it is possible to prevent a malfunction even if operating at high frequencies.
[0037]
  The EEPROM according to claim 4 is:,bookA charge pump circuit for generating an input voltage Vpp, a memory cell array having a plurality of memory cells, andReA plurality of Vpp switch circuits for selectively supplying the write voltage Vpp generated by the large pump circuit to corresponding memory cells of the memory cell array,The charge pump circuit includes a plurality of MOS capacitors and a plurality of transistors connected to the corresponding MOS capacitors and connected in series to each other, and each Vpp switch circuit has a drain connected to the write voltage Vpp. The first transistor, the selection signal line connected to the gate of the first transistor and for selecting whether or not to supply the write voltage Vpp, and the gate and the source of the first transistor are connected in series. A pair of MOS transistors, one end of which is connected to the gate and drain of the second and third transistors, respectively, and the other end of which is supplied with a clock signal and an inverted signal of the clock signal. A plurality of MOS type capacitors of the charge pump circuit and each Vpp switch. A pair of MOS type capacitor circuitEach of the insulating film is formed on the surface of the semiconductor substrate so as to cover the field where the surface of the semiconductor substrate is partitioned, and at least one opening is formed at a position corresponding to the inside of the field, and the insulating film A conductive layer having an opening corresponding to the opening of the insulating film, a first electrode layer electrically connected to the conductive layer, an opening of the conductive layer, and the insulating film A second electrode layer electrically connected to the surface of the semiconductor substrate through the opening, and an inversion layer formed on the semiconductor substrate when the voltage of the first electrode layer exceeds a threshold voltage Since the capacitance of the MOS capacitor is formed between the first and second electrode layers by being electrically connected to the second electrode layer, a highly reliable operation can be performed even at a high frequency. it can.
[0038]
  The EEPROM according to claim 5 is the EEPROM according to claim 4, wherein the pair of MOS capacitors of each Vpp switch circuit includes a plurality of MOS capacitors and a plurality of transistors of the charge pump circuit, and each of the Vpp switch circuits.Second andSince it has a threshold value equal to or higher than the threshold value of the third transistor, the level of the selection signal line in each Vpp switch circuit can be prevented from being charged up by a leakage current, and erroneous selection of the selection signal line can be prevented. Further, the reliability can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view showing a first MOS capacitor used in the present invention.
FIG. 2 is a cross-sectional view taken along the line II of FIG.
FIG. 3 is an equivalent circuit diagram of the capacitor of FIG.
FIG. 4 is a diagram illustrating frequency characteristics of the capacitor of FIG. 1;
FIG. 5 is a plan view showing a second MOS capacitor used in the present invention.
FIG. 6 is a plan view showing a third MOS capacitor used in the present invention.
FIG. 7 is a plan view showing a fourth MOS capacitor used in the present invention.
FIG. 8 is a circuit diagram showing a charge pump circuit according to the first embodiment.
FIG. 9 is a timing chart showing the operation of the first embodiment.
FIG. 10 is a circuit diagram showing a Vpp switch circuit according to a second embodiment.
FIG. 11 is a block diagram showing an EEPROM according to the fourth embodiment.
FIG. 12 is a plan view showing a conventional MOS capacitor.
13 is a cross-sectional view taken along line II-II in FIG.
14 is an equivalent circuit diagram of the capacitor of FIG. 12;
[Explanation of symbols]
21, 41, 51, 61 field, 22 polysilicon film, 22a, 28a, 42a, 48a opening, 23, 25, 55, 65 aluminum electrode layer, 24, 44, 54, 64 field contact, 26 aluminum contact, 27 P substrate, 28 gate oxide film, 71, 81, 82, 83 transistor, 72, 84, 85 MOS type capacitor, 91 memory cell, 92 memory cell array, 93 Vpp switch circuit group, 94 charge pump circuit.

Claims (5)

A first transistor having a drain connected to the write voltage Vpp;
A selection signal line connected to the gate of the first transistor and for selecting whether or not to supply the write voltage Vpp;
Second and third transistors connected in series between the gate and source of the first transistor;
A pair of MOS capacitors having one end connected to the gate and drain of each of the second and third transistors and the other end supplied with a clock signal and an inverted signal of the clock signal, respectively.
Each of the pair of MOS capacitors is
An insulating film formed on the surface of the semiconductor substrate so as to cover the partitioned field of the surface of the semiconductor substrate and having at least one opening formed at a position corresponding to the inside of the field;
A conductive layer formed on the insulating film and having an opening corresponding to the opening of the insulating film;
A first electrode layer electrically connected to the conductive layer;
A second electrode layer electrically connected to the surface of the semiconductor substrate through the opening of the conductive layer and the opening of the insulating film;
An inversion layer formed on the semiconductor substrate when the voltage of the first electrode layer exceeds a threshold voltage is electrically connected to the second electrode layer, whereby the first and second A Vpp switch circuit, wherein a capacitance of the MOS capacitor is formed between electrode layers. 2. The Vpp switch circuit according to claim 1, wherein each of the pair of MOS capacitors has a threshold value equal to or greater than a threshold value of the second and third transistors. A plurality of MOS capacitors;
A plurality of transistors each connected to a corresponding MOS capacitor and connected in series with each other,
Each of the plurality of MOS capacitors is
An insulating film formed on the surface of the semiconductor substrate so as to cover the partitioned field of the surface of the semiconductor substrate and having at least one opening formed at a position corresponding to the inside of the field;
A conductive layer formed on the insulating film and having an opening corresponding to the opening of the insulating film;
A first electrode layer electrically connected to the conductive layer;
A second electrode layer electrically connected to the surface of the semiconductor substrate through the opening of the conductive layer and the opening of the insulating film;
An inversion layer formed on the semiconductor substrate when the voltage of the first electrode layer exceeds a threshold voltage is electrically connected to the second electrode layer, whereby the first and second A charge pump circuit, wherein a capacitance of the MOS capacitor is formed between electrode layers. A charge pump circuit for generating a write voltage Vpp;
A memory cell array having a plurality of memory cells;
A plurality of Vpp switch circuits for selectively supplying a write voltage Vpp generated by the charge pump circuit to a corresponding memory cell of the memory cell array,
The charge pump circuit includes a plurality of MOS capacitors and a plurality of transistors connected to the corresponding MOS capacitors and connected in series to each other,
Each Vpp switch circuit includes a first transistor having a drain connected to the write voltage Vpp, a selection signal line connected to the gate of the first transistor and for selecting whether or not to supply the write voltage Vpp. The second and third transistors connected in series between the gate and source of the first transistor, one end connected to the gate and drain of the second and third transistors, respectively, and the other end A pair of MOS capacitors to which a clock signal and an inverted signal of the clock signal are respectively supplied;
Each of the plurality of MOS capacitors of the charge pump circuit and the pair of MOS capacitors of each Vpp switch circuit includes:
An insulating film formed on the surface of the semiconductor substrate so as to cover the partitioned field of the surface of the semiconductor substrate and having at least one opening formed at a position corresponding to the inside of the field;
A conductive layer formed on the insulating film and having an opening corresponding to the opening of the insulating film;
A first electrode layer electrically connected to the conductive layer;
A second electrode layer electrically connected to the surface of the semiconductor substrate through the opening of the conductive layer and the opening of the insulating film;
An inversion layer formed on the semiconductor substrate when the voltage of the first electrode layer exceeds a threshold voltage is electrically connected to the second electrode layer, whereby the first and second An EEPROM, wherein a capacitance of the MOS capacitor is formed between electrode layers. A pair of MOS capacitors of each Vpp switch circuit has a threshold value equal to or higher than the threshold values of the plurality of MOS capacitors and the plurality of transistors of the charge pump circuit and the second and third transistors of each Vpp switch circuit . 5. The EEPROM according to claim 4, further comprising:

Images