JP3978873B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method suitable for manufacturing an insulated gate field effect transistor using a single crystal silicon layer epitaxially grown on an insulating substrate as an active region.
[0002]
[Prior art]
Conventionally, a TFT (thin film transistor), which is a MOSFET (metal-oxide-semiconductor field effect transistor) using a single crystal silicon layer formed on a substrate, has an electron transfer several times larger than that using a polysilicon layer. And is known to be suitable for high-speed operation (Reference, RPZingg et al, “First MOS transistors on Insulator by Silicon Saturated Liquid Solution Epitaxy”. IEEE ELECTRON DEVICE LETTERS.VOL.13, NO. 5, MAY 1992, p294-6., Japanese Patent Publication No. 4-57098, Masayoshi Matsumura, "Thin Film Transistor" Applied Physics, Vol. 65, No. 8 (1996) pp 842-848).
[0003]
In such a semiconductor element, in order to form a single crystal silicon layer on a substrate, the following various film formation techniques (1) to (4) are known.
[0004]
(1) Using a single crystal silicon substrate as a seed, a silicon epitaxy layer is formed by cooling from an indium silicon solution or an indium gallium silicon solution heated to 920 to 930 ° C., and a silicon semiconductor is formed on this layer Create a layer. (Reference 1, Soo Hong Lee, “VERY-LOW-TEMPERATURE LIQUID-PHASE EPITAXIAL GROWTH OF SILICON”. MATERIALS LETTERS. Vol.9.No.2,3 (Jan., 1990) pp53-56. Reference2, R. Bergmann et al, "MOS transistors with epitaxial Si, laterally grown over SiO / Sub 2 / by liquid phase epitaxy." J. Applied Physics A, vol. A54, no. 1 p.103-5. Reference 3, RPZingg et al, "First MOS transistors on Insulator by Silicon Saturated Liquid Solution Epitaxy." IEEE ELECTRON DEVICE LETTERS.VOL.13, NO.5, MAY 1992 p294-6.)
[0005]
(2) Silicon is epitaxially grown on the sapphire substrate. (Reference 4, G.A.Garcia, R.E.Reedy, and M.L.Burger, "High-quality CMOS in thin (100 nm) silicon on sapphire," IEEE ELECTRON DEVICE LETTERS.VOL.9, pp32-34, Jan.1988.)
[0006]
(3) A silicon layer is formed on the insulating substrate by oxygen ion implantation. (Reference 5, K. Izumi, M. Doken, and H. Ariyoshtl, "CMOS device fabrication on buried SiO₂layers formed by oxygen implantation into silicon, "Electron.Lett., vol.14, no.18, pp593-594, Aug.1978.)
[0007]
(4) A step is formed on a quartz substrate, a polysilicon layer is formed thereon, and this is then heated to 1400 ° C. or higher with a laser beam or a strip heater. The heated polysilicon layer forms an epitaxial growth layer with the step formed on the quartz substrate as a nucleus. (Reference 6, Shizujiro Furukawa, “Graphoepitaxy”, Journal of Electronic Communication Society, Vol. 66, No. 5, pp 486-489. (1983. May). Reference 7, Geis, MW, et al .: “Crystallographic orientation of silicon on an amorphous substrate using an artificial-relief grating and laser crystallization ", Appl. Phys. Letter, 35, 1, pp71-74 (July 1979). Reference 8, Geis, MW, et al .:" Silicon graphoepitaxy ", Jpn.J.Appl.Phys., Suppl.20-1, pp.39-42 (1981).)
[0007]
[Problems to be solved by the invention]
However, in the known techniques so far, there is no technique that can form a silicon epitaxy layer on a large glass plate with a relatively low strain point. Further, silicon cannot be epitaxially grown at a low temperature and uniformly in a technique in which steps are formed on a glass plate and silicon is grown using this as a nucleus for epitaxial growth.
[0008]
An object of the present invention is to provide a method capable of epitaxially growing a silicon layer uniformly at a low temperature even in a large glass substrate having a relatively low strain point, and thereby forming a semiconductor element having a high current density at a high speed. is there.
[0009]
[Means for Solving the Problems]
  The present invention
    A step of forming a step on the insulating substrate;
    (A) forming a polysilicon or amorphous silicon layer with a predetermined thickness on the insulating substrate including the step;
    (B) on the insulating substrate and on or under the polysilicon or amorphous silicon layer;See belowForming a low melting point metal layer, or
    (C) Silicon is contained on the insulating substrate including the step.See belowA step of forming a low melting point metal layer,
    The polysilicon or amorphous silicon layer or the silicon of the low melting point metal layer is transformed into the low melting point metal layer by heat treatment.Or a melt of the low melting point metalA step of dissolving in
    Next, a step of epitaxially growing the polysilicon or the amorphous silicon layer or the silicon of the low-melting-point metal layer by the cooling process using the step as a seed to deposit a single crystal silicon layer;,
    A step of removing the low melting point metal layer remaining on the single crystal silicon layer;
For forming a single crystal silicon layerAssumingIs.
[0010]
  That isIn addition to the step of depositing the single crystal silicon layer described above, the present invention further includes:Remain inRemoving the low melting point metal layer, and then subjecting the single crystal silicon layer to a predetermined treatment.Forming a constituent layer of an insulated gate field effect transistor having the single crystal silicon layer existing inside the step as a channel region and having a source region and a drain region on both sides thereofSemiconductor device manufacturing method further comprising the step of:TheIt is to provide.
[0011]
According to the method of the present invention, a step formed on an insulating substrate is used as a seed, and a silicon epitaxial layer is formed by depositing single crystal silicon after dissolving polysilicon, amorphous silicon, or silicon in a low melting point metal layer. Therefore, the remarkable effects shown in the following (A) to (C) can be obtained.
[0012]
(A) The above polysilicon or amorphous silicon layer can be formed by a method such as low pressure CVD (chemical vapor deposition: substrate temperature 500 to 600 ° C.), and the above low melting point metal layer can be formed by a method such as sputtering. Furthermore, since the heat treatment temperature during the above-described silicon epitaxial growth can be 930 ° C. or less, a silicon single crystal film can be uniformly formed on the insulating substrate at a low temperature (eg, 920 to 930 ° C.).
[0013]
(B) Accordingly, a glass substrate or a ceramic substrate having a relatively low strain point can be easily obtained, a substrate with low cost and good physical properties can be used, and the size of the substrate can be increased.
[0014]
(C) The electron mobility of a silicon single crystal thin film formed on a glass substrate or the like at a low temperature is 540 cm.²/ V · sec (reference 3 mentioned above), which is as large as a silicon substrate, so it can be used for high-speed, high-current density top-gate, bottom-gate, and dual-gate LCDs (liquid crystal display devices). TFT, EL (electroluminescence element), FED (field emission display element) transistors, semiconductor elements such as high performance diodes, solar cells, capacitors, resistors, or electronic circuits in which these are integrated are made of glass. It can be created on a substrate or the like.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
  In the method of the present invention, the step is formed by dry etching such as reactive ion etching, and the polysilicon or amorphous silicon layer is formed by a low pressure CVD method (substrate temperature of about 500 to 650 ° C.) or a plasma CVD method.OrSputtering method (substrate temperature about 100-400 ° C)such asAfter forming the low melting point metal layer to a thickness of, for example, several μm to 0.005 μm by a low temperature film formation technique, and further depositing the low melting point metal layer to a thickness of, for example, several ten to several hundred times the polysilicon layer by a sputtering method, The heat treatment is preferably performed.
[0016]
  Also, a glass substrate is used as the insulating substrateCanAnd at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum.ByForm.
[0017]
In this case, when the low melting point metal layer is formed of metallic indium, the heat treatment is performed at 850 to 1100 ° C. (preferably 900 to 950 ° C.) in a hydrogen atmosphere to form an indium / silicon melt, and the low melting point metal is formed. When the layer is formed of metal indium gallium or gallium, the heat treatment is performed in a hydrogen atmosphere at 300 to 1100 ° C. (preferably 350 to 600 ° C.) or 400 to 1100 ° C. (preferably 420 to 600 ° C.). It can be a gallium-silicon melt or a gallium-silicon melt. In addition to a method of heating the entire substrate uniformly using an electric furnace, a lamp, or the like, the substrate can be heated by a method of locally heating only a predetermined place with an optical laser, an electron beam, or the like.
[0018]
As is apparent from the state diagram shown in FIG. 11, the melting point of the low melting point metal containing silicon is lowered according to the proportion of the low melting point metal. When indium is used, an indium melt layer containing silicon (for example, containing 1% by weight) is formed at a substrate temperature of 850 to 1100 ° C. Quartz plate glass can be used as the substrate up to about 1100 ° C. Up to 850 ° C., glass having lower heat resistance can be used. However, 850 ° C. to 600 ° C. is determined from the maximum use temperature (mostly the same as the strain point) of the aluminosilicate glass. Even when gallium is used, a gallium melt layer containing silicon (for example, containing 1% by weight) can be formed at a substrate temperature of 400 to 1100 ° C. for the same reason as described above.
[0019]
In either case, a glass substrate with a low strain point can be used as the substrate, so a large glass substrate (1 m²It is possible to form a semiconductor crystal layer on the above, but when the epitaxy temperature is as low as 350 to 600 ° C., glass having a low strain point of 470 to 670 ° C. should be used as the glass substrate. it can. This is inexpensive, can be easily made into a thin plate, and can produce a long rolled glass plate. By using this, a thin epitaxy layer can be continuously or discontinuously produced on a long rolled glass plate using the above method.
[0020]
Thus, since the constituent elements easily diffuse from the glass into the upper layer of the glass having a low strain point, a thin film of the diffusion barrier layer (for example, silicon nitride: about 10 to 1000 mm thick) is used for the purpose of suppressing this. ).
[0021]
After the single crystal silicon layer is deposited from the low melting point metal in which the silicon is dissolved by slow cooling, using the step as a seed, the low melting point metal layer is dissolved and removed with hydrochloric acid or the like, and then the A semiconductor element can be manufactured by performing predetermined treatment on the single crystal silicon layer.
[0022]
As described above, the low melting point metal thin film such as metal indium deposited on the single crystal silicon layer after cooling is dissolved and removed using hydrochloric acid or the like.¹⁶(Atoms / cc and so on) can be made to remain, so that a P-type semiconductor is produced immediately after the production. This is therefore convenient for the fabrication of N-channel MOS transistors. However, since an N-type semiconductor crystal layer can be formed by ion-implanting an appropriate amount of N-type impurities such as phosphorus atoms, a P-channel MOS transistor can be formed. For this reason, a CMOS transistor can also be produced. If a suitable amount of a Group 3 or Group 5 element (B, P, Sb, As, etc.) having high solubility is separately doped when forming a polysilicon film or a low-melting point metal layer, the P type of the growing silicon epi layer / N type and / or carrier concentration can be controlled arbitrarily.
[0023]
As described above, the single crystal silicon layer epitaxially grown on the substrate is applied to the channel region, the source region, and the drain region of the insulated gate field effect transistor, and the impurity species and / or the concentration of each region can be controlled. it can.
[0024]
Next, the present invention will be described in more detail with respect to preferred embodiments.
[0025]
<First Embodiment>
A first embodiment will be described with reference to FIGS.
[0026]
First, as shown in FIG. 1A, a photoresist 2 is formed in a predetermined pattern on one main surface of a quartz glass substrate 1, and this is used as a mask, for example, CF_FourF of plasma⁺Irradiation with ions 3 and a plurality of steps 4 are formed on the substrate 1 by reactive ion etching (RIE). In this case, the step 4 serves as a seed for epitaxial growth of single crystal silicon, which will be described later, and may have a depth d of 0.1 μm and a width w of 1.5 to 1.9 μm.
[0027]
Next, as shown in FIG. 1B, after the photoresist 2 is removed, the polysilicon film 5 is formed on the entire surface including the step 4 by a known low pressure CVD method (substrate temperature: about 500 to 650 ° C.) or plasma CVD method. Is deposited to a thickness of several μm to 0.005 μm (for example, 0.1 μm).
[0028]
Next, as shown in FIG. 1 (3), a metal indium film 6 is formed on the polysilicon film 5 by a thickness of several to several hundreds times the thickness of the polysilicon film 5 by sputtering or vacuum deposition (for example, 10 to 10 times). 15 μm).
[0029]
Next, the substrate 1 is held at 1000 ° C. or lower, particularly 920 to 930 ° C. for about 5 minutes under a hydrogen atmosphere. Thereby, the polysilicon 5 is dissolved in the melt of the metal indium 6.
[0030]
Then, by gradually cooling, the silicon dissolved in the metal indium is epitaxially grown as shown in FIG. 1 (4) using the step 4 as a seed, and a single crystal having a thickness of about 0.1 μm, for example. Deposited as a silicon layer 7.
[0031]
In this case, the (100) plane of the single crystal silicon layer 7 is epitaxially grown on the substrate, which is due to a known phenomenon called graphoepitaxy (the above-mentioned documents 6, 7, 8). reference). As shown in FIG. 5, when a vertical wall such as the step 4 is formed on the amorphous substrate (glass) 1 and an epitaxy layer is formed thereon, a random wall as shown in FIG. As shown in FIG. 5B, the (100) plane grows along the surface of the step 4 in the case of the plane orientation. The size of the single crystal grains increases in proportion to the temperature and time. However, when the temperature and time are reduced and shortened, the interval between the steps must be shortened. Further, the crystal orientation of the growth layer can be controlled by variously changing the shape of the step as shown in FIGS. When creating a MOS transistor, the (100) plane is most often used.
[0032]
Thus, after depositing the single crystal silicon layer 7 on the substrate 1 by graphoepitaxy, the metal indium 6 on the surface side is dissolved and removed with hydrochloric acid or the like as shown in FIG. A MOS transistor (TFT) having a channel region as a channel region is manufactured.
[0033]
That is, as shown in FIG. 2 (6), a gate oxide film 8 having a thickness of 350 mm is formed on the surface of the single crystal silicon layer 7 by oxidation treatment (950 ° C.).
[0034]
Next, as shown in FIG. 2 (7), in order to control the impurity concentration of the channel region for the N-channel MOS transistor, the P-channel MOS transistor portion is masked with a photoresist 9, and P-type impurity ions (for example, B⁺) 10 for example 2.7 × 10 at 10 kV¹¹  atoms / cm²Then, the silicon layer 11 is formed by further implanting the conductivity type of the single crystal silicon layer 7 into P type.
[0035]
Next, as shown in FIG. 2 (8), in order to control the impurity concentration of the channel region for the P-channel MOS transistor, this time, the N-channel MOS transistor portion is masked with the photoresist 12, and N-type impurity ions (for example, P⁺) 13 for example 1 × 10 at 10 kV¹¹atoms / cm²The silicon layer 14 is formed by compensating the P-type of the single crystal silicon layer 7 by implanting with a dose amount of
[0036]
Next, as shown in FIG. 3 (9), a phosphorus-doped polysilicon layer 15 as a gate electrode material is deposited to a thickness of 4000 mm by, for example, a CVD method (620 ° C.).
[0037]
Next, as shown in FIG. 3 (10), a photoresist 16 is formed in a predetermined pattern, and using this as a mask, the polysilicon layer 15 is patterned into a gate electrode shape. Further, after removing the photoresist 16, FIG. For example, as shown in (11) of FIG.₂An oxide film 17 is formed on the surface of the gate polysilicon 15 by an oxidation process therein.
[0038]
Next, as shown in FIG. 3 (12), the P-channel MOS transistor portion is masked with a photoresist 18, and N-type impurities such as As⁺The ion 19 is 5 × 10 at 20 kV, for example.¹⁵atoms / cm²At a dose of 950 ° C. for 40 minutes, N₂N channel MOS transistor N by annealing in⁺A type source region 20 and a drain region 21 are formed.
[0039]
Next, as shown in FIG. 4 (13), the N-channel MOS transistor portion is masked with a photoresist 22, and P-type impurities such as B⁺For example, the ion 23 is 5 × 10 at 10 kV.¹⁵atoms / cm²Ion implantation at 900 ° C. for 5 minutes, N₂P channel MOS transistor P by annealing in⁺A type source region 24 and a drain region 25 are formed.
[0040]
Next, as shown in (14) of FIG.₂The film 26 is laminated to a thickness of 500 mm at, for example, 750 ° C., the SiN film 27 is laminated to a thickness of, for example, 2000 mm at 420 ° C., and the boron and phosphorus-doped silicate glass (BPSG) film 28 is reflowed as a reflow film, for example, 6000 mm The BPSG film 28 is formed, for example, at 900 ° C. with N₂Reflow in.
[0041]
Next, as shown in (15) of FIG. 4, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is deposited on the entire surface including each hole to a thickness of 1 μm at 150 ° C. by sputtering or the like. Then, this is patterned to form the source or drain electrode 29 (S or D) and the gate extraction electrode or wiring 30 (G) of each of the P-channel MOSFET and N-channel MOSFET, thereby completing each MOS transistor.
[0042]
As described above, according to the present embodiment, the following significant operational effects can be obtained.
[0043]
(A) The silicon single crystal thin film 7 can be uniformly formed on the glass substrate 1 at a low temperature of 920 to 930 ° C.
[0044]
(B) Therefore, since a silicon single crystal thin film can be formed not only on a glass substrate but also on an insulating substrate such as a ceramic substrate, a substrate material having a low strain point, low cost and good physical properties can be arbitrarily selected. Also, the substrate can be enlarged.
[0045]
(C) The electron mobility of the silicon single crystal thin film 7 formed on the glass substrate or the like is 540 cm.²Since / v · sec, which is a large value equivalent to that of a silicon substrate, can be obtained, a transistor having a high current density can be formed at high speed. In addition to transistors, diodes, solar cells, capacitors, resistors, and the like, and electronic circuits in which these are integrated can be formed on a glass substrate. The process of forming a silicon semiconductor element such as a MOS transistor is almost the same as a conventionally known polysilicon TFT manufacturing process.
[0046]
<Second Embodiment>
A second embodiment will be described with reference to FIGS.
[0047]
In this embodiment, as compared with the first embodiment described above, glass having a low strain point of about 670 ° C. is used as the substrate 1 in the process shown in FIG. It is easy to increase the size, and if it is thinned (for example, 50 μm thick), it can be rolled / longened, and such a glass plate is adopted. Of course, a quartz substrate can also be employed.
[0048]
And after forming the level | step difference 4 like the above-mentioned, in the process shown in (2) of FIG. 1, well-known plasma CVD method, sputtering method (substrate temperature about 100-400 degreeC), or well-known low pressure CVD method (substrate temperature). The polysilicon film 5 (or amorphous silicon film) is deposited on the entire surface including the step 4 to a thickness of several μm to 0.005 μm (for example, 0.1 μm) by about 500 to 600 ° C.
[0049]
Next, in the step shown in FIG. 1 (3), a metal indium / gallium film (or metal gallium film) is deposited on the polysilicon film 5 by several tens to several hundred times of the polysilicon film 5 by sputtering or vacuum deposition. To a thickness (for example, 10 to 20 μm).
[0050]
Next, the substrate 1 is held at 350 to 450 ° C. (or 450 to 600 ° C.) for about 5 minutes in a hydrogen atmosphere. As a result, the polysilicon 5 (or amorphous silicon) is dissolved in the metal indium gallium melt or the metal gallium melt.
[0051]
Next, by gradually cooling, the silicon dissolved in the metal indium gallium (or metal gallium) is epitaxially grown as shown in FIG. It is deposited as a single crystal silicon layer 7 of about 0.1 μm.
[0052]
In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate in the same manner as described above, but the shape of the step is changed variously as shown in FIGS. Thus, the crystal orientation of the growth layer can be controlled.
[0053]
Thus, after depositing the single crystal silicon layer 7 on the substrate 1 by graphoepitaxy, the metal indium gallium (or metal gallium) on the surface side is dissolved and removed with hydrochloric acid or the like as shown in (5) of FIG. Then, the single crystal silicon layer 7 is patterned to manufacture a MOS transistor (TFT).
[0054]
That is, as shown in FIG. 7 (6), the surface of the single crystal silicon layer 7 is made of SiO 2 having a thickness of 2000 mm by plasma CVD at 400 ° C., for example.₂A gate insulating film composed of the film 40 and the SiN film 41 having a thickness of 500 mm is formed.
[0055]
Next, as shown in FIG. 7 (7), in order to control the impurity concentration of the channel region for the N-channel MOS transistor, P-type impurity ions (for example, B⁺) 10 for example 2.7 × 10 at 10 kV¹¹  atoms / cm²Then, the silicon layer 11 is formed by further implanting the conductivity type of the single crystal silicon layer 7 into P type.
[0056]
Next, as shown in FIG. 7 (8), a MoTa layer 42 (Mo 15%, Ta 85%) as a gate electrode material is deposited to a thickness of 5000 mm by sputtering, for example.
[0057]
Next, as shown in FIG. 7 (9), a photoresist 43 is formed in a predetermined pattern, and the MoTa layer 42 is patterned into a gate electrode shape using this as a mask.
[0058]
Next, as shown in FIG. 8 (10), after removing the photoresist 43, for example, As type impurities such as As⁺The ion 19 is 5 × 10 at 20 kV, for example.¹⁵atoms / cm²N-type MOS transistor N is implanted by ion implantation at a dose of 10 ° C. and lamp annealed at 1000 ° C. for 10 seconds.⁺A type source region 44 and a drain region 45 are formed.
[0059]
Next, as shown in FIG. 8 (11), the entire surface is made of SiO by the CVD method.₂The film 46 is laminated to a thickness of 2000 mm, for example, and the phosphosilicate glass (PSG) film 47 is laminated to a thickness of 5000 mm, for example.
[0060]
Next, as shown in FIG. 8 (12), a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is deposited on the entire surface including each hole to a thickness of 1 μm at 150 ° C. by sputtering or the like. Then, this is patterned to form each source or drain electrode 48 (S or D) and gate extraction electrode 49 (G) of the N channel MOSFET, thereby completing each N channel MOS transistor.
[0061]
As described above, according to the present embodiment, the following significant operational effects can be obtained.
[0062]
(A) The silicon single crystal thin film 7 can be uniformly formed on the glass substrate 1 at a temperature as low as 350 to 600 ° C.
[0063]
(B) Therefore, since a silicon single crystal thin film can be formed not only on a low strain point glass substrate but also on an insulating substrate such as a ceramic substrate or an organic substrate, a substrate material having a low strain point, low cost and good physical properties can be obtained. It can be arbitrarily selected, and the substrate can be enlarged. Glass substrates and organic substrates can be made at a lower cost than quartz substrates, and can be made thinner / longer / rolled. Large-sized glass substrates and the like can be manufactured with high productivity and at low cost. When glass having a low strain point (for example, 670 ° C.) is used as the glass substrate, if the constituent elements diffuse from the glass to the upper layer and affect the transistor characteristics, the barrier layer thin film is used for the purpose of suppressing this. (For example, silicon nitride: thickness of about 10 to 1000 mm) may be formed.
[0064]
(C) The electron mobility of the silicon single crystal thin film 7 formed on the glass substrate or the like is 540 cm.²Since / v · sec, which is a large value equivalent to that of a silicon substrate, can be obtained, a transistor having a high current density can be formed at high speed. In addition to transistors, diodes, solar cells, capacitors, resistors, and the like, and electronic circuits in which these are integrated can be formed on a glass substrate. The process of forming a silicon semiconductor element such as a MOS transistor is almost the same as a conventionally known polysilicon TFT manufacturing process.
[0065]
<Third Embodiment>
FIG. 9 shows a third embodiment.
[0066]
In this embodiment, as compared with the first embodiment described above, after the step (1) in FIG. 1, as shown in (2) in FIG. 6 is formed to a thickness of, for example, 10 to 20 μm by sputtering or vacuum deposition.
[0067]
Next, as shown in FIG. 9 (3), an amorphous silicon film 5 is deposited on the indium film 6 to a thickness of several μm to 0.005 μm (for example, 0.1 μm) by a known plasma CVD method.
[0068]
In this case, the formation temperature of the silicon film should not greatly exceed the melting point of the low melting point metal 6 (melting point 156 ° C. for indium and melting point 29.77 ° C. for gallium). (600-650 ° C.) is difficult. Therefore, the amorphous silicon film 5 is formed on the indium film 6 by plasma CVD.
[0069]
Next, the substrate 1 is held at 1000 ° C. or lower (particularly 920 to 930 ° C.) for about 5 minutes in a hydrogen atmosphere. As a result, the amorphous silicon 5 is dissolved in the melt of metallic indium.
[0070]
Next, by gradually cooling, the silicon dissolved in the metal indium is epitaxially grown as shown in FIG. 9 (4) using the step 4 as a seed, and a single crystal silicon layer having a thickness of, for example, about 0.1 μm. 7 precipitates out.
[0071]
In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate in the same manner as described above, but the shape of the step is changed variously as shown in FIGS. Thus, the crystal orientation of the growth layer can be controlled.
[0072]
Thus, after depositing the single crystal silicon layer 7 on the substrate 1 by graphoepitaxy, as described above, the metal indium on the surface side is dissolved and removed with hydrochloric acid or the like, and the single crystal silicon layer 7 is patterned to form a MOS transistor. (TFT) is manufactured.
[0073]
In the present embodiment, the low melting point metal layer 6 is formed on the step 4, the amorphous silicon layer 5 is formed thereon, and then heated and melted and cooled, but the silicon from the melt of the low melting point metal is used. This epitaxial growth occurs in the same manner as in the above-described embodiment.
[0074]
<Fourth embodiment>
FIG. 10 shows a fourth embodiment.
[0075]
In the present embodiment, as compared with the first embodiment described above, after the step (1) in FIG. 1, as shown in (2) in FIG. For example, an indium film 6A containing about 1% by weight of silicon is formed to a thickness of, for example, 10 to 20 μm by sputtering or vacuum deposition.
[0076]
Next, the substrate 1 is held at 1000 ° C. or lower (particularly 920 to 930 ° C.) for about 5 minutes in a hydrogen atmosphere. As a result, the silicon is dissolved in a melt of metallic indium.
[0077]
Next, by gradually cooling, the silicon dissolved in the metal indium is epitaxially grown as shown in FIG. 10 (3) using the step 4 as a seed, and a single crystal silicon layer having a thickness of about 0.1 μm, for example. 7 precipitates out.
[0078]
In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate in the same manner as described above, but the shape of the step is changed variously as shown in FIGS. Thus, the crystal orientation of the growth layer can be controlled.
[0079]
Thus, after depositing the single crystal silicon layer 7 on the substrate 1 by graphoepitaxy, as described above, the metal indium on the surface side is dissolved and removed with hydrochloric acid or the like, and the single crystal silicon layer 7 is patterned to form a MOS transistor. (TFT) is manufactured.
[0080]
In this embodiment, after the low melting point metal layer 6A containing silicon is formed on the step 4, heat melting and cooling are performed. The epitaxial growth of silicon from the melt of the low melting point metal has already been described. It occurs in the same way as in the embodiment.
[0081]
The embodiment of the present invention described above can be variously modified based on the technical idea of the present invention.
[0082]
[Effects of the invention]
According to the method of the present invention, the silicon epitaxial layer is formed by the precipitation of single crystal silicon from the low melting point metal layer in which polysilicon or amorphous silicon is dissolved using the step formed on the insulating substrate as a seed. Polysilicon or amorphous silicon layer and low melting point metal layer can be formed at low temperature, and furthermore, since the heat treatment temperature during the above-mentioned silicon epitaxial growth may be low, a silicon single crystal film is uniformly formed on an insulating substrate at low temperature can do.
[0083]
Therefore, a glass substrate or a ceramic substrate having a relatively low strain point can be easily obtained, and a substrate having good physical properties can be used at a low cost, and the substrate can be increased in size. Mobility is 540cm²/ V · sec, which is as large as a silicon substrate, so high-speed, high-current density transistors, high-performance diodes, solar cells, capacitors, resistors, and other semiconductor elements, or these are integrated. Electronic circuits can be created on glass substrates and the like.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention in order of steps.
FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the invention in the order of steps.
FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the invention in the order of steps.
FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the invention in the order of steps.
FIG. 5 is a schematic perspective view for explaining a situation of silicon crystal growth on an amorphous substrate.
FIG. 6 is a schematic cross-sectional view showing various step shapes and silicon growth crystal orientations in the graphoepitaxy technique.
FIG. 7 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention in the order of steps.
FIG. 8 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention in the order of steps.
FIG. 9 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the third embodiment of the present invention in the order of steps.
FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the fourth embodiment of the present invention in the order of steps.
FIG. 11 is a Si—In phase diagram (A) and a Si—Ga phase diagram (B).
[Explanation of symbols]
1 ... Glass (or quartz) substrate, 4 ... Step,
5 ... polysilicon (or amorphous silicon) film, 6 ... metal indium film,
7 ... single crystal silicon layer, 8 ... gate oxide film, 10, 23 ... P-type impurity ions,
11 ... P-type impurity implantation layer, 13, 19 ... N-type impurity ions,
14 ... N-type impurity implantation layer, 15, 42 ... Gate electrode (material), 17 ... Oxide film,
20, 21, 44, 45 ... N⁺Type source or drain region,
24, 25 ... P⁺Type source or drain region,
26, 27, 28, 40, 41, 46, 47 ... insulating film,
29, 30, 48, 49 ... electrodes or wiring

Claims (14)

Forming a step in the insulating substrate;
Forming a polysilicon or amorphous silicon layer on the insulating substrate including the step to a predetermined thickness;
Wherein the lower or on the polysilicon or amorphous silicon layer even on the insulating substrate, indium, gallium, tin, bismuth, lead, zinc, antimony and a low melting point metal Do that at least one selected from the group consisting of aluminum Forming a layer;
Dissolving the polysilicon or amorphous silicon layer in the low melting point metal layer by heat treatment;
Next, a step of epitaxially growing silicon of the polysilicon or amorphous silicon layer by the cooling process using the step as a seed, and depositing a single crystal silicon layer;
Removing the low melting point metal layer remaining thereon after deposition of the single crystal silicon layer;
Thereafter, the single crystal silicon layer is subjected to a predetermined treatment, the single crystal silicon layer existing inside the step is used as a channel region, and an insulated gate field effect transistor having a source region and a drain region on both sides of the channel region. And a step of forming a layer . 2. The method for manufacturing a semiconductor device according to claim 1 , wherein the group 3 or group 5 impurity species and / or the concentration of each of the channel region, the source region, and the drain region are controlled. The step is formed by dry etching, the polysilicon or amorphous silicon layer is formed by low pressure CVD (chemical vapor deposition), plasma CVD or sputtering, and the low melting point metal layer is deposited thereon or below. It is allowed, performing the heat treatment, a method of manufacturing a semiconductor device according to claim 1. The method for manufacturing a semiconductor device according to claim 1 , wherein a glass substrate is used as the insulating substrate. When the low melting point metal layer is formed of indium, the heat treatment is performed in a hydrogen atmosphere at 850 to 1100 ° C., and when the low melting point metal layer is formed of indium gallium or gallium, the heat treatment is performed in a hydrogen atmosphere, 300 carried out at C. to 1100 ° C. or 400 to 1100 ° C., a method of manufacturing a semiconductor device according to claim 1. The method of manufacturing a semiconductor device according to claim 4 , wherein a diffusion barrier layer is formed on the glass substrate, and the polysilicon or amorphous silicon layer is formed thereon. 2. The semiconductor device according to claim 1 , wherein an impurity element of Group 3 or Group 5 is mixed during film formation of the polysilicon or amorphous silicon layer, thereby controlling an impurity species and / or concentration of the single crystal silicon layer. Manufacturing method. Forming a step in the insulating substrate;
On the insulating substrate including the step, silicon-containing vital indium, gallium, scan's, bismuth, lead, zinc, antimony and the low melting point metal layer Do that from least one member selected from the group consisting of aluminum Forming by sputtering or vacuum deposition ;
It melted the low melting point metal by the heat treatment, a step of dissolving the silicon in the melt,
Next, the step of epitaxially growing the silicon with the step as a seed by cooling treatment to deposit a single crystal silicon layer;
Removing the low melting point metal layer remaining thereon after deposition of the single crystal silicon layer;
Thereafter, the single crystal silicon layer is subjected to a predetermined treatment, the single crystal silicon layer existing inside the step is used as a channel region, and an insulated gate field effect transistor having a source region and a drain region on both sides of the channel region. And a step of forming a layer . The method for manufacturing a semiconductor device according to claim 8 , wherein the group 3 or group 5 impurity species and / or the concentration thereof are controlled in each of the channel region, the source region, and the drain region . 9. The method of manufacturing a semiconductor device according to claim 8 , wherein the step is formed by dry etching, the low melting point metal layer is deposited, and the heat treatment is performed. The method for manufacturing a semiconductor device according to claim 8 , wherein a glass substrate is used as the insulating substrate. When the low melting point metal layer is formed of indium, the heat treatment is performed in a hydrogen atmosphere at 850 to 1100 ° C., and when the low melting point metal layer is formed of indium gallium or gallium, the heat treatment is performed in a hydrogen atmosphere, 300 The manufacturing method of the semiconductor device according to claim 8 performed at -1100 ° C or 400-1100 ° C. The method for manufacturing a semiconductor device according to claim 11 , wherein a diffusion barrier layer is formed on the glass substrate, and the low melting point metal layer is formed thereon. 9. The manufacturing of a semiconductor device according to claim 8 , wherein an impurity element of Group 3 or Group 5 is mixed during film formation of the low melting point metal layer, thereby controlling an impurity species and / or concentration of the single crystal silicon layer. Method.

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