JP3979116B2 - Signal transmission system - Google Patents

Description

【００３５】
全ての結果がＮＧである場合も考えられるため、処理Ｓ４９では受信可能な結果が得られたかどうかの判定を行い、もしもＮＧの場合は受信タイミングを設定できなかったものとして、処理Ｓ５０においてエラー信号を外部に出力する。そうでない場合は、処理Ｓ４８において結果をメモリに格納し、処理Ｓ５１により受信タイミング制御部２３ｂに対して最適な受信タイミングを設定する。
以上でスレーブタイミング調整部２１の処理が終了する。
【００３６】
次に図５および図６により、送信調整シーケンスの説明を行う。図５はマスターノードについて、図６はスレーブノードについてそれぞれ示しており、両図は各図中の「Ａ」、「Ｂ」、「Ｃ」同士で接続される。
送信調整シーケンスは、処理Ｍ８０により開始され、マスタータイミング調整部２０ａが実行する処理Ｍ８１が起動される。これはＩＤ信号（＝各スレーブノードを識別するために予め設定されたＩＤ番号を、データ信号とした信号）を、並列直列変換部１０ａより全スレーブノードに送信する処理を表す。送信調整シーケンスは、個々のスレーブノードとマスターノードとの１対１の伝送により実行するため、マスターノード側からスレーブノードを１つずつ指定するために処理Ｍ８１が必要となる。
【００３７】
マスタータイミング調整部２０ａは、処理Ｍ８２により一定時間だけＩＤ信号を送信し続けた後、処理Ｍ８３によりスレーブノードから送信されるテストパターンを受信する。ここでの一定時間とは、以下で説明するスレーブタイミング調整部２１による処理Ｓ８１〜Ｓ８５の処理時間よりも十分に長い時間を表す。
続いてスレーブタイミング調整部２１の処理を説明する。以下でのスレーブタイミング調整部２１の処理は全てのスレーブノードにおいて実行する。
【００３８】
図６において処理Ｓ８０により開始され、まず処理９２により送信タイミングの初期化が行われる。処理Ｓ８１により、処理Ｍ８１により送信されたＩＤ信号を受信し、それがＩＤ信号であるか、終了通知信号であるかを判別する。終了通知信号を受信した場合は、処理Ｓ９１により処理を終了する。ＩＤ信号を受信した場合は、処理Ｓ８２により各スレーブノードのＩＤ番号との照合を行い、処理Ｓ８３において自ノードが指定されているか否かを判定する。この判定結果はレジスタ等の記憶手段により保持するものとする。
【００３９】
処理Ｓ８３の結果、ＩＤ信号によって指定されたスレーブノードは、処理Ｓ８４によりテストパターン信号をマスターノード１に対して送信する。テストパターン信号については図４の処理Ｍ４１と同様であるため、説明を省略する。またＩＤ信号によって指定されていないスレーブノードは、処理Ｓ８５により全ての論理値が“０”であるテストパターン信号を送信する。処理Ｓ８４と処理Ｓ８５は同様のタイミングで実行され、かつ各信号がシリアルバスにおいて合流される。よって、処理Ｓ８４のテストパターン信号が合流による影響を受けず、正しくマスターノード１に伝送されるように、処理Ｓ８５の信号を選ぶことが必要である。
【００４０】
次にマスタータイミング調整部２０ａの処理を説明するが、テストパターンを受信する処理Ｍ８３から処理Ｍ８６までの４つは、図４の処理Ｓ４１〜Ｓ４４と同様であるため説明を省略する。
処理Ｍ８６により、現在指定中のスレーブノードの関して全ての送信タイミングに関するテストを終了したか否かの判定を行い、未終了の場合は処理Ｍ９０によりタイミング変更指示信号をスレーブノードに送信する。ここでタイミング変更指示信号とは、スレーブノードからの送信タイミングを変更して再度テストを行う指示信号である。次に処理Ｍ９５により、一定時間だけタイミング変更指示信号を送信し続けた後に処理Ｍ８３に戻り、処理Ｍ８３〜Ｍ８６を実行する。処理Ｍ９５における一定時間とは、後述するスレーブタイミング調整部２１による処理Ｓ８６〜Ｓ８７、Ｓ８３〜Ｓ８５の処理時間よりも十分に長い時間とする。
【００４１】
一方テスト終了の場合は、処理Ｍ８７により全ての照合結果をメモリから読み出し、処理Ｍ８８により最適なタイミングを決定し、その結果を選択結果信号として処理Ｍ８９によりスレーブノードに送信する。処理Ｍ８７、Ｍ８８は図４の処理Ｓ４６、Ｓ４７と各々同様であるので説明を省略する。
続いて処理Ｍ９１において、全てのスレーブノードに関して送信タイミング調整を終えたかどうかの判定を行う。まだ終えていない場合は、処理Ｍ９２においてスレーブノードのＩＤ番号を更新し、処理Ｍ８１に戻り、次のスレーブノードの送信タイミング調整を行う。調整終了の場合は、処理Ｍ９６とＭ９７により、終了通知信号を一定時間だけスレーブノードに送信し続ける。ここで一定時間とは、スレーブタイミング調整部２１によるＳ８１の処理時間よりも十分に長い時間を示す。最後に処理Ｍ９３において最終結果とステータスを出力し、Ｍ９４により処理を終了する。
【００４２】
スレーブタイミング調整部２１は、マスタータイミング調整部２０ａによる処理Ｍ８９もしくはＭ９０により送信された信号を、処理Ｓ８６により受信する。受信信号がタイミング変更指示信号である場合、処理Ｓ８７によりデータ送信タイミングの変更を送信タイミング制御部２４ｂに対して指示し、更に処理Ｓ８３に戻る。
【００４３】
受信信号が選択結果信号である場合、処理Ｓ８８によりその結果をメモリに格納し、処理Ｓ８９により送信タイミング制御部２４ｂに対して設定する。更に処理Ｓ９０によりマスターノード１に対するテストパターンの送信を中止した後、処理Ｓ８１に戻る。
また処理Ｓ８６において上記以外の信号を受信している場合は、処理Ｓ８３に戻りテストパターン信号の送信を継続する。
【００４４】
図７は、本発明の信号伝送システムの第２実施形態を示す模式図である。
図７は、本発明の信号伝送システムの第１実施形態におけるシリアルバスの部分を、光分波器６０（６０ａ、６０ｂ）、光合波器６１（６１ａ）、電気光変換部６２（６２ａ〜６２ｆ）、光電気変換部６３（６３ａ〜６３ｈ）で置き換えた構成となっている。その他のマスターノード１、メインスレーブノード２、サブスレーブノード３（３ｃ、３ｄ）、および各部における信号は、本発明の信号伝送システムの第１実施形態と同様であるため、説明を省略する。
第２実施形態においては、各部から送信されるシリアルデータ信号およびフレーム信号は光信号に変換され、それぞれ光ファイバや後述する光バス等の光伝送媒体を介して伝送され、受信側で電気信号に変換される。
【００４５】
光分波器６０は光信号の入射ポート１つと、出射ポート３つを備えている。入射ポートからの光信号入射に対して、各出射ポートにおいて同様の光量の光信号が得られるように導光路を構成する。光分波器６０としては例えばスターカプラなどを用いることができ、また特開平１０−１２３３５０号公報や特開平１０−１２３３７４号公報に記載された光バスを用いることもできる。これらの光バスは、シート状の光伝送媒体の内部または入射端面で信号光を拡散することによって、出射端面において一様な光強度レベルの信号光を得るものである。
【００４６】
光合波器６１は光信号の入射ポート３つと、出射ポート１つを備えている。いずれの入射ポートから光信号が入射されても、出射ポートにおいて同様の光量の光信号が得られるように導光路を構成する。光合波器６１としては上述の光分波器６０と同様にスターカプラや光バスを用いることができる。
電気光変換部６２は、各ノードから出力される電気信号を光信号に変換して出力するものであり、発光ダイオード、ＬＥＤ等の発光素子とその駆動回路を含み構成される。
【００４７】
光電気変換部６３は、光分波器６０、光合波器６１から出力される光信号を電気信号に変換して各ノードに接続するものであり、フォトダイオード等の受光素子と、その出力信号の増幅回路を含み構成される。
図７においては、電気光変換部６２と光電気変換部６３が各ノードとは別ブロックとなっているが、各々を各ノード内に含める構成としてもよい。
【００４８】
【発明の効果】
以上説明したように、本発明によれば、シリアルデータ信号とフレーム信号のみを伝送するシリアルバスにより１対多のノード間通信を実現することができる。特に多ノード側から１ノード側への伝送における、送信元の切り換えの際に伝送の中断を回避できるという効果がある。またここで必要となる各ノード間の伝送タイミング調整を自動的に行うことができ、伝送路の初期化を容易に実現できる。
また１対多のノード間での通信を光信号により伝送中断なく行うことにより、ノード間の高速かつリアルタイムな制御を行うことができる。特に電気信号により通信に比べてＥＭＩの問題が緩和され、ノード間の伝送距離を長くできるメリットがある。例えば多色印刷機能を持つカラーページプリンタにおいて、各色の印刷装置とそれらを制御する装置との間での通信に適用することができる。
印刷装置においてはドラムを初めとする可動メカトロニクス部品の影響により、電気信号がＥＭＩ雑音を受けやすい問題がある。更にメカトロニクス部品のサイズが大きく、電子回路部品と共にレイアウトする際の自由度が小さいため、レイアウトを行い易くするためには装置間の伝送距離を長くできることが望ましい。本発明により、以上のような印刷装置内部の部品レイアウトや組立を容易に行うことができる。
【図面の簡単な説明】
【図１】本発明の信号伝送システムの第１実施形態を示す模式図である。
【図２】従来の信号伝送システムを示す模式図である。
【図３】本発明の信号伝送システムが実行するタイミング調整シーケンスの全体処理フロー図である。
【図４】本発明の信号伝送システムが実行するタイミング調整シーケンスに含まれる、受信調整シーケンスの処理フロー図である。
【図５】本発明の信号伝送システムが実行するタイミング調整シーケンスに含まれる、送信調整シーケンス（マスターノード）の処理フロー図である。
【図６】本発明の信号伝送システムが実行するタイミング調整シーケンスに含まれる、送信調整シーケンス（スレーブノード）の処理フロー図である。
【図７】本発明の信号伝送システムの第２実施形態を示す模式図である。
【符号の説明】
１ マスターノード
２ メインスレーブノード
３ サブスレーブノード
４ シリアルバス
１０ａ、１０ｂ、１０ｃ、１０ｄ、１０ｅ、１０ｆ、１０ｇ 並列直列変換部
１１ａ、１１ｂ、１１ｃ、１１ｄ、１１ｈ 直列並列変換部
１２ａ、１２ｂ、１２ｃ、１２ｄ、１２ｅ、１２ｆ、１２ｇ 送信ＰＬＬ
１３ａ、１３ｂ、１３ｃ、１３ｄ、１３ｈ 受信ＰＬＬ
２０ａ マスタータイミング調整部
２１ｂ、２２ｃ、２２ｄ スレーブタイミング調整部
６０ａ、６０ｂ 光分波器
６１ａ 光合波器
６２ａ、６２ｂ、６２ｃ、６２ｄ、６２ｅ、６２ｆ、６２ｇ、６２ｈ 光電気変換部
６３ａ、６３ｂ、６３ｃ、６３ｄ、６３ｅ、６３ｆ 電気光変換部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal transmission system that transmits and receives signals between one-to-many nodes using an optical multiplexer / demultiplexer that is responsible for propagation of signal light.
[0002]
[Prior art]
In recent years, with the improvement of semiconductor integration technology, the data processing speed of LSI has been dramatically increased. Along with this, an improvement in signal transmission capability is required for a wiring board on which a semiconductor integrated circuit is mounted. In particular, recently, a so-called parallel processing architecture including a plurality of high-speed CPU chips has been adopted in a personal computer as well, in a server type system corresponding to a higher model. The parallel processing architecture technology is described in, for example, “Hideharu Amano, Parallel Computer, Shosodo, pp. 6-13”. According to this, when configuring a system including a plurality of modules that perform data processing such as a CPU, the coupling method between modules is classified into a bus coupling type, a switch coupling type, and a coupling network type. Of these, the bus coupling type is not suitable for coupling a large number of modules, but has advantages such as a simple structure, a small amount of hardware, and excellent extensibility compared to other modules. It is widely used in commercial computers such as personal computers and computer application products such as page printers.
[0003]
The mounting of the inter-module coupling part of the parallel processing system requires a large number of connection connectors and wirings, so that the communication capacity and wiring density have been improved by multilayering and miniaturization of the wirings. However, the limit is being reached due to signal delay and transmission waveform distortion caused by inter-wiring capacitance and connection wiring resistance. In addition, electromagnetic noise (EMI: Electromagnetic Interference) becomes a serious problem due to an increase in operating speed.
[0004]
As described above, the processing capability of the data processing apparatus is often limited by the transmission capability of the wiring board bus. In order to overcome the limitations of electric buses, the use of an in-system optical connection technology called optical interconnection has been studied. The outline of the optical interconnection technology is as follows. .33, pp. 81-86, 1994 ”,“ Osamu Wada, April 1993 Electronics, pp. 52-55 ”, various forms have been proposed depending on the contents of the system configuration. . According to this technology, it is possible to reduce electromagnetic noise while being able to operate at a higher frequency than electric, eliminating the need for physical connection of bus signal lines, and transmission bandwidth by multiplexing using wavelength, strength, etc. Can be expanded, and simultaneous bi-directional communication is possible.
[0005]
In particular, the spatial light transmission technology is different from the transmission technology using optical fibers, and enables simultaneous communication between multiple ports, so that it is compatible with the above-described bus-coupled parallel processing architecture. A related technique is described in JP-A-10-123350. This technology realizes optical communication between ports installed on the end face of a flat light guide, and diffuses incident signal light and transmits it to the opposite end face to realize broadcast communication. By using multiple transmissions, multiple independent broadcast communications are performed simultaneously.
[0006]
As a signal transmission system technology that applies such spatial light transmission, in order to alleviate the problem of transmission skew between signals and reduce the number of transmission lines, a plurality of electric signal lines are converted in parallel and serially. A system has been proposed in which a serial signal is converted into an optical signal and transmitted via a spatial light transmission medium. In particular, here, only a data signal and a frame signal are transmitted from the transmission node to the reception node, and a clock signal is not transmitted. The frame signal represents the transmission frequency of the electric signal line, and the clock signal represents the transmission frequency of the serial signal obtained after parallel-serial conversion. The clock signal is necessary for latching the serial signal at the receiving node. Here, the frequency is multiplied from the received frame signal by means such as a PLL (Phase Locked Loop) circuit to automatically generate the clock signal. As a result, it is not necessary to transmit a clock signal having a high frequency particularly in optical transmission, and a transmission band necessary for optical parts and circuit parts constituting the transmission path can be narrowed, and a transmission system can be easily realized.
[0007]
[Problems to be solved by the invention]
As an example of the prior art, FIG. 2 shows a configuration in which one master node 100 and three slave nodes 210, 220, and 230 are connected by a transmission path that transmits only a data signal and a frame signal. For simplicity, only the transmission path from the slave node to the master node is shown here. Each of the slave nodes 210, 220, and 230 includes parallel-serial converters 10e, 10f, and 10g included in a serial data signal transmitter, and transmission PLLs 12e, 12f, and 12g. The master node 100 is a serial-parallel converter included in a receiver. The unit 11h and the reception PLL 13h only. The serial data signals output from the parallel / serial converters 10e, 10f, and 10g are merged on the serial bus 400 and input to the serial / parallel converter 11h. Similarly, frame signals are combined and input to the reception PLL 13h.
[0008]
Here, when the transmission from the slave node # 1 to the master node is completed and the transmission from the slave node # 2 to the same master node is started immediately, the serial data signal input to the serial / parallel converter 11h of the master node The frame signals input to the reception PLL 13h are switched together. At this time, since the reception PLL 13h requires time (usually on the order of milliseconds) to stabilize due to a change in the input signal, serial data cannot be transmitted during that time and is interrupted.
[0009]
If the system has sufficient time from when the node is switched to when data transfer is started, the above interruption is not a problem. However, in a system that needs to shorten the memory access time as much as possible, for example, data transfer between the CPU and the cache memory, such interruption is a problem because the performance of the entire system is greatly deteriorated.
[0010]
In view of the above circumstances, an object of the present invention is to provide a signal transmission system capable of performing high-speed transmission between one-to-many nodes connected by a serial transmission path.
[0011]
[Means for Solving the Problems]
The above object is a signal transmission system for transferring data between one master node and a slave node group composed of a plurality of slave nodes, wherein the slave node group includes one main slave node and one slave node group. The main slave node includes means for generating and transmitting a slave synchronization signal used for synchronous transmission of a slave data signal transmitted from the slave node group to the master node. This is achieved by a signal transmission system in which a slave node and the master node transmit and receive the slave data signal in synchronization with the slave synchronization signal.
[0012]
Here, the master node executes a transmission adjustment sequence for individually setting a transmission timing between the slave data signal and the slave synchronization signal in each slave node during a period when data transfer is not performed. An adjustment unit, wherein the slave node instructs the transmission timing control unit to change the transmission timing of the slave data signal and the transmission timing control unit according to a command from the master timing adjustment unit. And a slave timing adjustment unit that adjusts the transmission timing.
[0013]
The signal transmission system according to the present invention is a signal transmission system for transferring data between one master node and a slave node group composed of a plurality of slave nodes, wherein the master node is the master node. Means for generating and transmitting a master synchronization signal used for synchronous transmission of a master data signal to be transmitted to the slave node group, wherein the slave node group includes one main slave node and one or more sub-slave nodes. The main slave node includes means for generating and transmitting a slave synchronization signal used for synchronous transmission of a slave data signal transmitted from the slave node group to the master node, and the master node and each slave node And the master data in synchronization with the master sync signal. Send and receive data signals, in synchronization with the slave synchronization signal and performs transmission and reception of the slave data signal.
[0014]
Here, the master node sets a reception adjustment sequence for individually setting the transmission timing between the master data signal and the master synchronization signal in each slave node during a period when data transfer is not performed, and the slave data A master timing adjustment unit that executes a transmission adjustment sequence for individually setting the transmission timing between the signal and the slave synchronization signal in each slave node, and the slave node changes the reception timing of the master data signal. A reception timing control unit, a transmission timing control unit that changes the transmission timing of the slave data signal, and a reception timing for the reception timing control unit during execution of the reception adjustment sequence according to a command from the master timing adjustment unit Instruct the receiver to change Adjusts the timing during execution of the transmission adjustment sequence can include at a slave timing adjusting unit for adjusting the transmission timing instructed the change in the transmission timing to the transmission timing control unit.
[0015]
The master synchronization signal and the slave synchronization signal can be generated from the same oscillation source. Furthermore, at least one of the master data signal, the slave data signal, the master synchronization signal, and the slave synchronization signal can be transmitted through an optical transmission medium.
With this configuration, it is possible to obtain a signal transmission system capable of performing high-speed transmission between one-to-many nodes connected by a serial transmission path.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described. In the following description, the master data signal is a serial data signal output from the master node, the slave data signal is output from the slave node, the master synchronization signal is output from the master node, and the slave synchronization The signal is described as a frame signal output from the slave node.
[0017]
FIG. 1 is a schematic diagram showing a first embodiment of a signal transmission system of the present invention.
In FIG. 1, a parallel / serial conversion unit 10 a, a transmission PLL 12 a, a serial / parallel conversion unit 11 a, a reception PLL 13 a, and a master timing adjustment unit 20 a are all included in the master node 1. For example, a CPU board is connected to the master node 1 via a transmission data signal 100a, a transmission frame signal 102a, a reception data signal 101a, a reception frame signal 103a, a timing adjustment activation signal 110a, and a busy signal 111a. The master node 1 exchanges signals 200a, 201a, 202a, and 203a with the main slave node 2 and the sub slave nodes 3c and 3d through the serial bus 4.
[0018]
The master timing adjustment unit 20a activates the timing adjustment sequence if the timing adjustment activation signal 110a is valid, but directly connects the input / output signals 100a to 103a to the outside if invalid. The timing adjustment sequence will be described later.
The transmission PLL 12a receives the frame signal output from the master timing adjustment unit 20a, and outputs a clock signal having a multiplication frequency given in advance.
[0019]
The parallel-serial conversion unit 10a performs speed conversion of the parallel data signal and outputs a serial data signal. For example, when 16 parallel data signals each having a transmission rate of 20 Mbps, a 20 MHz frame signal, and a 160 MHz clock signal output from the transmission PLL 12a (= 8 times the frame signal) are given as input signals, the parallel-serial converter 10a Output signals are two serial data signals of 160 Mbps.
The above corresponds to the transmitter in the master node 1.
[0020]
Next, the reception PLL 13a inputs a frame signal from the serial bus, and performs the same operation as the transmission PLL 12a.
The serial / parallel converter 11a converts the speed of the serial data signal and outputs a parallel data signal. For example, when two serial data signals each having a transmission speed of 160 Mbps, a 20 MHz frame signal, and a 160 MHz clock signal output from the reception PLL 13a are given as input signals, the output signal of the serial / parallel converter 11a is 20 Mbps parallel data. There are 16 signals.
The above corresponds to the receiver in the master node 1.
[0021]
In FIG. 1, the main slave node 2 includes a parallel / serial conversion unit 10b, a transmission PLL 12b, a serial / parallel conversion unit 11b, a reception PLL 13b, a slave timing adjustment unit 21b, a reception timing control unit 23b, and a transmission timing control unit 24b. It has a configuration. The sub slave nodes 3 (3c, 3d) have the same configuration. The difference between the two is that the main slave node 2 outputs the frame signal output from the transmission timing control unit 24b to the serial bus, while the sub slave node 3 does not output to the serial bus. . The main slave node 2 and the sub slave nodes 3c and 3d have transmission data signals 100b, 100c and 100d, transmission frame signals 102b, 102c and 102d, reception data signals 101b, 101c and 101d, and reception frame signals 103b, 103c and 103d, respectively. For example, a memory board is connected via the timing adjustment activation signals 110b, 110c, and 110d. The main slave node 2 and the sub slave nodes 3c and 3d exchange signals 200b, 201b, 202b, 203b, 200c, 201c, 203c, 200d, 201d, and 203d with the master node 1 through the serial bus 4, respectively. To do.
[0022]
The parallel / serial converters 10b, 10c, and 10d, the transmission PLLs 12b, 12c, and 12d, the serial / parallel converters 11b, 11c, and 11d, and the reception PLLs 13b, 13c, and 13d are all the same as the modules included in the master node 1. Description is omitted.
The slave timing adjustment unit 21b activates the timing adjustment sequence if the timing adjustment activation signal 110b is valid, but directly connects the input / output signals 100b to 103b to the outside if invalid. The timing adjustment sequence will be described later.
[0023]
The reception timing control unit 23b outputs a result obtained by delaying the serial data signal input from the serial bus according to the instruction signal from the slave timing adjustment unit 21b. Here, for example, a device having a variable delay time such as a programmable delay line can be used.
If the reception timing control unit 23b is provided for each bit of the serial data signal, the reception timing control unit 23b can adjust the skew including the data. However, in this case, since there is a problem that the number of parts increases, a method of adjusting by providing one reception timing control unit 23b for each of a plurality of bits can be used.
This is a method of changing the transmission timing of serial data to match the frame signal, but conversely, a method of changing the timing of the frame signal by the reception timing control unit 23b to match the serial data signal can also be used. In this case, in addition to the programmable delay line, for example, a method of changing the timing of the frame signal and the clock signal using a PLL whose phase can be adjusted as the reception PLL 13b can be used.
[0024]
The transmission timing control unit 24b outputs the result of delaying the serial data signal output to the serial bus according to the instruction signal from the slave timing adjustment unit 21b.
Similarly to the reception timing control unit 23b, if one transmission timing control unit 24b is provided for each bit of the serial data signal, it is possible to adjust the skew including the data. However, in this case, since there is a problem that the number of components increases, a method of adjusting by providing one transmission timing control unit 24b for each of a plurality of bits can also be used.
Similarly to the reception timing control unit 23b, the timing of the serial data signal line or the frame signal line is changed by a programmable delay line, or the timing of the frame signal and the clock signal is changed by a PLL whose phase can be adjusted as the transmission PLL 12b. It is also possible to use a method.
[0025]
Similarly to the slave timing adjustment unit 21b, the slave timing adjustment units 22c and 22d also exchange signals with the reception timing control units 23c and 23d and the transmission timing control units 24c and 24d, respectively.
The frame signals output from the master node and the slave node can be generated from the same oscillation source. For example, this is realized by providing an oscillation source on the master node side, transmitting the generated frame signal to the slave node, and connecting the reception frame signal 103 and the transmission frame signal 102 on the slave node side.
[0026]
Next, the timing adjustment sequence will be described with reference to FIGS. Both of these are executed by the master timing adjustment unit 20a and the slave timing adjustment unit 21.
[0027]
FIG. 3 shows a flowchart of the entire sequence.
When the timing adjustment activation signal 110 is detected by the process 31 and started by the process 30, the busy signal 111 (111a, 111c, 111d) is activated by the process 32, and the busy state is notified to the outside. Thereby, input / output of the data signals 100 and 101 is prohibited during the timing adjustment processing.
First, a reception adjustment sequence is executed as process 33, and then a transmission adjustment sequence is executed as process 34. When these are finished, the busy state for the outside is canceled by processing 35, and the whole is finished by processing 36.
[0028]
FIG. 4 shows a flowchart of the reception adjustment sequence. In FIG. 4 to FIG. 6, each processing block name starting with M represents processing performed by the master timing adjustment unit 20 a, and one starting with S represents processing performed by the slave timing adjustment unit 21. A thick arrow represents signal exchange between the master node 1 and the slave node.
The reception adjustment sequence is started by a process M40, and a process M41 executed by the master timing adjustment unit 20a is activated. This represents processing for transmitting the test pattern signal from the parallel-serial converter 10a to all slave nodes. This test pattern is preliminarily stored in a storage unit such as a memory in both the master timing adjustment unit 20a and the slave timing adjustment unit 21.
[0029]
As the test pattern, for example, in the case of a 10-bit signal, the following repetitive pattern can be used.
Bit string “0001110101”
Bit string 2. “0011010101”
The conditions necessary for the test pattern depend on the specifications of the transmission path, but for example, the following is necessary.
Condition 1. The logical value “1” occupies 40% to 60% in the bit string.
Condition 2. It is possible to determine from the pattern itself which is the first bit.
Both bit strings 1 and 2 satisfy conditions 1 and 2.
[0030]
Next, the master timing adjustment unit 20a continues to transmit the test pattern signal for a predetermined time in the process M42, and then ends the process in the process M43. The fixed time here represents a time sufficiently longer than the processing times of the processes S41 to S52 of the slave timing adjustment unit 21 described below.
Next, processing of the slave timing adjustment unit 21 will be described. The following is executed on all slave nodes.
In step S40, the test pattern signal transmitted in step M41 is received. At this time, the slave timing adjustment unit 21 needs to set an initial value of the reception timing to the reception timing control unit 23b in advance.
[0031]
In step S42, the received test pattern is collated with the correct answer pattern stored in advance, and in step S43, the collation result is stored in the memory. Here, for example, when the above bit string 1 is a correct pattern, the received test pattern is:
2. Bit string “10000111010”
Suppose that In this case, each bit is received correctly, but the position of the first bit is only shifted to the lower side by 1 bit, and a correct answer is obtained if word alignment is performed. Therefore, the following two are stored as the collation results.
Result 1. Whether all individual bits are received correctly.
Result 2. If the result 1 is OK, how many bits should be shifted to get the correct answer?
[0032]
In process S44, it is determined whether or not all the reception timing tests have been completed. If not completed, the reception timing is changed in step S45, and the process returns to step S41. Here, the reception timing is changed by the reception timing control unit 23b according to an instruction from the slave timing adjustment unit 21.
When the test is completed, all the collation results are read from the memory at step S46, and the optimum reception timing is determined at step S47. Table 1 below shows an example of a collation result based on eight reception timings that are continuously changed as an example. Here, among reception timings 3 to 7 where “Result 1” is OK, intermediate reception timing 5 is determined as the optimum reception timing.
[0033]
As a determination method, for example, a look-up table in which 8 bits representing “result 1” are used as addresses and optimum reception timing for each address is stored in advance can be used. In the example of Table 1, if OK is a value “1”, NG is a value “0”, “Result 1” at reception timing 8 is MSB, and “Result 1” at reception timing 1 is LSB, address “01111100”, that is, 124 addresses In addition, a value indicating the reception timing 5 is stored.
[0034]
[Table 1]

[0035]
Since all the results may be NG, it is determined whether or not a receivable result has been obtained in process S49. If NG, it is determined that the reception timing could not be set, and an error signal is received in process S50. Is output to the outside. Otherwise, the result is stored in the memory in step S48, and the optimum reception timing is set for the reception timing control unit 23b in step S51.
This completes the processing of the slave timing adjustment unit 21.
[0036]
Next, the transmission adjustment sequence will be described with reference to FIGS. FIG. 5 shows the master node, and FIG. 6 shows the slave node. Both figures are connected by “A”, “B”, and “C” in each figure.
The transmission adjustment sequence is started by the process M80, and the process M81 executed by the master timing adjustment unit 20a is activated. This represents a process of transmitting an ID signal (= a signal in which an ID number set in advance for identifying each slave node is used as a data signal) to all slave nodes from the parallel-serial converter 10a. Since the transmission adjustment sequence is executed by one-to-one transmission between each slave node and the master node, the process M81 is required to designate the slave nodes one by one from the master node side.
[0037]
The master timing adjustment unit 20a receives the test pattern transmitted from the slave node by the process M83 after continuing to transmit the ID signal for a predetermined time by the process M82. Here, the fixed time represents a time sufficiently longer than the processing times of processing S81 to S85 by the slave timing adjustment unit 21 described below.
Next, processing of the slave timing adjustment unit 21 will be described. The processing of the slave timing adjustment unit 21 below is executed in all slave nodes.
[0038]
In FIG. 6, the process starts from step S <b> 80, and first, transmission timing is initialized by step 92. In step S81, the ID signal transmitted in step M81 is received, and it is determined whether it is an ID signal or an end notification signal. If an end notification signal is received, the process ends at step S91. When the ID signal is received, the ID number of each slave node is checked in step S82, and it is determined in step S83 whether or not the own node is designated. This determination result is held by storage means such as a register.
[0039]
As a result of the process S83, the slave node specified by the ID signal transmits a test pattern signal to the master node 1 by the process S84. The test pattern signal is the same as the process M41 in FIG. In addition, the slave node not designated by the ID signal transmits a test pattern signal whose logical values are all “0” in step S85. Process S84 and process S85 are executed at the same timing, and the signals are joined on the serial bus. Therefore, it is necessary to select the signal of the process S85 so that the test pattern signal of the process S84 is not affected by the merge and is correctly transmitted to the master node 1.
[0040]
Next, the process of the master timing adjustment unit 20a will be described. Since the four processes from the process M83 to the process M86 that receive the test pattern are the same as the processes S41 to S44 in FIG.
In process M86, it is determined whether or not all transmission timing tests have been completed for the currently designated slave node, and if not completed, a timing change instruction signal is transmitted to the slave node in process M90. Here, the timing change instruction signal is an instruction signal for changing the transmission timing from the slave node and performing the test again. Next, the process M95 continues to transmit the timing change instruction signal for a predetermined time, and then returns to the process M83 to execute the processes M83 to M86. The fixed time in the process M95 is a time sufficiently longer than the process times of processes S86 to S87 and S83 to S85 performed by the slave timing adjustment unit 21 described later.
[0041]
On the other hand, when the test is completed, all matching results are read from the memory by the process M87, the optimum timing is determined by the process M88, and the result is transmitted as a selection result signal to the slave node by the process M89. The processes M87 and M88 are the same as the processes S46 and S47 in FIG.
Subsequently, in process M91, it is determined whether or not the transmission timing adjustment has been completed for all slave nodes. If not completed yet, the slave node ID number is updated in process M92, and the process returns to process M81 to adjust the transmission timing of the next slave node. In the case of the end of the adjustment, the end notification signal is continuously transmitted to the slave node for a predetermined time by the processes M96 and M97. Here, the fixed time indicates a time sufficiently longer than the processing time of S81 by the slave timing adjustment unit 21. Finally, the final result and status are output in process M93, and the process ends in M94.
[0042]
The slave timing adjustment unit 21 receives the signal transmitted by the process M89 or M90 by the master timing adjustment unit 20a through the process S86. If the received signal is a timing change instruction signal, the transmission timing control unit 24b is instructed to change the data transmission timing in step S87, and the process returns to step S83.
[0043]
If the received signal is a selection result signal, the result is stored in the memory in step S88, and set in the transmission timing control unit 24b in step S89. Furthermore, after stopping the transmission of the test pattern to the master node 1 by the process S90, the process returns to the process S81.
If a signal other than the above is received in process S86, the process returns to process S83 and the transmission of the test pattern signal is continued.
[0044]
FIG. 7 is a schematic diagram showing a second embodiment of the signal transmission system of the present invention.
FIG. 7 shows a serial bus portion in the first embodiment of the signal transmission system of the present invention, which includes an optical demultiplexer 60 (60a, 60b), an optical multiplexer 61 (61a), and an electro-optical converter 62 (62a to 62f). ), And the photoelectric conversion unit 63 (63a to 63h). Other master node 1, main slave node 2, sub-slave node 3 (3c, 3d), and signals in each part are the same as those in the first embodiment of the signal transmission system of the present invention, and thus description thereof is omitted.
In the second embodiment, the serial data signal and the frame signal transmitted from each unit are converted into optical signals, respectively transmitted through an optical transmission medium such as an optical fiber or an optical bus described later, and converted into an electrical signal on the receiving side. Converted.
[0045]
The optical demultiplexer 60 includes one optical signal incident port and three output ports. The light guide is configured so that an optical signal having the same amount of light can be obtained at each exit port when an optical signal enters from the entrance port. As the optical demultiplexer 60, for example, a star coupler or the like can be used, and an optical bus described in JP-A-10-123350 or JP-A-10-123374 can also be used. These optical buses obtain signal light having a uniform light intensity level at the exit end face by diffusing the signal light inside the sheet-like optical transmission medium or at the entrance end face.
[0046]
The optical multiplexer 61 includes three optical signal incident ports and one outgoing port. The light guide is configured so that an optical signal having a similar light quantity can be obtained at the exit port regardless of which optical signal is incident from any of the entrance ports. As the optical multiplexer 61, a star coupler or an optical bus can be used as in the optical demultiplexer 60 described above.
The electro-optical conversion unit 62 converts an electrical signal output from each node into an optical signal and outputs the optical signal, and includes a light-emitting element such as a light-emitting diode or an LED and a drive circuit thereof.
[0047]
The photoelectric conversion unit 63 converts the optical signal output from the optical demultiplexer 60 and the optical multiplexer 61 into an electrical signal and connects it to each node. The light receiving element such as a photodiode and its output signal The amplifier circuit is configured.
In FIG. 7, the electro-optic conversion unit 62 and the opto-electric conversion unit 63 are separate blocks from each node, but each may be included in each node.
[0048]
【The invention's effect】
As described above, according to the present invention, one-to-many communication between nodes can be realized by a serial bus that transmits only serial data signals and frame signals. In particular, there is an effect that interruption of transmission can be avoided at the time of switching the transmission source in transmission from the multi-node side to the one-node side. Also, transmission timing adjustment between the nodes required here can be automatically performed, and the initialization of the transmission path can be easily realized.
In addition, by performing communication between one-to-many nodes using optical signals without interruption of transmission, high-speed and real-time control between nodes can be performed. In particular, the problem of EMI is mitigated by electrical signals compared to communication, and there is an advantage that the transmission distance between nodes can be increased. For example, in a color page printer having a multi-color printing function, the present invention can be applied to communication between a printing device for each color and a device that controls them.
In a printing apparatus, there is a problem that an electric signal is easily subjected to EMI noise due to the influence of movable mechatronic parts such as a drum. Furthermore, since the size of the mechatronic component is large and the degree of freedom when laying out together with the electronic circuit component is small, it is desirable that the transmission distance between the devices can be increased in order to facilitate layout. According to the present invention, it is possible to easily perform component layout and assembly inside the printing apparatus as described above.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a first embodiment of a signal transmission system of the present invention.
FIG. 2 is a schematic diagram showing a conventional signal transmission system.
FIG. 3 is an overall process flow diagram of a timing adjustment sequence executed by the signal transmission system of the present invention.
FIG. 4 is a processing flow diagram of a reception adjustment sequence included in a timing adjustment sequence executed by the signal transmission system of the present invention.
FIG. 5 is a processing flow diagram of a transmission adjustment sequence (master node) included in a timing adjustment sequence executed by the signal transmission system of the present invention.
FIG. 6 is a processing flow diagram of a transmission adjustment sequence (slave node) included in a timing adjustment sequence executed by the signal transmission system of the present invention.
FIG. 7 is a schematic diagram showing a second embodiment of the signal transmission system of the present invention.
[Explanation of symbols]
1 Master node
2 Main slave node
3 Sub-slave node
4 Serial bus
10a, 10b, 10c, 10d, 10e, 10f, 10g Parallel to serial converter
11a, 11b, 11c, 11d, 11h Serial-to-parallel converter
12a, 12b, 12c, 12d, 12e, 12f, 12g Transmission PLL
13a, 13b, 13c, 13d, 13h Reception PLL
20a Master timing adjustment unit
21b, 22c, 22d Slave timing adjustment unit
60a, 60b optical demultiplexer
61a Optical multiplexer
62a, 62b, 62c, 62d, 62e, 62f, 62g, 62h Photoelectric converter
63a, 63b, 63c, 63d, 63e, 63f Electro-optical converter

Claims (5)

A signal transmission system for transferring data between one master node and a slave node group composed of a plurality of slave nodes, the slave node group comprising one main slave node and one or more sub-slaves And the main slave node includes means for generating and transmitting a slave synchronization signal used for synchronous transmission of a slave data signal transmitted from the slave node group to the master node, and the master node includes data A master timing adjustment unit that executes a transmission adjustment sequence for individually setting the transmission timing between the slave data signal and the slave synchronization signal in each slave node during a period in which the transfer is not performed; , Change the transmission timing of the slave data signal Wherein a transmission timing control unit, wherein and a slave timing adjusting unit for adjusting the indicated transmission timing of the change in transmission timing to the transmission timing control unit in accordance with instructions from the master timing adjustment unit, and the respective slave node A signal transmission system, wherein a master node transmits and receives the slave data signal in synchronization with the slave synchronization signal. A signal transmission system for transferring data between one master node and a slave node group composed of a plurality of slave nodes, wherein the master node transmits from the master node to the slave node group Means for generating and transmitting a master synchronization signal used for synchronous transmission of a master data signal, wherein the slave node group comprises one main slave node and one or more sub-slave nodes; Means for generating and transmitting a slave synchronization signal used for synchronous transmission of a slave data signal transmitted from the slave node group to the master node, wherein the master node is configured to transmit the master data during a period when data transfer is not being performed. Transmission timing between the signal and the master synchronization signal A master timing adjustment unit that individually executes a reception adjustment sequence that is individually set in a slave node and a transmission adjustment sequence that individually sets the transmission timing between the slave data signal and the slave synchronization signal in each slave node; The slave node includes a reception timing control unit that changes a reception timing of the master data signal, a transmission timing control unit that changes a transmission timing of the slave data signal, and the reception adjustment sequence according to a command from the master timing adjustment unit During the execution of the transmission timing, the reception timing control unit is instructed to change the reception timing to adjust the reception timing. During the execution of the transmission adjustment sequence, the transmission timing control unit is instructed to change the transmission timing. To adjust the transmission timing. And a slave timing adjustment unit that performs, the master node and each slave node, in synchronism with the master synchronizing signal to transmit and receive the master data signal, the slave data signal in synchronization with the slave synchronization signals Transmission / reception system for transmitting and receiving signals. The signal transmission system according to claim 2 , wherein the master synchronization signal and the slave synchronization signal are generated from the same oscillation source. The signal transmission system according to claim 2 or 3 , wherein at least one of the master data signal and the slave data signal is transmitted via an optical transmission medium. The signal transmission system according to claim 2 , wherein at least one of the master synchronization signal and the slave synchronization signal is transmitted via an optical transmission medium.

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