JP3979498B2 - Driving circuit and driving method for liquid crystal display - Google Patents

Description

  The present invention relates to a driving circuit and a driving method for a liquid crystal display, and more particularly to a driving circuit and a driving method for a liquid crystal display having a look-up table (LUT).

  Liquid crystal displays are widely used in portable electronic products such as notebook computers and personal digital assistants (PDAs) due to their advantages such as light weight, low power consumption and low radiation. On the other hand, liquid crystal monitors and liquid crystal televisions are also replacing conventional cathode ray tube monitors and televisions. However, liquid crystal displays also have their own drawbacks. For example, every time the image changes, the alignment method of the liquid crystal molecules must be changed, causing a delay in the screen. In order to improve this problem, it is required to improve the reaction rate of the liquid crystal.

Please refer to FIG. FIG. 1 is a timing diagram of pixel voltage and light transmittance V1 in a conventional liquid crystal display. Among them, the pixel voltage is indicated by a solid line, and the light transmittance V1 is indicated by a broken line. When the pixel of the liquid crystal display is switched from the data voltage C1 to the data voltage C2, a delay time occurs at the time of charging due to the characteristics of the liquid crystal molecules, so the liquid crystal molecules cannot be deflected to a predetermined angle within one frame period, so that the expected light transmittance is achieved. Can't reach. According to FIG. 1, frame N represents the length of one frame period, and frames N + 1, N + 2,... Represent the next frame period after frame N. As shown by the light transmittance V1 curve in FIG. 1, the light transmittance V1 cannot reach the predetermined transmittance within the period of the frame N, but reaches the predetermined transmittance at the period of the frame N + 2. Such a delay causes screen delays.

In order to improve this problem, an overdrive driving method is applied to a liquid crystal display. Please refer to FIG. FIG. 2 is a timing diagram of pixel voltage and light transmittance V2 in a conventional liquid crystal display using the overdrive driving method. When switching the pixel of the liquid crystal display from the data voltage C1 to the data voltage C2, the reaction of the liquid crystal molecules is accelerated by applying the overdrive data voltage C3. According to FIG. 2, when the data voltage C1 is switched to the data voltage C2, the overdrive data voltage C3 higher than the data voltage C2 is applied to accelerate the reaction of the liquid crystal molecules so that the liquid crystal molecules are scheduled within one frame period. It can be deflected at an angle to reach the expected light transmittance. According to FIG. 2, the light transmittance V <b> 2 reaches a predetermined transmittance within the period of the frame N.

In the conventional overdrive driving method, for example, US Patent Publication No. US2002 / 0050965, a liquid crystal display is overdriven with a simple parameter table for storing video data. The simple parameter table contains only some data needed to switch each grayscale value to another grayscale value. Therefore, when receiving video data from the system end, a processor that performs operations such as interpolation and expands the values in the parameter table is necessary. Therefore, the conventional overdrive driving method requires extra computations, resulting in a decrease in the performance of the liquid crystal display.
United States Patent Publication US2002 / 0050965

  In order to solve the above-described problems, an object of the present invention is to provide a driving circuit and a driving method for a liquid crystal display having a reference table device.

The present invention provides a method of driving a liquid crystal display. The liquid crystal display includes a liquid crystal panel. The liquid crystal panel includes a plurality of scan lines, a plurality of data lines, switch elements connected to the corresponding scan lines and the corresponding data lines, and switch elements connected to the corresponding scan lines and the corresponding data lines. A plurality of pixels. In this method, (a) a scan voltage is continuously applied to the scan line, (b) M-bit video data is received from the video signal end, and (c) the N most significant bits from the M-bit video data To generate N-bit video data, of which N is less than M, (d) N-bit video data is delayed by one frame period to generate delayed N-bit video data, and (e) current A comparison result value is determined by comparing the most significant bit of the P bit in the M bit video data with the delayed N bit video data. (F) If the comparison result value is a first value, the most significant bit of the P bit The first video data value is selected from the parameter table according to the bit and the delayed N-bit video data, and the first data line voltage is generated according to the first video data value, and the corresponding data line It applied to include steps such as applying to (g) comparison if the result value is the second number, the data line corresponding to produce a second data line voltage by the current M-bit video data.

The parameter table according to the present invention is created by measuring an overdrive voltage required to reach a predetermined data voltage within one frame period, and each grayscale value is converted to another grayscale value. Includes video data. Therefore, according to the present invention, at the time of overdrive, the necessary overdrive video data can be obtained only by collating the parameter table without developing the parameter table by the processor as in the prior art. The driving circuit and driving method according to the present invention takes in the most significant bit or the least significant bit in consideration of the data length of the video memory, and therefore a 16-bit memory is applied to the video memory.
In order to elaborate on the features of such an apparatus and method, specific examples are given and described below with reference to the figures.

  In order to describe the present invention in detail, the operation of the liquid crystal display will be described first. Please refer to FIG. FIG. 3 is a circuit diagram of the liquid crystal display. According to FIG. 3, the liquid crystal display 30 includes a liquid crystal panel 31, and the liquid crystal panel 31 includes a plurality of scan lines 32, a plurality of data lines 34, and a plurality of pixels 36. Each pixel 36 is connected to a corresponding scan line 32 and data line 34, respectively, and further includes a switch device 38 and a pixel electrode 39, respectively. Among them, the switch device 38 is connected to the corresponding scan line 32 and data line 34. In order to drive the liquid crystal display 30, the scan voltage is applied to the scan line 32 to turn on the switch device 38, and then the data line voltage is written to the pixel electrode 39 via the data line 34 via the switch device 38. Thus, when a switch voltage is applied to the scan line 32 and the switch device 38 is turned on, the data voltage on the data line 34 charges the pixel electrode 39 through the switch device 38 and deflects the liquid crystal molecules. When the scan voltage on the scan line is erased, the switch device 38 is turned off, the electrical connection between the data line 34 and the pixel 36 is disconnected, and the pixel electrode 39 remains charged. By controlling the opening and closing of the switch device 38 by the scan line 32, the charging of the pixel electrode 39 by the data line 34 is controlled. The deflection angle of the liquid crystal molecules in the pixel 36 differs depending on the data line voltage in the scan line 32, and various screens are displayed by exhibiting various transmittances.

Please refer to FIG. FIG. 4 is an explanatory diagram showing the drive circuit 40 according to the first embodiment of the present invention. The drive circuit 40 drives the liquid crystal display 30 in FIG. 3, and the video signal terminal 41, the bit processor 42, the video memory 43, the comparison circuit 44, the reference table device 45, the multiplexer 46, and the data line drive. A circuit 47, a memory 48, a parameter table selector 49, and a temperature sensor 51 are included. In this embodiment, the video memory 43 is a memory having a data length of 16 bits (5, 6, 5 or 5, 5, 5) and includes an associated circuit for controlling data access. Controls storage and retrieval of files. The video signal end 41 transmits three sets of 8-bit red, green and blue (RGB) video data to the bit processor 42. In each set of video data, the pixel 30 controls the gray scale values of the three colors red, green, and blue, and the gray scale value of each color is 256 (2 to the power of 8). 24 (8 × 3) bits of video data are required. However, in order to apply the video memory 43 having a data length of 16 bits to the present invention without increasing the capacity of the video memory 43, this embodiment first uses the bit processor 42 to obtain the maximum of three sets of RGB video data. The upper bits are taken in, transmitted to the video memory 43 and stored. For example, the 5 most significant bits of the red video data R, the 6 most significant bits of the green video data G, and the 5 most significant bits of the blue video data B are captured and processed. However, as long as the sum of the fetched bits does not exceed the 16-bit data length of the video memory 43, the most significant bit of 5 bits is fetched from each of the red, green, and blue three sets of video data R, G, and B and processed. It is also possible.

In the following, a description will be given by taking one set of RGB as an example. The video signal end 41 transmits 8-bit video data to the bit processor 42. The bit processor 42 processes the 8-bit video data D8 and outputs the 6-bit second captured video data D6 and the current 8-bit video data D8. Among them, the second captured video data D6 is obtained by the bit processor 42 capturing the 6 most significant bits from the current 8-bit video data D8, stored in the video memory 43, and output after being delayed by one frame period. . The delayed second captured video data D6 is defined as first captured video data D6 '. It should be noted that the first captured video data D6 ′ and the second captured video data D6 belong to two frames, respectively, and the 8-bit data D8 of the two frames is input with a difference of one frame period. It is input from the end 41.

The bit processor 42 transmits the second captured video data D6 and the current 8-bit video data D8 to the comparison circuit 44 and the multiplexer 46, respectively, and the first captured video data D6 ′ output from the video memory 43 is sent to the comparison circuit 44. It is transmitted and compared with the second captured video data D6. After the comparison circuit 44 compares the first captured video data D6 'and the second captured video data D6, the comparison result value is set to 0 or 1. When the comparison result value is 0, the first captured video data D6 ′ and the second captured video data D6 are the same, whereas when the comparison result value is 1, the first captured video data D6 ′ and the second captured video data D6 ′ are the same. The captured video data D6 is different. Since the first captured video data D6 ′ and the second captured video data D6 are obtained by capturing the 6 most significant bits from the two 8-bit video data D8, if the comparison result value is 0, both 8-bit video data The difference in D8 does not exceed 4. For example, when the first captured video data D6 ′ and the second captured video data D6 are 2 (that is, 000010), the comparison result value output from the comparison circuit 44 is 0 and the corresponding both 8-bit video data. The value of D8 is between 8 and 11 (ie 00001000 to 00001011), the difference does not exceed 4 and the pixel 30 does not need to be overdriven. Conversely, if the comparison result value is 1, the difference between the two 8-bit video data D8 exceeds 4, and the pixel 30 must be overdriven. For example, if the first captured video data D6 ′ is 2 (that is, 000010) and the second captured video data D6 is 5 (that is, 00101), the values of the corresponding 8-bit video data D8 are 8 to 11 (that is, 00001000), respectively. 000010011) and 20-23 (i.e., 00001100-00001111), the pixel 30 must be overdriven.

The lookup table device 45 has a parameter table and operates according to the parameter table. Please refer to FIG. FIG. 5 is an explanatory diagram showing the parameter table 50 of the reference table device 45 in FIG. In the parameter table 50, (2 ⁶ × 2 ⁶ ) or (2 ⁵ × 2 ⁵ ) pieces of 8-bit overdrive video data 52 are stored, and each overdrive video data 52 is stored in the first captured video data D6 ′. This corresponds to the combination of the second captured video data D6. When the comparison result value is 1 and the first captured video data D6 ′ and the second captured video data D6 are different, the first captured video data D6 ′ and the second captured video data D6 are transmitted to the reference table device 45. . Subsequently, the reference table device 45 selects the corresponding 8-bit overdrive video data 52 from the parameter table 50 based on the first captured video data D6 ′ and the second captured video data D6, and uses the multiplexer 46 as the first video data value D8 ′. Send to. For example, when the first captured video data D6 ′ is 2 (that is, 000010) and the second captured video data D6 is 5 (that is, 00101), the reference table device 45 has 8 values of 25 (that is, 00011001) from the parameter table 50. Bit overdrive video data D8 ′ is selected and transmitted to multiplexer 46. The comparison result value by the comparison circuit 44 is transmitted to the multiplexer 46 to control the operation of the multiplexer 46. If the comparison result value transmitted to the multiplexer 46 is 0, the multiplexer 46 outputs the current 8-bit video data D8, whereas if the comparison result value transmitted to the multiplexer 46 is 1, The multiplexer 46 outputs overdrive video data D8 ′. The output Dout of the multiplexer 46 is sent to the data line driving circuit 47, and the data line driving circuit 47 generates the corresponding data line voltage by the output Dout (equal to D8 or D8 ′) of the multiplexer 46, and the corresponding data line. 34 to control the display characteristics of the pixel 30. For example, when the first captured video data D6 ′ and the second captured video data D6 are 2 (ie, 000010) and the current 8-bit video data D8 value is 10 (ie, 00001010), the output of the multiplexer 46 The value Dout is 10 (ie, 00001010), and the data line driving circuit 47 generates a first data line voltage corresponding to the output value Dout of the multiplexer 46. If the first captured video data D6 ′ is 2 (ie, 000010) and the second captured video data D6 is 63 (ie, 111111), the overdrive video data D8 ′ output from the reference table device 45 is 255 (ie, 11111111). The output value Dout of the multiplexer 46 is also 255, and the data line driving circuit 47 generates a second data line voltage corresponding to the output value Dout of the multiplexer 46.

Still referring to FIG. FIG. 6 is an explanatory diagram showing other operations of the drive circuit 40. Here, the bit processor 42 takes in the most significant bits having a different number of bits from the 8-bit video data D8, for example, the most significant bit of 5 bits and the most significant bit of 6 bits from the 8-bit video data D8 to obtain the first captured video. Data D5 ′ and second captured video data D6 are used. In this case, the comparison circuit 44 compares the first captured video data D5 'with the second captured video data D6 and determines the comparison result value as 0 or 1. When comparing the first captured video data D5 ′ and the second captured video data D6, the comparison circuit 44 first fills in the least significant bit of the first captured video data D5 ′ and then fills the first captured video data. The data D5 ′ is compared with the second captured video data D6. For example, if the first captured video data D5 ′ and the second captured video data D6 are 7 (that is, 00111) and 10 (001010), respectively, the comparison circuit 44 compensates the first captured video data D5 ′ with 0, and 14 After conversion to (001110), the value of 14 is compared with 10 (001010), which is the value of the second captured video data D6. Similarly, if the comparison result value output from the comparison circuit 44 is 0, it is not necessary to overdrive the pixel 30, while if the comparison result value is 1, the pixel 30 must be overdriven. Is the same as described above. When the comparison circuit 44 compares the first captured video data D5 ′ and the second captured video data D6, 0 is supplemented to the first captured video data D5 ′, and the least significant bit of the second captured video data D6 is set. It is also possible to compare the first captured video data D5 ′ and the second captured video data D6 after deletion. For example, if the first captured video data D5 ′ and the second captured video data D6 are 7 (ie, 00111) and 10 (001010), respectively, the comparison circuit 44 deletes the least significant bit of the second captured video data D6. After conversion to 5 (that is, 00101), it is compared with 7 (that is, 00111) that is the value of the first captured video data D5 ′. Similarly, if the comparison result value output from the comparison circuit 44 is 0, it is not necessary to overdrive the pixel 30, while if the comparison result value is 1, the pixel 30 must be overdriven. Is the same as described above.

In this case, the data structure of the parameter table of the reference table device 45 needs to be changed accordingly. Please refer to FIG. FIG. 7 is an explanatory diagram showing the parameter table 70 in the case of FIG. The parameter table 70 stores (2 ⁵ × 2 ⁶ ) pieces of 8-bit overdrive video data 72. When the comparison result value is 1 and the first captured video data D5 ′ and the second captured video data D6 are different, the first captured video data D5 ′ and the second captured video data D6 are transmitted to the reference table device 45, The reference table device 45 selects the corresponding 9-bit overdrive video data 72 from the parameter table 70 based on the first captured video data D5 ′ and the second captured video data D6, and sends it to the multiplexer 46 as the first video data value D8 ′. Send.

In order to save power, the comparison circuit 44 transmits a reference table open / close signal to the reference table device 45. If the comparison result value is 1, the reference table opening / closing signal is high and the reference table device 45 is turned on. On the other hand, if the comparison result value is 0, the reference table opening / closing signal is low and the reference table device 45 is turned off. To do.

In this embodiment, the bit processor 42 takes in the most significant bits of N bits and P bits from the 8-bit video data D8 to form first captured video data and second captured video data. (N, P) is (6, 6) or (5, 6). However, (N, P) is not limited to (6, 6) or (5, 6), and there are other possibilities such as (5, 5). 8 and 9 will be referred to together with FIG. FIG. 8 is an explanatory diagram showing the drive circuit 40 when (N, P) is (5, 5), and FIG. 9 is an explanatory diagram showing the parameter table 90 in the case of FIG. When (N, P) is (5, 5), the operation method is similar to that when (N, P) is (6, 6), but the main distinction between the two is 8 The most significant bit of 5 bits is fetched from the bit video data D8, and the latter is to fetch the 6 most significant bits from the 8-bit video data D8. When (N, P) is (5, 5), the first captured video data D5 ′ and the second captured video data D5 are 5-bit video data, and the parameter table 90 has (2 ⁵ × 2 ⁵ ) pieces. The 8-bit overdrive video data 92 is stored. The reference table device 45 selects the corresponding video data value 92 from the parameter table 90 based on the first captured video data D5 ′ and the second captured video data D5, and controls the subsequent operation of the data line driving circuit 47.

Please refer to FIG. FIG. 10 is an explanatory diagram showing a drive circuit 100 according to Embodiment 2 of the present invention. The drive circuit 100 drives the liquid crystal display 30 in FIG. Similar to the drive circuit 40, the drive circuit 100 includes a video signal terminal 101, a bit processor 102, a video memory 103, a comparison circuit 104, a lookup table device 105, a multiplexer 106, a data line drive circuit 107, A memory 108, a parameter table selector 109, and a temperature sensor 111 are included, and the functions of these devices are the same as the corresponding devices in the drive circuit 44. In this embodiment, the video memory 103 is also a 16-bit memory, and the video signal end 101 transmits three sets of 8-bit RGB video data to the bit processor 102.

In the following, a description will be given by taking one set of RGB as an example. The video signal terminal 101 transmits 8-bit video data D8 to the bit processor 102. The bit processor 102 processes the 8-bit video data D8 and outputs 6-bit second captured video data D6 and 2-bit third captured video data D2. The second captured video data D6 is delayed by one frame period and converted to 6-bit first captured video data D6 '. Generation and transmission of the first captured video data D6 ′ and the second captured video data D6 are the same as in the first embodiment, and the 6 most significant bits are captured from the 8-bit video data D8. The data D2 is obtained by the bit processor 102 taking in the 2 least significant bits from the 8-bit video data D8. The bit processor 102 transmits the third captured video data D2 to the multiplexer 106.

The comparison circuit 104 compares the first captured video data D6 ′ with the second captured video data D6 and determines the comparison result value as 0 or 1. In this embodiment, the comparison process and the definition of the comparison result value are the same as those in the first embodiment, and the description thereof is omitted here. The comparison circuit 104 transmits the first captured video data D6 ′ and the second captured video data D6 to the reference table device 105 and transmits the comparison result value to the multiplexer 106. As in the first embodiment, when the first captured video data D6 ′ and the second captured video data D6 match or are different, the reference table device 105 uses the parameter table 50, the parameter table 60, or the parameter table 90 to store the overdrive video data. Match. The reference table device 105 selects 8-bit overdrive video data from the parameter table 50, the parameter table 60, or the parameter table 90 based on the first captured video data D6 ′ and the second captured video data D6 during the verification. The 2-bit least significant bit D2 ′ and the 6-bit most significant bit D6-out are taken in and output from the bit overdrive video data. For example, if the first captured video data D6 ′ is 2 (that is, 000010) and the second captured video data D6 is 3 (that is, 000011), the reference table device 105 has 8 from the parameter table 50 that is 25 (that is, 00011001). After selecting the bit overdrive video data, the 2-bit least significant bit (that is, 01) and the 6-bit most significant bit (000110) of the 8-bit overdrive video data are respectively fetched, and the multiplexer 106 and the data line driving circuit Outputs D2 ′ and D6-out transmitted to 107 are set. Similarly, the comparison result value by the comparison circuit 104 is transmitted to the multiplexer 106 to control the operation of the multiplexer 106. If the comparison result value transmitted to the multiplexer 106 is 0, the multiplexer 106 outputs the 2 least significant bits D2 of the current 8-bit video data D8, and transmits it to the multiplexer 106. If the comparison result value is 1, the multiplexer 106 outputs the output D2 ′ of the reference table device 105. The output D2-out of the multiplexer 106 is sent to the data line driving circuit 107. The data line driving circuit 107 outputs the output D2-out (equal to D2 or D2 ′) of the multiplexer 106 and the output D6-out of the reference table device 105. A corresponding data line voltage is generated and applied to the corresponding data line 34 to control the display characteristics of the pixel 30. For example, when the first captured video data D6 ′ and the second captured video data D6 are 2 (ie, 000010) and the current 8-bit video data D8 is 11 (ie, 00001011), the reference table device 105 is According to the parameter table 50, the overdrive video data 52 having a value of 8 (ie, 00001000) is selected, and both outputs D2 ′ and D6-out become 2 (ie, 000010) and 0 (ie, 00), respectively. D2-out is equal to the third captured video data D2 (ie, the least significant bit of 2 bits in the video data D8, which is 11 according to the binary display), and the data line driving circuit 107 has 2 bits in the current 8-bit video data D8. Overrider with least significant bit and value of 8 (ie, 00001000) The corresponding first data line voltage is generated by the 6 most significant bits D 6 -out in the Eve video data 52. If the first captured video data D6 ′ is 2 (that is, 000010) and the second captured video data D6 is 63 (that is, 111111), the reference table device 105 has an overdrive whose value is 255 (that is, 11111111) according to the parameter table 50. When the video data 52 is selected, both outputs D2 ′ and D6-out are 63 (ie, 111111) and 3 (ie, 11), respectively, and the data line driving circuit 107 responds by the overdrive video data 52 having a value of 255. A second data line voltage is generated.

When the liquid crystal molecules of the liquid crystal panel 31 are deflected by the data voltage, the reaction time varies depending on the temperature of the liquid crystal panel 31. In order to provide the liquid crystal display 30 with an optimal display effect at any temperature, in the first and second embodiments of the present invention, the drive circuit 40 and the drive circuit 100 have an appropriate parameter table depending on the temperature of the liquid crystal panel 31. Select. 4 and 10, each of the memory 48 and the memory 108 includes a plurality of parameter tables 54 and 114, and the parameter tables 54 and 114 respectively correspond to various liquid crystal panel temperatures. When the drive circuits 40 and 100 are in operation, the temperature sensors 51 and 111 detect the temperature of the liquid crystal panel 31 to generate a temperature compensation signal St and transmit it to the parameter table selectors 49 and 109. Therefore, the parameter table selectors 49 and 109 select one of the plurality of parameter tables 54 and 114 stored in the memories 48 and 108 according to the temperature compensation signal St and transmit it to the reference table devices 45 and 105. The reference table devices 45 and 105 output video data values D8 'and D2' according to the selected parameter table.

The first and second embodiments of the present invention are the same in terms of circuit devices, a method of capturing video data by a bit processor, a method of delaying video data, a method of comparing video data, a parameter table, and the like. The difference between the two is that Example 1 outputs the 8-bit value of the parameter table directly to the multiplexer, and Example 2 converts the 8-bit value of the parameter table to the 2 least significant bits and the 6 most significant bits. The output is divided and output to the multiplexer and the data line driving circuit. It should be noted that the least significant bit and the most significant bit captured by the drive circuit according to the present invention are not limited to the above-mentioned 6 bits, 5 bits, and 2 bits, but 7 bits and 1 bit are also possible.

The above is a preferred embodiment of the present invention and does not limit the scope of the present invention. Therefore, any modifications or changes that can be made by those skilled in the art, which are made within the spirit of the present invention and have an equivalent effect on the present invention, shall belong to the scope of the claims of the present invention. To do.

Since the driving circuit and driving method according to the present invention extract and process the most significant bit from the video data, it enables video processing and transmission without increasing the memory capacity and cost.

It is a timing diagram of pixel voltage and light transmittance V1 in a conventional liquid crystal display. FIG. 6 is a timing diagram of pixel voltage and light transmittance V2 in a conventional liquid crystal display using an overdrive driving method. It is a circuit diagram of a liquid crystal display. It is explanatory drawing showing the drive circuit by Example 1 of this invention. It is explanatory drawing showing the parameter table | surface of the reference table apparatus in FIG. It is explanatory drawing showing the other operation | movement of a drive circuit. It is explanatory drawing showing the parameter table in the case of FIG. It is explanatory drawing showing a drive circuit in case (N, P) is (5,5). It is explanatory drawing showing the parameter table in the case of FIG. It is explanatory drawing showing the drive circuit by Example 2 of this invention.

Explanation of symbols

30 liquid crystal display 31 liquid crystal panel 32 scan line 34 data line 36 pixel 38 switch device 39 pixel electrode 40, 100 drive circuit 41, 101 video signal terminal 42, 102 bit processor 43, 103 video memory 44, 104 comparison circuit 45, 105 Reference table device 46, 106 Multiplexer 47, 107 Data line drive circuit 48, 108 Memory 49, 109 Parameter table selector 50, 70, 90 Parameter table 51, 111 Temperature sensor 52, 72, 92 Overdrive video data 54, 114 Parameter table

Claims (20)

A method of driving a liquid crystal display, the liquid crystal display comprising:
Including a liquid crystal panel,
Multiple scanlines,
Multiple data lines,
A plurality of pixels each connected to a corresponding scan line and a corresponding data line and comprising a switch element connected to the corresponding scan line and the corresponding data line, the method comprising:
(A) continuously applying a scan voltage to the scan line ;
(B) receiving M-bit video data from the video signal end ;
(C) a step that causes a video data of N bits takes in the most significant bit of the N bits from the video data of M bits, of which N is below M,
(D) the image data of N bits by one frame period delay, step that produces an N-bit video data delayed,
(E) comparing the most significant bit of the P bits in the current M-bit video data with the delayed N-bit video data to determine a comparison result value;
(F) If the comparison result value is the first numerical value, the first video data value is output from the parameter table using the most significant bit of the P bits and the delayed N-bit video data, and the first video data value is output by the multiplexer. Selecting and applying a first data line voltage to the corresponding data line by the first video data value;
(G) If the comparison result value is a second numerical value, the current M-bit video data is selected by the multiplexer, and a second data line voltage is generated by the current M-bit video data and applied to the corresponding data line. A method for driving a liquid crystal display comprising steps. In addition,
(H) Step that produce a temperature compensation signal by the temperature of the liquid crystal panel,
2. The method of driving a liquid crystal display according to claim 1, further comprising the step of: (i) selecting a parameter table in step (f) from a plurality of parameter tables according to a temperature compensation signal. 2. The method of driving a liquid crystal display according to claim 1, wherein ( ^2N × ^2P ) video data values are recorded in the parameter table. 2. The method of driving a liquid crystal display according to claim 1, wherein the P exceeds N. 2. The method of driving a liquid crystal display according to claim 1, wherein P is equal to N. A method of driving a liquid crystal display, the liquid crystal display comprising:
Including a liquid crystal panel,
Multiple scanlines,
Multiple data lines,
A plurality of pixels each connected to a corresponding scan line and a corresponding data line and comprising a switch element connected to the corresponding scan line and the corresponding data line, the method comprising:
(A) continuously applying a scan voltage to the scan line;
(B) receiving a video data M bits from the video signal terminal,
(C) step that causes the video data of N bits takes in the most significant bit of the N bits from the video data of M bits, of which N is below M,
(D) the image data of N bits is delayed one frame period, that produce an N-bit video data delayed step,
(E) comparing the most significant bit of the P bits in the current M-bit video data with the delayed N-bit video data to determine a comparison result value;
(F) If the comparison result value is the first numerical value, the first video data value is output from the parameter table using the most significant bit of the P bits and the delayed N-bit video data, and the first video data value is output by the multiplexer. select the least significant bit of Q bits in step applied to the corresponding data line causes a first data line voltage by the first image data value ,,
(G) If the comparison result value is the second numerical value, the second video data value is output from the parameter table by the most significant bit of P bits and the delayed N-bit video data, and the current M-bit video data is output by the multiplexer. The least significant bit of the Q bits is selected, and the second data line voltage is generated by the most significant bit of the (MQ) bits in the second video data value and the least significant bit of the Q bits in the current M bit video data. And applying to the corresponding data line. A method for driving a liquid crystal display. In addition,
(H) Step that produce a temperature compensation signal by the temperature of the liquid crystal panel,
7. The liquid crystal display driving method according to claim 6, further comprising the step of: (i) selecting a parameter table in step (f) according to claim 6 from a plurality of parameter tables according to a temperature compensation signal. 7. The method of driving a liquid crystal display according to claim 6, wherein ( ^2N * ^2P ) video data values are recorded in the parameter table. 7. The method of driving a liquid crystal display according to claim 6, wherein the P exceeds N. 7. The method of driving a liquid crystal display according to claim 6, wherein the P is equal to N. A driving circuit for driving a liquid crystal display, wherein the liquid crystal display is
Including a liquid crystal panel,
Multiple scanlines,
Multiple data lines,
A plurality of pixels each connected to a corresponding scan line and a corresponding data line and comprising a switch element connected to the corresponding scan line and the corresponding data line, the drive circuit comprising:
A scan line driving circuit for continuously applying a scan voltage to the scan line; and
A video signal end for receiving M-bit video data;
A bit processor that takes N bits most significant bit lower than M from M bit video data and generates N bit video data;
A video memory that stores N-bit video data and outputs it after being delayed by one frame period;
A comparison circuit for comparing the most significant bit of the P bits in the current M-bit video data with the delayed N-bit video data to determine a comparison result value;
A look-up table device for outputting video data values according to the most significant bit of P bits and delayed N-bit video data;
A multiplexer that selectively outputs the video data value or the current M-bit video data according to the comparison result value;
And a data line driving circuit for generating a data line voltage by an output of the multiplexer and applying the data line voltage to a corresponding data line. The drive circuit further includes
A temperature sensor that senses the temperature of the liquid crystal panel and generates a temperature compensation signal;
A memory for storing multiple parameter tables,
By selecting one parameter table from a plurality of parameter tables stored in the memory according to the temperature compensation signal and transmitting it to the reference table device, the reference table device outputs the video data value according to the selected parameter table. The drive circuit according to claim 11, further comprising a selector for causing the selector to operate. 12. The drive circuit according to claim 11, wherein (2 ^N × 2 ^P ) video data values are recorded in the parameter table. The drive circuit according to claim 11, wherein the P exceeds N. 12. The driving circuit according to claim 11, wherein the P is equal to N. A driving circuit for driving a liquid crystal display, wherein the liquid crystal display is
Including a liquid crystal panel,
Multiple scanlines,
Multiple data lines,
A plurality of pixels each connected to a corresponding scan line and a corresponding data line and comprising a switch element connected to the corresponding scan line and the corresponding data line, the drive circuit comprising:
A scan line driving circuit for continuously applying a scan voltage to the scan line; and
A video signal end for receiving M-bit video data;
A bit processor that takes N bits most significant bit lower than M from M bit video data and generates N bit video data;
A video memory that stores N-bit video data and outputs it after being delayed by one frame period;
A comparison circuit for comparing the most significant bit of the P bits in the current M-bit video data with the delayed N-bit video data to determine a comparison result value;
A look-up table device for outputting video data values according to the most significant bit of P bits and delayed N-bit video data;
A multiplexer that selectively outputs the least significant bit of the Q bits in the video data value or the least significant bit of the Q bits in the current M bit video data according to the comparison result value;
And a data line driving circuit for generating a data line voltage to be applied to a corresponding data line according to the most significant bit of (MQ) bits in the output of the multiplexer and the video data value. The drive circuit further includes
A temperature sensor that senses the temperature of the liquid crystal panel and generates a temperature compensation signal;
A memory for storing multiple parameter tables,
By selecting one parameter table from a plurality of parameter tables stored in the memory according to the temperature compensation signal and transmitting it to the reference table device, the reference table device outputs the video data value according to the selected parameter table. The drive circuit according to claim 16, further comprising a selector for causing the selector to operate. 17. The driving circuit according to claim 16, wherein (2 ^N × 2 ^P ) video data values are recorded in the parameter table. The drive circuit according to claim 16, wherein the P exceeds N. The drive circuit according to claim 16, wherein P is equal to N.