JP3989318B2 - Clock monitoring device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an external device that converts an analog value into a PDM, a sampling clock supplied from the external device, and a device that processes PDM data and converts the analog value into a multi-bit digital value. The present invention relates to a clock monitoring device for monitoring an increase or decrease of a sampling clock due to poor contact or external noise in a transmission path for transmitting data, and suppressing an analog data conversion error.
[0002]
[Prior art]
A conventional clock device is shown in FIGS.
FIG. 5 is a block diagram of a conventional clock device, in which 31 is a clock change detection unit that detects a change in the clock to be monitored, 32 is an up counter timer, 34 is an error detection unit that detects an overflow of the timer output, and 35. Is an error output unit that holds an error detection signal and outputs the held data.
Next, the operation of the clock device will be described with reference to FIG.
First, when power is applied, a reset signal 13 is input to put the circuit in a desired signal output state, and the circuits 31, 32, and 35 are in an initial state. The system clock 12 is a system startup clock. The clock input 11 is a clock to be monitored and has a lower frequency than the system clock 12 .
When the clock 11 is input to the clock change detection unit 31, it passes through two internal storage elements (not shown) connected in series. Since these two storage elements store the clock input signal in units of the system clock 12, each time the clock input 11 changes, a pulse for one cycle of the system clock is output as the clock change detection output 15.
The timer unit 32 is an up counter and always counts up with the system clock 12. When the clock change detection output 15 is input thereto, the timer value is set to “0”.
The error detection unit 34 inputs the timer output 21 output from the timer unit 32 to the error detection unit 34 and outputs an error detection output 41 when all the timer outputs 21 are “H”.
The error output unit 35 holds an error detection output 41 and outputs the held signal as an error output 51.
FIG. 6 is a time chart of signals of the respective circuits shown in FIG. 5. When the clock input 11 is stopped as indicated by a dotted line, the error detection unit 34 outputs the timer output 21 output from the timer unit 32. When all become “H” (when the seventh output of the timer output 21 becomes “H” in FIG. 6), the error detection signal 41 is turned on, and the error detection unit 35 turns on the error output 51. Indicates the state.
[0003]
[Problems to be solved by the invention]
However, in the conventional technique described above, the sampling clock supplied from the external device has increased or decreased due to the loss of the clock caused by poor contact due to the deterioration of the transmission path or the increase of the clock due to external noise. In the case of this technology, only the stop of the clock due to disconnection can be detected.
For example, FIG. 7 shows an example in which the clock input 11 is increased (detection edge is increased). When the edge of the clock input 11 increases in this way, a change in the edge can be detected, but since the timer loaded by this detection does not reach the error detection value (overflow), it cannot be detected until the clock increases or decreases.
Therefore, there is a problem that the data processed with respect to the clock includes an error.
Therefore, the present invention provides a clock monitoring device that detects an increase / decrease in a clock, detects that an error is included in data obtained by performing signal processing based on the clock, and enables processing for suppressing the error. The purpose is that.
[0004]
[Means for Solving the Problems]
To achieve the above object, according to claim 1 invention the signal processing PDM data which the external device outputs in accordance with a sampling clock supplied from the external device to the external device for PDM converts the analog values of the multi-bit the clock monitoring apparatus for monitoring the sampling clock apparatus including signal processing circuit for converting into a digital value, from a change detector for detecting a change of the sampling clock, the time measurement for each change detection of said sampling clock An initial condition output unit that prevents malfunction of the signal processing circuit when the power is turned on, an error detection unit that detects increase / decrease or stop of the sampling clock from the output of the timer unit, and an error detection unit And an error output unit for holding an output.
Further, an invention according to claim 2, wherein the timer unit is a bit timer of the number of bits determined in advance, the error detection unit detects an increase or decrease or stop of the sampling clock by an output of said bit timer And an error detection signal is output.
In this clock monitoring device, when detecting an abnormality in the clock input, for example, if the bit of the bit timer output is 3 bits and a 3-bit timer output is used, 3 bits = 2 ³ kinds of states are detected. Among them, "111" indicates the stop state of the clock input, and "010", ... indicates the state of increase of the clock frequency, so that the detailed state can be detected. Compared to the case where only the stop state can be detected, an abnormal state due to increase or decrease of the clock can be detected more accurately.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 is a block diagram of a clock monitoring apparatus according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the clock monitoring apparatus shown in FIG. 1, and FIGS. 3 and 4 are time charts of signals.
In FIG. 1, 1 is a clock change detection unit that inputs a clock input 11 and outputs a pulse for one cycle of the system clock 12, 2 is a timer unit that outputs a 3-bit timer value by a 3-bit timer, and 3 is an initial condition. An output unit 4 is an error detection unit that determines a 3-bit timer output and outputs an error detection signal, and 5 is an error output unit.
[0006]
Next, the operation of the clock monitoring device in FIG. 1 will be described.
After the power supply is applied, the clock change detector 1 is initialized to a desired value. At the same time, the reset signal 13 and the error clear signal 14 input through the logic element 19 initialize the timer unit 2, the initial condition output unit 3, and the error output unit 5 to desired values.
In this case, the clock input 11 is a clock to be monitored and has a frequency lower than that of the system clock 12.
Next, referring to the circuit diagram of the clock monitoring device of FIG. 2, when the clock input 11 is first input to the clock change detection unit 1, it passes through the two storage elements 16 and 17 connected in series. The two storage elements 16 and 17 are connected to the logic element 18.
Since the storage elements 16 and 17 store the clock input 11 in units of the system clock 12, the output of the logic element 18 outputs a pulse corresponding to one cycle of the system clock as the clock change detection output TRG whenever the clock input 11 changes. To do. In this state, the signal waveform DVMCLKd of the storage element 16, the waveform DVMCLKdd of the storage element 17, and the output waveform TRG of the logic element 18 for one cycle of the system clock 12 and the counter value are shown at the same interval in the time chart of FIG. .
Next, the timer unit 2 always counts up with the system clock 12 by an up counter. When the clock change detection output TRG is input thereto, the timer value is set to “0” and counted as shown in the count value of FIG.
The error detection unit 4 is composed of a logic element AND, and the timer output output from the timer unit 2 is input to this logic element.
3 is a time chart in a normal state, and FIG. 4 shows a time chart in an abnormal state.
Now, change the clock change detection output TRG and the 3-bit timer output as “000”, “001”, “010”, “011”, “100”, “101”, “110”, “111”, etc. Among them, if “000”, “001”, “010”, “111” is an error state, and “011”, “100”, “101”, “110” are normal, the error detection unit 4 When the 3-bit timer output is “000”, “001”, “010”, “111”, an error detection output is output.
The error output unit 5 holds the error detection output from the error detection unit 4 and outputs the held signal as an error output ER.
In the normal operation as shown in FIG. 3, when the clock change detection output TRG is generated, one of the timer outputs “011”, “100”, “101”, and “110” is output. In this case, the error detection unit 4 determines that it is normal, and “L” is output as the error detection output. Therefore, the error output unit 5 outputs normal.
[0007]
FIG. 4 shows a time chart of error detection when the frequency of the clock input 11 is increased. As shown in FIG. 4, when the frequency of the clock input 11 is now increased, a change in edge is detected. Since the interval at which the clock change detection output is output is shortened, the bit values of the clock change detection output TRG and the timer output are “010”, so that the error detection output is output and the error output ER is output from the error output unit 5. Is output.
When the clock is stopped as in the conventional case, the timer output is “111”, and the error detection unit 4 determines that an error has occurred, and the error output unit 5 outputs the error output ER.
Up to this point, the timer output has been described as a 3-bit timer output. However, the timer output is not limited to 3 bits, and the number of bits can be arbitrarily increased or decreased depending on the situation. For example, if the number of bits is increased to 4 bits,.
[0008]
【The invention's effect】
As described above, according to the present invention, since an arbitrary time is detected from the output of the timer loaded with the clock change detection output, an increase in clock edges due to noise superposition or a contact failure due to deterioration of the transmission path can be detected. There is an effect that it is possible to detect the loss of the generated clock.
In addition, the disconnection of the clock transmission path can be detected as in the conventional case.
[Brief description of the drawings]
FIG. 1 is a block diagram of a clock monitoring apparatus according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of the clock monitoring apparatus shown in FIG.
FIG. 3 is a time chart of signals in a normal state.
FIG. 4 is a time chart of signals at the time of abnormality.
FIG. 5 is a block diagram of a conventional clock device.
6 is a time chart of signals of each circuit shown in FIG. 5. FIG.
FIG. 7 is a time chart showing an example of an increase in clock input.
[Explanation of symbols]
1 Clock change detection unit 2 Timer unit 3 Initial condition output unit 4 Error detection unit 5 Error output unit

Claims (2)

An external device that converts an analog value into PDM (Pulse density modulation);
A signal processing circuit for converting the PDM data the external device to output in accordance with a sampling clock supplied from the external device to the signal processing digital value of multi-bit,
In the clock monitoring device for monitoring the sampling clock of the device comprising :
A clock change detection unit that detects a change of the sampling clock,
A timer unit for measuring time every time a change in the sampling clock is detected;
An initial condition output unit for preventing malfunction of the signal processing circuit at power-on;
An error detection unit for detecting increase / decrease or stop of the sampling clock from the output of the timer unit;
An error output unit for holding the output of the error detection unit;
A clock monitoring device comprising: The timer unit is a bit timer having a predetermined number of bits,
Said error detection unit, a clock monitoring apparatus according to claim 1, wherein by detecting an increase or decrease or stop of the sampling clock by an output of the bit timer and outputs an error detection signal.

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