JP3989628B2 - Data transmission / reception circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission / reception circuit for transmitting baseband digital data via a transmission line.
[0002]
[Prior art]
As shown in FIG. 4, a conventional data transmission / reception circuit of this type includes first and second transmission / reception circuits 1 and 2 arranged opposite to each other via a data line L1. In the first transmission / reception circuit 1, a receiver 3 and a driver 4 are connected to one end of a transmission line (data line) L1. One end of the transmission line L1 is connected to a DC power source + V through a resistor Ra and is connected to a common potential point through a resistor Rb. The parallel combined resistance value of the resistors Ra and Rb is set substantially equal to the characteristic impedance Zo of the transmission line L1. The input / output terminals of the receiver 3 and the driver 4 have substantially the same circuit configuration as the input / output terminals of the TTL IC. Therefore, its own output impedance is relatively low and the input impedance is relatively high.
[0003]
The configuration of the second transmission / reception circuit 2 is the same as that of the first transmission / reception circuit 1 described above.
When the characteristic impedance Zo of the transmission line L1 is 120 to 130Ω, Ra≈220Ω and Rb≈330Ω are selected. The same applies to Rc and Rd. Therefore, the divided voltage by only these resistors is about 4V when the power supply voltage (+ V) is 5V, which is a so-called H level (high level) voltage. Terminating both ends of the transmission line L1 by parallel combined resistors of resistors Ra, Rb and Rc, Rd (referred to as the Thevenin termination) enables the signal waveform quality to be ensured even if the line length becomes long. Yes.
[0004]
[Problems to be solved by the invention]
(1) When the first transmitter / receiver circuit is mounted on a small computer and the second transmitter / receiver circuit is mounted on a peripheral device, and the number of data lines, that is, the number of channels is large, the power supplied from the power source (+ V) to the line termination resistor is There was a problem that it became larger and exceeded the supply capacity of small computers.
[0005]
(2) When the number of channels is large, there is a problem that the heat dissipation structure becomes complicated in order to suppress the temperature rise in the small computer due to the heat generated by the termination resistor group.
(3) When the number of channels is large, there is a problem that the accommodation space for the terminating resistor in the small computer becomes large and the mounting becomes difficult.
[0006]
[Means for Solving the Problems]
(1) A data transmission / reception circuit according to claim 1 is a low-power-consumption first data transmission / reception circuit disposed at one end of a transmission line composed of a data line and a control line, and a second data transmission / reception disposed at the other end. It consists of a circuit.
The first data transmission / reception circuit includes a receiver and a tri-state type driver that is activated (enabled) by an enable signal given to a control terminal connected to one end of a data line, and a control driver that sends an enable signal. Connected to one end of the control line.
[0007]
In the second data transmitting / receiving circuit, a termination resistor (R4) having a resistance value substantially equal to the characteristic impedance of the control line is connected between the other end of the control line and the common potential point, and the receiver is used for data A tri-state transmission circuit connected to the other end of the line and controlled inactive by an enable signal is connected to the other of the data line via a first resistor having a resistance value approximately equal to the characteristic impedance of the data line. Connected to the end. A DC power source is connected to the other end of the data line through a series circuit of a first switch means and a second resistor that are controlled to be opened and closed by an enable signal, and the common potential point is controlled to be opened and closed by an enable signal. The second switch means and the third resistor are connected to the other end of the data line via a series circuit. The parallel combined resistance value of the second and third resistors is set substantially equal to the characteristic impedance of the data line.
[0008]
(2) In the invention of claim 2, in the above (1), the first and second switch means are formed of a tri-state buffer.
(3) In the invention of claim 3, in (1), the transmission circuit of the second transmission / reception circuit has an inverter whose input terminal is connected to the other end of the control line, and an output of the inverter is given to the control terminal. And a tri-state type driver.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention is shown in FIG. 1 with parts corresponding to those in FIG.
First and second ( hereinafter, data notation may be omitted ) transmission / reception circuits 1 and 2 are arranged opposite to each other across the data line L1 and the control line L2. The first transmission / reception circuit 1 is mounted on a small computer, for example, and the second transmission / reception circuit 2 is mounted on a peripheral device, for example.
[0010]
In the first (data) transmission / reception circuit 1, the receiver 3 and the tristate type driver 4 (the output terminal is opened in the non-enabled state) activated (enabled) by the enable signal Se applied to the control terminal are data. It is connected to one end of the work line L1. A control driver 5 for sending an enable signal Se is connected to one end of the control line L2.
[0011]
In the second data transmission / reception circuit 2, a termination resistor (R4) having a resistance value approximately equal to the characteristic impedance Zo of the control line is connected between the other end of the control line L2 and the common potential point. The receiver 6 is connected to the other end of the data line L1. A tri-state transmission circuit 11 controlled inactive by an enable signal Se is connected to the other end of the data line L1 via a resistor R1 having a resistance value substantially equal to the characteristic impedance Zo of the data line L1. The A DC power source + V is connected to the other end of the data line L1 through a series circuit of a first switch means (in this example, a buffer 9) controlled to be opened and closed by an enable signal Se and a resistor R2. The common potential point is connected to the other end of the data line L1 through a series circuit of a second switch means (in this example, a buffer 10) whose opening and closing is controlled by an enable signal Se and a resistor R3. The parallel combined resistance value of the resistors R2 and R3 is set substantially equal to the characteristic impedance Zo of the data line L1.
[0012]
In the example of FIG. 1, the first and second switch means 9 and 10 are constituted by tristate buffers. The transmission circuit 11 includes an inverter 8 whose input terminal is connected to the other end of the control line L2, and a tri-state driver 7 whose output is supplied to the control terminal.
The receivers 3 and 6, the enabled drivers 4 and 7 and the buffers 9 and 10, the control driver 5 and the inverter 8 are input / output terminals of the TTL type IC, and the input impedance is relatively high, and the output impedance Is relatively low.
[0013]
Next, data transfer between the transmission / reception circuits 1 and 2 will be described.
(1) When transferring data from the first transmitting / receiving circuit 1 side to the second transmitting / receiving circuit 2 side When the enable signal Se of the first transmitting / receiving circuit 1 is set to L (low) level (FIG. 2A), the driver 4 is enabled. . The enable signal Se is transferred to the second transmitting / receiving circuit 2 side, the buffers 9 and 10 are enabled, and the driver 7 is disabled. Therefore, a transmission / reception path as shown in FIG. 3A is configured, and data transfer can be performed (FIG. 2B).
[0014]
(2) When transferring data from the second transmitting / receiving circuit 2 side to the first transmitting / receiving circuit 1 side When the enable signal Se on the first transmitting / receiving circuit 1 side is set to H (high) level (FIG. 2A), the driver 4 and the buffer 9 , 10 are disabled (the output terminal is open), and the driver 7 is enabled. Therefore, the transmission / reception path shown in FIG. 3B is configured, and data transfer can be performed (FIG. 2C). The signal transmitted from the driver 7 propagates to the receiver 3 via R1 and L1, and then is totally reflected due to its high input impedance, returns to L1, and is terminated at R1.
[0015]
【The invention's effect】
(1) In the present invention, since the termination resistors R2 and R3 connected to the power source are not provided in the first transmission / reception circuit 2 but in the second transmission / reception circuit 2, the first transmission / reception circuit 1 is provided in a small computer. If built-in, no power is consumed by the termination resistor regardless of the number of channels, and power consumption can be suppressed.
[0016]
(2) For the same reason, the heat dissipation structure of the small computer can be simplified and the mounting space problem can be solved.
(3) When the terminating resistors R2 and R3 are connected, a high-speed buffer IC is used as a switch, so that the data transfer direction can be changed at high speed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is an operation waveform diagram of the main part of FIG.
3 is a circuit diagram showing a data transmission path configured when the enable signal is set to L level and H level in FIG. 1, respectively.
FIG. 4 is a circuit diagram of a conventional data transmission / reception circuit.

Claims (3)

A first data transmission / reception circuit with low power consumption disposed at one end of a transmission line composed of a data line and a control line, and a second data transmission / reception circuit disposed at the other end,
The first data transmission / reception circuit includes:
A receiver and a tri-state type driver activated (enabled) by an enable signal given to the control terminal are connected to one end of the data line,
A control driver for sending the enable signal is connected to one end of the control line;
The second data transmission / reception circuit includes:
A termination resistor (R4) having a resistance value substantially equal to the characteristic impedance of the control line is connected between the other end of the control line and the common potential point,
A receiver is connected to the other end of the data line;
A tri-state transmission circuit controlled inactive by the enable signal is connected to the other end of the data line via a first resistor having a resistance value substantially equal to the characteristic impedance of the data line;
A DC power source is connected to the other end of the data line via a series circuit of a first switch means and a second resistor that are controlled to open and close by the enable signal.
A common potential point is connected to the other end of the data line via a series circuit of second switch means and third resistor controlled to be opened and closed by the enable signal,
A data transmitting / receiving circuit, wherein a parallel combined resistance value of the second and third resistors is set substantially equal to a characteristic impedance of the data line.  2. A data transmitting / receiving circuit according to claim 1, wherein said first and second switch means comprise a tri-state buffer. 2. The inverter according to claim 1, wherein the transmission circuit of the second data transmission / reception circuit includes an inverter having an input terminal connected to the other end of the control line, and a tri-state driver in which an output of the inverter is applied to the control terminal. A data transmission / reception circuit.

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