JP3991981B2 - Signal output circuit - Google Patents

Description

  The present invention relates to a signal output circuit used in a sensor that detects acceleration, angular velocity, pressure, and the like.

  A sensor that detects acceleration, angular velocity, pressure, and the like generally electrically amplifies a conversion element for converting a displacement amount of the detection target into an electric signal and a weak electric signal output from the element. Output circuit. The output circuit shown in FIG. 6 is known.

  In FIG. 6, reference numeral 26 denotes a first differential amplifier. The first differential amplifier 26 includes source-coupled transistors 1 and 2, a source of the transistors 1 and 2, and a first power supply terminal 33. An electric signal from a sensor is input to the gate of the transistor 1, and a first reference voltage setting means 28 is applied to the gate of the transistor 2.

  Reference numeral 30 denotes a first current mirror as an active load of the first differential amplifier 26. The first current mirror 30 has a diode-coupled transistor 3 and a gate connected to the gate of the transistor 3. The transistor 4 includes a gate and a drain connected to the drain of the transistor 1, a source connected to the second power supply terminal 34, and a drain of the transistor 4 connected to the drain of the transistor 2. The source is connected to the second power supply terminal 34.

  Reference numeral 5 denotes a preamplification transistor, the gate is connected to the drain of the transistor 2 which is the output of the first differential amplifier 26, and the source is connected to the second power supply terminal 34 via the constant current source 21. The drain is connected to the first power supply terminal 33.

  An output transistor 6 has a gate connected to the source of the transistor 5, a source connected to the second power supply terminal 34, and a drain connected to the first power supply terminal 33 via the constant current source 22. Connected. The drain of the transistor 6 is connected to the output terminal 32.

  In this output circuit, since the sum of the current flowing from the drain of the transistor 3 to the drain of the transistor 1 and the current flowing from the drain of the transistor 4 to the drain of the transistor 2 is kept constant, the gate of the transistor 1 When the input signal input to the transistor 5 increases, the drain voltage of the transistor 2 that is the output of the first differential amplifier 26 increases, and the gate voltage of the transistor 5 is the same as the drain voltage of the transistor 2, so that the transistor 5 The source voltage of increases. When the source voltage of the transistor 5 increases, the drain voltage of the transistor 6 decreases, and as a result, the output voltage of the output terminal 32 decreases.

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP-A-2-62106

However, in the conventional signal output circuit described above, when the output voltage is transmitted to the power receiving side circuit using the electric wire, the following problems occur when the electric wire is disconnected or shorted to the ground potential.

  That is, the input voltage to the power receiving side circuit is 0 V, but it is possible to determine whether this 0 V is a voltage as a normal output of the sensor, or a voltage due to a break in the electric wire or a short to the ground potential. There is a problem that a detection circuit for detecting a short circuit must be provided separately.

  It is an object of the present invention to provide an output circuit that can detect a disconnection of a wire or a short circuit to a ground potential without providing this detection circuit.

In order to achieve this object, according to a first aspect of the present invention, an input signal is applied to one input terminal and a first reference voltage setting means is connected to the other input terminal. A first active load provided in the first differential amplifier, a gate connected to the output terminal of the first differential amplifier, and a first constant current source connected to the source; A transistor, a second transistor having a gate connected to a connection point of the first transistor and the first constant current source, and a drain connected to a second constant current source and an output terminal; and one working terminal Is connected to the connection point of the first transistor and the first constant current source, and the current flowing through the first transistor in the range where the output voltage corresponding to the input signal at the output terminal exceeds a predetermined limit voltage Bypass the working terminal A limiter unit for the output voltage at the output terminal by controlling the serial first of the transistors first potential at the connection point of the constant current source is configured to maintain the predetermined limit voltage, provided to the limiter means A limiter canceling means for disabling control by the limiter means so as to output the output voltage according to the input signal even in a range exceeding the limit voltage by the limiter canceling signal, and the limiter canceling means are operated. And when the abnormality detection output signal generated when abnormality is detected is applied, the first differential amplifier is maintained so that the output voltage is maintained at a voltage set in a range exceeding the predetermined limit voltage. This is a signal output circuit with output saturation means to control, and it is possible to break the wire or short to the ground potential without providing a detection circuit. Operational effects of being able to exit. In addition, since the limiter canceling means and the output saturation means are provided, there is an effect that the abnormality can be detected even when an abnormality occurs other than a disconnection or a short circuit to the ground potential.

According to a second aspect of the invention, limiter means, second differential connected to the second reference voltage setting means for connecting said output terminal to one input terminal, to set the limit voltage to the other input terminal An amplifier, a second active load provided in the second differential amplifier, a gate connected to an output terminal of the second differential amplifier, and a connection point between the first transistor and the first constant current source 2. The signal output circuit according to claim 1, comprising at least a third transistor having a source connected as a working terminal , wherein an output voltage output from the output terminal does not become lower than the second reference voltage. By setting the second reference voltage to a value larger than 0V, the output voltage is not 0V in a normal state. Therefore, when the output voltage is 0V, it is possible to determine that a disconnection or a short to the ground potential has occurred.

According to a third aspect of the present invention, the second reference voltage setting means includes a fourth transistor having a source connected to the other input terminal of the second differential amplifier and a drain connected to the ground potential, and the second transistor . 3. A current supply source connected to a connection point between the other input terminal of the differential amplifier and the source of the fourth transistor, and a second reference voltage source connected to the gate of the fourth transistor. The signal output circuit described is effective in that the second reference voltage can be easily set.

  According to a fourth aspect of the invention, the second differential amplifier comprises source-coupled sixth and seventh transistors and a third constant current source connected to the sources of the sixth and seventh transistors. Item 2. The signal output circuit according to Item 2, wherein the output voltage and the second reference voltage can be compared with high accuracy with a simple configuration. In addition, since the output voltage is directly input to the second differential amplifier, there is an effect that the response speed becomes faster compared to the case where the output voltage passes through another circuit or the like.

  According to the fifth aspect of the present invention, the limiter canceling means connects the drain to the source of the fourth transistor of the second reference voltage setting means, connects the source to the ground potential, and connects the gate to the input terminal of the limiter canceling signal. The signal output circuit according to claim 3, comprising the fifth transistor, and has the same effect as that of claim 1.

  According to a sixth aspect of the invention, the limiter canceling means connects the source to the common source of the sixth and seventh transistors constituting the second differential amplifier, connects the drain to the power supply potential, and releases the limiter to the gate. 5. The signal output circuit according to claim 4, wherein the signal output circuit is constituted by an eighth transistor serving as a signal input terminal.

  According to the seventh aspect of the present invention, the limiter canceling means is a ninth transistor in which the source is connected to the gate of the third transistor constituting the limiter means, the drain is connected to the power supply potential, and the gate is the input terminal of the limiter canceling signal. The signal output circuit according to claim 2, which is composed of the above-described transistors, exhibits the same effects as those of claim 1.

According to an eighth aspect of the present invention, the output saturation means connects the drain to the input terminal to which the first reference voltage of the first differential amplifier is input, connects the source to the ground potential, and detects the abnormality of the gate. 2. The signal output circuit according to claim 1, comprising a tenth transistor serving as an input terminal for an output signal, and has the same effect as that of claim 1.
According to the ninth aspect of the present invention, the limiter unit connects the output terminal to one input terminal via the first level adjusting unit that performs a transition for a predetermined voltage, and sets the limit voltage to the other input terminal. A second differential amplifier in which a second reference voltage setting means to be connected is connected via a second level adjusting means for making a transition for a predetermined voltage, and a second active load provided in the second differential amplifier And a third transistor having a gate connected to the output terminal of the second differential amplifier and a source serving as an operation terminal connected to a connection point between the first transistor and the first constant current source. The signal output circuit according to Item 1, wherein the limit voltage can be set to a voltage equal to or lower than the second reference voltage, the operation range can be expanded, and the output voltage output from the output terminal is newly Less than the set limit voltage Because not to, the output voltage never becomes 0V in the normal state by the limit voltage set this new and 0V larger value. Therefore, when the output voltage is 0 V, it is possible to determine that a disconnection or a short circuit to the ground potential has occurred.

The present invention provides a first differential amplifier in which an input signal is applied to one input terminal and the first reference voltage setting means is connected to the other input terminal, and a first differential amplifier provided in the first differential amplifier. Active load, a first transistor having a gate connected to the output terminal of the first differential amplifier and a first constant current source connected to the source, the first transistor and the first constant current A second transistor having a gate connected to a source connection point, a second constant current source and an output terminal connected to a drain, and one working terminal of the first transistor and the first constant current source; In a range in which an output voltage corresponding to the input signal at the output terminal exceeds a predetermined limit voltage, the current flowing through the first transistor is bypassed through the working terminal and the first transistor and the first transistor are connected to a connection point. 1 constant current source connection A limiter unit for the output voltage at the output terminal by controlling the potential of the point is configured to maintain the predetermined limit voltage, it is provided in the limiter means, by the limiter release signal in a range exceeding the predetermined limit voltage Even if there is a limiter canceling unit that disables the control by the limiter unit to output the output voltage according to the input signal, and an abnormality detection that occurs when the limiter canceling unit is activated and an abnormality is detected A signal output circuit comprising output saturation means for controlling the first differential amplifier so that the output voltage is held at a voltage set in a range exceeding the predetermined limit voltage when an output signal is applied. By providing the limiter means, there is a disconnection of the electric wire or a short circuit to the ground potential without providing a separate detection circuit. It is possible is to detect a short circuit to the power supply potential.

  Hereinafter, a signal output circuit of the present invention will be described with reference to embodiments and drawings. A sensor was used as means for inputting a signal to the signal output circuit.

(Embodiment 1)
The invention according to the first to fourth aspects of the present invention will be described with reference to the first embodiment and FIG.

  First, the configuration of the signal output circuit according to the first embodiment will be described.

In FIG. 1, reference numeral 26 denotes a first differential amplifier. The first differential amplifier 26 includes source-coupled transistors 1 and 2, a common source of the transistors 1 and 2, and a first power supply terminal 33. The signal from the sensor is input to the gate of the transistor 1, and the first reference voltage setting means 28 supplies the first reference voltage to the gate of the transistor 2. A voltage is given.

  Reference numeral 30 denotes a first current mirror as an active load of the first differential amplifier 26. The first current mirror 30 includes a diode-coupled transistor 3 and a transistor having a gate connected to the gate of the transistor 3. 4. The gate and drain of the transistor 3 are connected to the drain of the transistor 1, the source of the transistor 3 is connected to the second power supply terminal 34, the drain of the transistor 4 is connected to the drain of the transistor 2, and the transistor 4 is connected to the second power supply terminal 34.

  Reference numeral 5 denotes a first transistor for preamplification, the gate is connected to the drain of the transistor 2 which is the output of the first differential amplifier 26, and the source is connected via the first constant current source 21. The drain is connected to the second power supply terminal 34 and the drain is connected to the first power supply terminal 33.

  Reference numeral 6 denotes a second transistor for output, the gate is connected to the source of the first transistor 5, the source is connected to the second power supply terminal 34, the drain is the output terminal 32 and the second constant current. It is connected to the first power supply terminal 33 via the source 22.

  Reference numeral 27 denotes a second differential amplifier. The second differential amplifier 27 includes source-coupled sixth and seventh transistors 8 and 9 and sources of the sixth and seventh transistors 8 and 9. And a third constant current source 23 connected between the first power supply terminal 33 and the gate of the sixth transistor 8 via the constant current source 24. 34 and to the source of the transistor 12 for output monitoring. The transistor 12 has a drain connected to the first power supply terminal 33 and a gate connected to the output terminal 32.

  The gate of the seventh transistor 9 is connected to the second power supply terminal 34 via the constant current source 25 and to the source of the fourth transistor 13 of the second reference voltage setting means 38. . The drain of the fourth transistor 13 is connected to the first power supply terminal 33, and the gate is connected to the second reference voltage 29 which is a limit voltage.

  Reference numeral 31 denotes a second current mirror as an active load of the second differential amplifier 27. The second current mirror 31 includes a diode-coupled transistor 14 and a transistor having a gate connected to the gate of the transistor 14. 15, the gate and drain of the transistor 14 are connected to the drain of the sixth transistor 8, and the source is connected to the second power supply terminal 34. The drain of the transistor 15 is connected to the drain of the seventh transistor 9, and the source is connected to the second power supply terminal 34.

  Reference numeral 7 denotes a third transistor for output limitation. The gate of the third transistor 7 is connected to the drain of the seventh transistor 9 that is the output of the second differential amplifier 27, and the source is the third transistor. The source of one transistor 5, the gate of the second transistor 6, and the first constant current source 21 are connected, and the drain is connected to the first power supply terminal 33.

  The limiter means includes at least the third transistor 7, the second differential amplifier 27, and the second reference voltage setting means 38.

  Further, in the signal output circuit, a limiter releasing means 35 is provided in the limiter means, and an output saturation means 36 is provided in the first differential amplifier 26.

  The limiter canceling means 35 is composed of a fifth transistor 16 connected in parallel to the fourth transistor 13, and the output saturation means 36 is between the first reference voltage setting means 28 and the first power supply terminal 33. The tenth transistor 17 is provided. The limiter canceling means 35 and the output saturation means 36 are controlled by an abnormality detecting means 37.

  The abnormality detection means 37 generates a control signal when an excessive or abnormal disturbance (vibration, electromagnetic wave, etc.) is applied to the sensor, for example, during a period until the output reaches a stable region when the sensor is activated. is there.

  Next, the operation of the signal output circuit of this embodiment will be described.

  Since the sum of the current flowing from the drain of the transistor 3 to the drain of the transistor 1 and the current flowing from the drain of the transistor 4 to the drain of the transistor 2 is kept constant, the input inputted to the gate of the transistor 1 When the signal increases, the drain voltage of the transistor 2 that is the output of the first differential amplifier 26 increases. Since the drain voltage and the gate voltage of the first transistor 5 are the same potential, the source voltage of the transistor 5 increases and the drain voltage of the second transistor 6 decreases. As a result, the output voltage at the output terminal 32 decreases.

  Here, when the output voltage is lower than the second reference voltage 29, which is the limit voltage, when the output voltage decreases, the gate voltage of the transistor 12 decreases, and the gate voltage of the sixth transistor 8 becomes the gate voltage of the transistor 12. Decreases in conjunction.

  A second reference voltage 29 that is a limit voltage given to the gate of the fourth transistor 13 is given as a gate voltage of the seventh transistor 9.

  Therefore, the drain voltage of the seventh transistor 9 which is the output of the second differential amplifier 27, that is, the gate voltage of the third transistor 7 decreases, and in conjunction with this, the source voltage of the third transistor 7, ie, The gate voltage of the second transistor 6 decreases, and the drain voltage of the second transistor 6 increases to the second reference voltage 29 that is the limit voltage.

  As a result, even if an input voltage that causes the output voltage to be equal to or lower than the second reference voltage 29 is input, the output voltage does not become lower than the second reference voltage 29 but is maintained at the second reference voltage 29. . At this time, the first and third transistors 5 and 7 are connected to both sources and drains, and since the source voltage is common, the third transistor 7 is turned on and the first transistor 5 is turned off. The output of the first differential amplifier 26 is cut off and does not affect the output voltage.

  On the other hand, when the output voltage is larger than the second reference voltage 29, which is a limit voltage, the first and third transistors 5 and 7 have the same source voltage. Therefore, the third transistor 7 is off and the first transistor 5 is turned on, the output of the second differential amplifier 27 is cut off, and the output voltage is not affected.

  As described above, since the output voltage output from the output terminal 32 does not become lower than the second reference voltage, the output voltage is set to 0 V in a normal state by setting the second reference voltage to a value larger than 0 V. Is no longer. Therefore, when the output voltage is 0 V, the power receiving side circuit can determine that a disconnection or a short circuit to the ground potential has occurred.

In addition, the voltage at which the output voltage limiter operates, that is, the limit voltage is accurate and can supply a stable voltage with respect to temperature, etc., and the limit voltage can be easily changed by simply changing the second reference voltage 29. Can be changed.

  By the way, when the input voltage input to the gate of the transistor 1 rises and the output voltage tends to fall below the second reference voltage 29 which is the limit voltage, the limiter is applied from the abnormality detection means 37 to the gate of the fifth transistor 16. When the abnormality detection signal as the release signal is input, the fifth transistor 16 serving as the limiter release means 35 is turned on, thereby short-circuiting the source and drain of the fourth transistor 13, and as a result, The gate-source voltage of the fourth transistor 13 and the second reference voltage 29 are removed. Accordingly, the gate voltage of the seventh transistor 9 is adjusted by the level of the forward voltage of the transistor 16, that is, the gate-source voltage of the fourth transistor 13 and the second reference are higher than the level adjustment voltage of the sixth transistor 8. The level is adjusted by a voltage 29 lower. This corresponds to the fact that the apparent reference voltage is lowered by 29 minutes from the gate-source voltage of the fourth transistor 13 and the second reference voltage, and the output voltage is always larger than the second reference voltage 29 which is the limit voltage. It becomes a condition. At this time, the drain voltage of the seventh transistor 9 that is the output of the second differential amplifier 27, that is, the gate voltage of the third transistor 7 rises, and the source voltage of the third transistor 7 and the first transistor 5 is the source voltage. Since they are common, the third transistor 7 is in the off state and the first transistor 5 is in the on state, the output of the second differential amplifier 27 is cut off, and the output voltage is not affected. As a result, even if an input voltage that causes the output voltage to be equal to or lower than the second reference voltage 29 is input, output corresponding to the input is possible even in the region where the output voltage is equal to or lower than the second reference voltage 29.

  Further, the limiter canceling means 35 may have the following configuration. That is, as shown in FIG. 2, an eighth transistor 18 is provided, the source of the eighth transistor 18 is connected to the common source of the sixth and seventh transistors 8 and 9, and the drain is connected to the second power supply terminal. 34, and the gate is connected to the output of the abnormality detection means 37.

  Furthermore, a configuration as shown in FIG. That is, the ninth transistor 19 is provided, the source of the ninth transistor 19 is connected to the gate of the third transistor 7, the drain is connected to the second power supply terminal 34, and the gate is the output of the abnormality detection means 37. Is connected to. 2 and 3, the third transistor 7 and the first transistor 5 share the same source voltage as in FIG. 1, so that the third transistor 7 is off and the first transistor 5 is on. The output of the second differential amplifier 27 is cut off and does not affect the output voltage. As a result, even if an input voltage that causes the output voltage to be equal to or lower than the second reference voltage 29 is input, output corresponding to the input is possible even in the region where the output voltage is equal to or lower than the second reference voltage 29.

  Here, when the abnormality detection output of the abnormality detection means 37 is simultaneously given to the gate of the tenth transistor 17 of the output saturation means 36 and the gate of the fifth transistor 16 of the limiter cancellation means 35, the limiter is released as described above. Furthermore, since the tenth transistor 17 is turned on and the gate of the transistor 2 is grounded to the first power supply terminal 33, the input voltage input to the gate of the transistor 1 is always higher than the gate voltage of the transistor 2. Therefore, the drain voltage of the transistor 2 that is the output of the first differential amplifier 26 increases, and the gate voltage of the first transistor 5 that has the same potential also increases, so the source voltage of the first transistor 5 also increases. . As a result, the drain voltage of the second transistor 6 decreases, and the output voltage of the output terminal 32 also decreases. Since the output voltage of the output terminal 32 further decreases from the gate voltage of the transistor 2, the output voltage is fixed to the ground potential.

By adopting the configuration as described above, since an output similar to a voltage due to disconnection or short-circuit to the ground potential can be obtained at the time of abnormality detection, it is possible to connect via the signal output terminal 32 without providing a separate abnormality detection terminal. Information of abnormality detection can be transmitted to the power receiving side circuit.

  In this embodiment, the signal output circuit is not provided with level adjusting means, but may be provided as necessary. For example, as shown in FIG. 4, diode-coupled transistors 10 and 11 are used between the sixth transistor 8 and the transistor 12, and between the seventh transistor 9 and the fourth transistor 13, respectively. You may let them.

  The same effect can be obtained even if a bipolar transistor is used instead of the transistor used in this embodiment (not shown). In this case, the source corresponds to the emitter, the drain corresponds to the collector, and the gate corresponds to the base.

  In addition, as shown in FIG. 5, the upper limit of the output voltage can be defined when the PN of all transistors in FIG. 1 is inverted. That is, in the signal output circuit of the present invention, the limit voltage, that is, the lower limit voltage is set by the second reference voltage setting means 38, but the upper limit voltage can be set similarly. Thus, there is an effect that a short circuit to the power supply terminal can be detected without providing a detection circuit. In this case, the same effect can be obtained even if the bipolar transistor is used as described above.

  In the above embodiment, the sensor is used as means for inputting a signal to the signal output circuit, but the present invention is not limited to this.

  The signal output circuit of the present invention can detect a wire breakage, a short circuit to a ground potential, or a short circuit to a power supply potential without providing a separate detection circuit on the power receiving side, and is particularly useful as a signal output circuit for a sensor or the like. It is.

Signal output circuit diagram of one embodiment of the present invention Same signal output circuit diagram Same signal output circuit diagram Same signal output circuit diagram Same signal output circuit diagram Conventional signal output circuit diagram

Explanation of symbols

1, 2, 3, 4, 10, 11, 12, 14, 15 Transistor 5 1st transistor 6 2nd transistor 7 3rd transistor 8 6th transistor 9 7th transistor 13 4th transistor 16 4th 5 transistor 17 10th transistor 18 8th transistor 19 9th transistor 20, 24, 25 constant current source 21 1st constant current source 22 2nd constant current source 23 3rd constant current source 26 1st Differential amplifier 27 second differential amplifier 28 first reference voltage setting means 29 second reference voltage 30 first active load 31 second active load 32 output terminal 33 first power supply terminal 34 second Power supply terminal 35 Limiter releasing means 36 Output saturation means 37 Abnormality detecting means 38 Second reference voltage setting means

Claims (9)

A first differential amplifier having an input signal applied to one input terminal and a first reference voltage setting means connected to the other input terminal; and a first active load provided in the first differential amplifier; ,
A first transistor having a gate connected to an output terminal of the first differential amplifier and a first constant current source connected to a source;
A second transistor having a gate connected to a connection point between the first transistor and the first constant current source, and a drain connected to a second constant current source and an output terminal;
One working terminal is connected to a connection point between the first transistor and the first constant current source, and the output voltage corresponding to the input signal at the output terminal exceeds a predetermined limit voltage. By bypassing the current flowing through the transistor through the working terminal and controlling the potential at the connection point of the first transistor and the first constant current source, the output voltage at the output terminal maintains the predetermined limit voltage. Configured limiter means;
A limiter canceling unit provided in the limiter unit, which disables the control by the limiter unit so as to output the output voltage according to the input signal even in a range exceeding the predetermined limit voltage by a limiter canceling signal; ,
When the limiter releasing means is activated and an abnormality detection output signal generated when an abnormality is detected is applied, the output voltage is held at a voltage set in a range exceeding the predetermined limit voltage. A signal output circuit comprising output saturation means for controlling one differential amplifier. The limiter means connects the output terminal to one input terminal and the second differential amplifier to which the second reference voltage setting means for setting a limit voltage is connected to the other input terminal, and the second difference amplifier. A second active load provided in the dynamic amplifier;
2. The system according to claim 1, further comprising: a third transistor having a gate connected to an output terminal of the second differential amplifier and a source serving as a working terminal connected to a connection point between the first transistor and the first constant current source. The signal output circuit described. The second reference voltage setting means includes a fourth transistor having a source connected to the other input terminal of the second differential amplifier and a drain connected to the ground potential, and the other input of the second differential amplifier. A current supply source connected to a connection point between the end and the source of the fourth transistor;
3. The signal output circuit according to claim 2, comprising a second reference voltage source connected to the gate of the fourth transistor. The second differential amplifier includes source-coupled sixth and seventh transistors;
3. The signal output circuit according to claim 2, comprising a third constant current source connected to sources of the sixth and seventh transistors. The limiter canceling means is composed of a fifth transistor having a drain connected to the source of the fourth transistor of the second reference voltage setting means, a source connected to the ground potential, and a gate serving as an input terminal for the limiter canceling signal. The signal output circuit according to claim 3. The limiter canceling means connects the source to the common source of the sixth and seventh transistors constituting the second differential amplifier, connects the drain to the power supply potential, and uses the gate as the input terminal for the limiter cancel signal. 5. The signal output circuit according to claim 4, wherein the signal output circuit is constituted by a transistor. The limiter canceling means comprises a ninth transistor having a source connected to a gate of a third transistor constituting the limiter means, a drain connected to a power supply potential, and a gate serving as an input terminal for a limiter canceling signal. The signal output circuit described. The output saturation means has a drain connected to an input terminal to which the first reference voltage of the first differential amplifier is input, a source connected to a ground potential, and a gate serving as an input terminal for the abnormality detection output signal. The signal output circuit according to claim 1, comprising 10 transistors. The limiter means is
An output terminal is connected to one input terminal via a first level adjusting means for making a transition for a predetermined voltage, and a second reference voltage setting means for setting a limit voltage is connected to the other input terminal for a predetermined voltage. A second differential amplifier connected via second level adjusting means for performing a transition; a second active load provided in the second differential amplifier;
2. The system according to claim 1, further comprising: a third transistor having a gate connected to an output terminal of the second differential amplifier and a source serving as a working terminal connected to a connection point between the first transistor and the first constant current source. The signal output circuit described.

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