JP3995660B2 - display - Google Patents

Description

  The present invention relates to a display as information display means, and more particularly to a dual view display in which different images appear when viewed from different directions.

  Conventionally, in order to share a single display with a plurality of viewers, a technology for switching a video signal to be displayed according to the rotation angle of the display (see Patent Document 1), and a vehicle-mounted display near the center of an automobile windshield Various techniques (see Patent Document 2) for ensuring high visibility from any seat by hanging from the ceiling are disclosed and proposed.

  However, in the display described in the above document, when the information requested by a plurality of viewers is different from each other, information cannot be provided to each of them simultaneously.

  Therefore, conventionally, in a vehicle-mounted display or the like used in a car navigation system or the like, in view of the fact that a viewer on the driver's seat and a viewer on the passenger's seat see one display from different directions, A display panel composed of a first pixel that outputs the image light and a second pixel that outputs the image light for the second visual direction, and is disposed on the front surface of the display panel and is output from the first and second pixels. And a dual-view display capable of simultaneously displaying different images for a plurality of viewers. Has been disclosed and proposed (see, for example, Patent Document 3).

In addition, as related arts related to the above, video display means for alternately outputting video light for the left eye and right eye, and optical separation means for separating each video light corresponding to the left and right eyes, Various stereoscopic video display devices are disclosed and proposed (see, for example, Patent Document 4).
Japanese Patent Laid-Open No. 2-144242 Registered Utility Model No. 3045443 JP 2003-76289 A JP 2003-295113 A

  Certainly, the dual view display having the above-described configuration can simultaneously display different images for a plurality of viewers, so that the sharing of a single display can be enhanced.

  However, the conventional dual view display always outputs video light for the first visual direction without considering whether it is necessary to output video in a plurality of directions when driving the display panel. The first pixel and the second pixel that outputs the image light for the second visual direction are driven. For this reason, there is a problem that power is wasted when the display is viewed from only one direction.

  In view of the above problems, an object of the present invention is to provide a display capable of simultaneously displaying different images for a plurality of viewers while suppressing waste of power.

  In order to achieve the above object, a display according to the present invention includes a display panel including a first pixel that outputs video light for a first visual direction and a second pixel that outputs video light for a second visual direction; A first driving circuit for driving the first pixel, a second driving circuit for driving the second pixel, and video light output from the first and second pixels arranged on the front surface of the display panel are respectively And at least one of the first and second drive circuits shifts a start pulse by a clock signal to generate a sampling pulse. A register, a sampling circuit that samples a video signal in response to the sampling pulse, and a switch that controls whether the clock signal can be input to the shift register in response to a switching signal. When comprises a first by using the output signal of said sampling circuit, and configured to drive the second pixel.

  In addition, the display according to the present invention drives a display panel including a first pixel that outputs video light for the first visual direction and a second pixel that outputs video light for the second visual direction, and the first pixel. A first driving circuit for driving the second pixel, a second driving circuit for driving the second pixel, and image light output from the first and second pixels arranged in front of the display panel in the first and second visual directions, respectively. And at least one of the first and second drive circuits, a shift register for generating a sampling pulse by shifting a start pulse with a clock signal, and the sampling A sampling circuit that samples a video signal according to a pulse; and a switch that controls whether the start pulse can be input to the shift register according to a switching signal. Ri, by using the output signal of the sampling circuit, the first, may be configured to drive the second pixel.

  With such a configuration, when the display is viewed from only one direction, or when viewed from neither direction, it is unnecessary in the shift register that configures the first drive circuit and / or the second drive circuit. Since sampling pulse generation can be stopped, it is possible to simultaneously display different videos for a plurality of viewers while suppressing waste of power.

  In the display configured as described above, at least one of the first and second drive circuits includes a logic gate circuit that generates a logical sum signal of the sampling pulse and the switching signal, and the video corresponding to the switching signal. And a selector that sends either a signal or a non-display signal to the sampling circuit, and the sampling circuit may be configured to sample the output signal of the selector in accordance with the logical sum signal. . With such a configuration, even when one of the first and second pixels is in a normal driving state and the other is in a non-driving state, the potential level of the source line corresponding to the non-driving pixel is Since the state is not unstable, adverse effects on the display can be avoided.

  In the display configured as described above, the display panel includes a first source line to which an output signal of the first drive circuit is supplied, a second source line to which an output signal of the second drive circuit is supplied, and a first source line. A gate line intersecting the second source line, an active element having a source connected to one of the first and second source lines, a gate connected to the gate line, and a drain connected to the pixel electrode; It is preferable to adopt an active matrix type structure including a plurality of. By adopting such a configuration, each pixel can be turned on more reliably than when a simple matrix type display panel is used, so that a clear and high-response display screen can be realized. It becomes.

  In the display configured as described above, each of the first and second pixels is divided into a plurality of picture elements, and the selector includes a plurality of input video signals corresponding to the plurality of divided picture elements. It may be configured to send any one of the non-display signals to the sampling circuit. With such a configuration, it is possible to improve the definition of the display panel and enhance the display power of the display screen.

  As described above, with the display according to the present invention, it is possible to simultaneously display different videos for a plurality of viewers while suppressing waste of power.

  FIG. 1 is a schematic configuration diagram of a dual view display according to the present invention. As shown in the figure, the display according to the present invention includes a first pixel a that outputs video light for the first visual direction (video light for the viewer V1) and video light for the second visual direction (viewer V2). Display panel 1 including a second pixel b that outputs a first image line), a first source line driver circuit 2a that supplies a source signal to the first pixel a, and a first source signal that supplies a source signal to the second pixel b 2 source line driving circuit 2b, a gate line driving circuit 3 for supplying gate signals to the first and second pixels a and b, and an output from the first and second pixels a and b disposed on the front surface of the display panel 1. And an optical separation unit 4 (slit in the present embodiment) for separating the image light corresponding to the first and second visual directions, respectively.

  In the display configured as described above, only the video light output from the first pixel a is transmitted in the first visual direction (the direction in which the viewer V1 exists), and the video light output from the second pixel b is blocked. Is done. On the other hand, in the second visual direction (the direction in which the viewer V2 exists), only the image light output from the second pixel b is transmitted, and the image light output from the first pixel a is blocked. Accordingly, the viewers V1 and V2 can simultaneously view different videos.

  Here, the display configured as described above has a characteristic portion (difference from the conventional configuration) in the internal configuration of the first and second source line driving circuits 2a and 2b. Therefore, in the following, the internal configuration of the first and second source line drive circuits 2a and 2b will be described in detail with reference to FIGS.

  FIG. 2 is a circuit diagram showing a first embodiment of the first source line driving circuit 2a. Note that the second source line driving circuit 2b has the same configuration, and thus the description thereof is omitted.

As shown in the figure, the first source line drive circuit 2a of the present embodiment includes a shift register 21 that generates sampling pulses P1 to Pm by shifting the start pulse XSP by the clock signal XSC, and sampling pulses P1 to Pm 2 A logic gate circuit 22 that generates a logical sum signal with a value (high level / low level) switching signal SLT, and a video signal VS (analog signal for performing normal image display) and non-display according to the switching signal SLT A selector 23 that sends out one of the signals ND (black signal in the present embodiment), a sampling circuit 24 that samples the output signal of the selector 23 according to the logical sum signal, and sampling according to the output pulse OE A hold circuit 25 that holds the output signal of the circuit 24 and a shift register 21 in response to the switching signal SLT Become has a switch 26 for controlling the input whether the clock signal XSC, and has a configuration for driving the first pixel a ₁₁ ~a _mn using the output signal of the sampling circuit 24 which is held in the hold circuit 25.

  The logic gate circuit 22 includes m number of OR circuits OR1 to ORm to which sampling pulses P1 to Pm are supplied at one input terminal and a switching signal SLT is supplied to the other input terminal.

  The sampling circuit 24 has an input terminal connected to the output terminal of the selector 23, and analog switches S11 to S1m that are controlled to open and close according to the logical sum signal, and output terminals of the analog switches S11 to S1m and a common electrode (for example, ground And sampling capacitors C11 to C1m connected to each other) and buffers B11 to B1m connected to the output ends of the analog switches S11 to S1m.

  The hold circuit 25 includes analog switches S21 to S2m whose input ends are connected to the output ends of the buffers B11 to B1m and controlled to open and close according to the output pulse OE, and the output ends of the analog switches S21 to S2m and a common electrode For example, hold capacitors C21 to C2m connected to the ground electrode) and buffers B21 to B2m connected to the output terminals of the analog switches S21 to S2m.

  On the other hand, in the display of the present embodiment, an active matrix type panel (for example, a TFT [Thin Film Transistor] liquid crystal panel) is used as the display panel 1. More specifically, the display panel 1 includes the m first source lines Xa1 to Xam to which the output signal of the first source line driving circuit 2a (the output signal of the hold circuit 25) is supplied, and the second source line driving. It has m second source lines Xb1 to Xbm to which the output signal of the circuit 2b is supplied, and n gate lines Y1 to Yn intersecting the first and second source lines.

Near each intersection of the first source lines Xa1 to Xam and the gate lines Y1 to Yn, (m × n) first pixels a _{11 to} a _mn are formed, and the second source lines Xb1 to Xbm and the gate are formed. Near each intersection of the lines Y1 to Yn, (m × n) second pixels b _{11 to} b _mn are formed. Each of the first pixels a _{11 to} a _mn has an active element having a source connected to the first source lines Xa 1 to Xam, a gate connected to the gate lines Y 1 to Yn, and a drain connected to the pixel electrode. Become. The second pixels b _{11 to} b _mn have active elements each having a source connected to the second source lines Xb 1 to Xbm, a gate connected to the gate lines Y 1 to Yn, and a drain connected to the pixel electrode. It consists of

  In this way, by using an active matrix type panel as the display panel 1, individual pixels can be lighted more reliably than when a simple matrix type is used, and a clear and high-response display screen is realized. It becomes possible to do.

The operation of the first source line driver circuit 2a having the above structure, first described in detail for the case of the first pixel a ₁₁ ~a _mn the normal driving state.

  In this case, the signal level of the switching signal SLT is changed to a low level. As a result, the switch 26 is closed and the input of the clock signal XSC to the shift register 21 is permitted. Therefore, the shift register 21 generates the sampling pulses P1 to Pm. When the signal level of the switching signal SLT is changed to the low level, the output signals of the OR circuits OR1 to ORm are the sampling pulses P1 to Pm obtained by the shift register 21 themselves. Further, the selector 23 selectively outputs the video signal VS to the sampling circuit 24 in accordance with the switching signal SLT.

Therefore, in the case of the first pixel a ₁₁ ~a _mn the normal driving state, the sampling pulse P1~Pm is supplied to the analog switch S11~S1m sampling circuit 24, the analog switch S11~S1m and a sequentially conducting state Is done. As a result, the sampling capacitors C11 to C1m are sequentially charged with the instantaneous amplitude of the video signal VS.

  As described above, when the sampling capacitors C11 to C1m are sequentially charged and the video signal VS in one horizontal scanning period is sampled by the sampling pulses P1 to Pm, the output pulse OE is supplied to the hold circuit 25. The As a result, the analog switches S21 to S2m of the hold circuit 25 are closed simultaneously, and the video signal VS charged in the sampling capacitors C11 to C1m is transferred to the hold capacitors C21 to C2m via the buffers B11 to B1m. Will be retained. The video signal VS held in the hold capacitors C21 to C2m is supplied to the corresponding first source lines Xa1 to Xam via the buffers B21 to B2m.

  On the other hand, the gate line driving circuit 3 supplies a scanning signal synchronized with the horizontal synchronizing signal of the video signal VS to the gate lines Y1 to Yn, so that the pixels connected to the same gate line are turned on line by line.

With the above operation, the display panel 1, the first pixel a ₁₁ ~a _mn is the normal driving state, the image light for the first visual direction (the image light for the viewer V1) is output.

Next, the case where the first pixels a _{11 to} a _mn are set to the non-driven state (that is, the case where the display is viewed only from the second visual direction or the direction where the display is not viewed from any direction) will be described in detail.

In this case, the signal level of the switching signal SLT is changed to a high level. As a result, the switch 26 is opened, and the input of the clock signal XSC to the shift register 21 is prohibited. When the signal level of the switching signal SLT is changed to the high level, the output signals of the OR circuits OR1 to ORm are always at the high level regardless of the output signal of the shift register 21. Accordingly, when the first pixels a _{11 to} a _mn are not driven, all the analog switches S11 to S1m are turned on. In the selector 23, the non-display signal ND is selectively output to the sampling circuit 24 in accordance with the switching signal SLT. As a result, the non-display signal ND is charged in the sampling capacitors C11 to C1m.

  When the charging of the sampling capacitors C11 to C1m is completed as described above, the output pulse OE is supplied to the hold circuit 25. As a result, the analog switches S21 to S2m of the hold circuit 25 are closed simultaneously, and the non-display signal ND charged in the sampling capacitors C11 to C1m is transferred to the hold capacitors C21 to C2m via the buffers B11 to B1m. Will be held. The non-display signal ND held in the hold capacitors C21 to C2m is supplied to the corresponding first source lines Xa1 to Xam via the buffers B21 to B2m.

  On the other hand, the gate line driving circuit 3 supplies a scanning signal synchronized with the horizontal synchronizing signal of the video signal VS to the gate lines Y1 to Yn, so that the pixels connected to the same gate line are turned on line by line.

With the above operation, in the display panel 1, the first pixels a _{11 to} a _mn are not driven, and only black display is performed in the first visual direction.

As described above, in the display of the present embodiment, a first source line driver circuit 2a supplies a source signal to the first pixel a ₁₁ ~a _mn, supplies source signal to the second pixel b ₁₁ ~b _mn first At least one of the two source line driving circuits 2b shifts the start pulse XSP with the clock signal XSC to generate sampling pulses P1 to Pm, and performs sampling to sample the video signal VS according to the sampling pulses P1 to Pm. The circuit 24 and a switch 26 that controls whether or not the clock signal XSC can be input to the shift register 21 in response to the binary switching signal SLT. The first and second signals are output using the output signal of the sampling circuit 24. The pixels a _{11 to} a _mn and b _{11 to} b _mn are driven.

  With such a configuration, the first source line driving circuit 2a and / or the second source line driving circuit 2b are configured when the display is viewed from only one direction or when viewed from neither direction. Since unnecessary sampling pulse generation in the shift register 21 can be stopped, it is possible to simultaneously display different videos for a plurality of viewers while suppressing waste of power.

However, in the display having the above configuration, when any one of the first and second pixels a _{11 to} a _mn and b _{11 to} b _mn is in the normal driving state and the other is in the non-driving state, the non-driving state is set. If some potential is not applied to the pixels, the potential levels of the source lines Y1 to Yn corresponding to the non-driven pixels become unstable, which adversely affects the display (active element on / off malfunctions and , There is a risk of display quality deterioration due to a leakage current to a pixel in which the active element is turned off.

  Therefore, in the display of the present embodiment, in view of the above problems, at least one of the first and second source line driving circuits 2a and 2b generates a logical sum signal of the sampling pulses P1 to Pm and the switching signal SLT. A logic gate circuit 22; and a selector 23 for sending either the video signal VS or the non-display signal ND to the sampling circuit 24 in response to the switching signal SLT. The output signal of the selector 23 is sampled according to the above.

With such a configuration, even when one of the first and second pixels a _{11 to} a _mn and b _{11 to} b _mn is in a normal driving state and the other is in a non-driving state, Since the potential levels of the source lines Y1 to Yn corresponding to the drive pixels do not become unstable, adverse effects on the display can be avoided.

In this embodiment, the case where the black signal is supplied as the non-display signal ND has been described as an example. However, the configuration of the present invention is not limited to this, and other signals (white signal) Etc.) may be provided. However, first, second source line driver circuit 2a, 2b and the first and the second pixel _{a 11 ~a mn, b 11 ~b} mn are prevented from becoming a high impedance state, as a hidden signal ND It is desirable to supply a voltage signal of a predetermined level or higher.

  In the present embodiment, the switch 26 that controls whether the clock signal XSC can be input to the shift register 21 according to the switching signal SLT has been described as an example. However, the configuration of the present invention is not limited to this. Instead, as shown in FIG. 3, the same effect as described above can be obtained even if a switch 27 is provided for controlling whether or not the start pulse XSP can be input to the shift register 21 in accordance with the switching signal SLT. Is possible.

Further, in the present embodiment, first, second pixel a ₁₁ ~a _mn, b ₁₁ but ~b _mn has been described as an example when configured for each one pixel, the configuration of the present invention However, as shown in FIG. 4, each of the first and second pixels a _{11 to} a _mn and b _{11 to} b _mn is divided into a plurality of picture elements (for example, picture element a _{11 -1 to} a _11-3 and picture elements b _{11-1 to} b _11-3 , etc., and the selector 23 receives a plurality of input video signals corresponding to the divided picture elements. One of the VS1 to VS3 and the non-display signal ND may be sent to the sampling circuit 24. With such a configuration, it is possible to improve the definition of the display panel 1 and enhance the display power of the display screen. Of course, the number of divisions of the first and second pixels a _{11 to} a _mn and b _{11 to} b _mn is arbitrary, and it may be divided into two picture elements or four picture elements or more.

  In the present embodiment, the case where the sampling circuit 24 and the hold circuit 25 are included as constituent elements of the first source line driving circuit 2a and the second source line driving circuit 2b has been described as an example. The configuration of the present invention is not limited to this, and the sampling circuit 24 is included, but the hold circuit 25 may not be included. Furthermore, the sampling circuit 24 and the hold circuit 25 are not limited to analog video signals having sampling capacitors C11 to C1m and hold capacitors C21 to C2m, but may be for digital video signals.

  The present invention can be suitably used for a dual view display or the like in which different images appear when one display is viewed from different directions.

These are the schematic block diagrams of the dual view display which concerns on this invention. These are the circuit diagrams which show 1st Embodiment of the source line drive circuit 2a. These are the circuit diagrams which show 2nd Embodiment of the source line drive circuit 2a. These are the circuit diagrams which show 3rd Embodiment of the source line drive circuit 2a.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display panel 2a, 2b 1st, 2nd source line drive circuit 3 Gate line drive circuit 4 Optical separation part (slit)
V1, V2 Viewer 21 Shift register 22 Logic gate circuit 23 Selector 24 Sampling circuit 25 Hold circuit 26, 27 Switch OR1-ORm OR circuit S11-S1m, S21-S2m Analog switch B11-B1m, B21-B2m Buffer C11-C1m the sampling capacitor C21~C2m hold capacitor a ₁₁ ~a _mn first pixel (for first visual direction)
b _{11 to} b _mn second pixel (for second visual direction)
Xa1 to Xam first source line (for first visual direction)
Xb1 to Xbm second source line (for second visual direction)
Y1 to Yn Gate line XSC clock signal XSP start pulse P1 to Pm Sampling pulse SLT switching signal VS Video signal ND Non-display signal (black signal)
OE output pulse

Claims (3)

A display panel including a first pixel that outputs video light for the first visual direction and a second pixel that outputs video light for the second visual direction; a first drive circuit that drives the first pixel; A second driving circuit for driving the pixels, and an optical separating unit disposed on the front surface of the display panel and separating the image light output from the first and second pixels in correspondence with the first and second visual directions, respectively. In a display comprising:
At least one of the first and second drive circuits includes a shift register that generates a sampling pulse by shifting a start pulse with a clock signal, and a switch that controls whether the clock signal can be input to the shift register according to a switching signal. A logic gate circuit for generating a logical sum signal of the sampling pulse and the switching signal, a selector for transmitting either a video signal or a non-display signal in response to the switching signal, and a response in accordance with the logical sum signal A sampling circuit that samples the output signal of the selector, and drives the first and second pixels using the output signal of the sampling circuit ,
The display panel includes a first source line to which an output signal of the first drive circuit is supplied, a second source line to which an output signal of the second drive circuit is supplied, and a gate that intersects the first and second source lines. Active matrix type comprising a plurality of active elements each having a line, a source connected to one of the first and second source lines, a gate connected to the gate line, and a drain connected to the pixel electrode The display characterized by being. A display panel including a first pixel that outputs video light for the first visual direction and a second pixel that outputs video light for the second visual direction; a first drive circuit that drives the first pixel; A second driving circuit for driving the pixels, and an optical separating unit disposed on the front surface of the display panel and separating the image light output from the first and second pixels in correspondence with the first and second visual directions, respectively. In a display comprising:
At least one of the first and second drive circuits includes a shift register that generates a sampling pulse by shifting a start pulse with a clock signal, and a switch that controls whether the start pulse can be input to the shift register according to a switching signal. A logic gate circuit for generating a logical sum signal of the sampling pulse and the switching signal, a selector for transmitting either a video signal or a non-display signal in response to the switching signal, and a response in accordance with the logical sum signal A sampling circuit that samples the output signal of the selector, and drives the first and second pixels using the output signal of the sampling circuit ,
The display panel includes a first source line to which an output signal of the first drive circuit is supplied, a second source line to which an output signal of the second drive circuit is supplied, and a gate that intersects the first and second source lines. Active matrix type comprising a plurality of active elements each having a line, a source connected to one of the first and second source lines, a gate connected to the gate line, and a drain connected to the pixel electrode The display characterized by being. Each of the first and second pixels is divided into a plurality of picture elements, and the selector receives one of a video signal and a non-display signal that are inputted in correspondence with the plurality of divided picture elements. The display according to claim 1 , wherein the display is sent to the sampling circuit .

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